Macros | Functions
mpu.h File Reference

SAMV70/SAMV71/SAME70/SAMS70-XULTRA board mpu config. More...

#include "compiler.h"
Include dependency graph for mpu.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define ARM_MODE_USR   0x10
 
#define DTCM_END_ADDRESS   0x203FFFFFUL
 
#define DTCM_START_ADDRESS   0x20000000UL
 
#define EXT_EBI_END_ADDRESS   0x6FFFFFFFUL
 
#define EXT_EBI_START_ADDRESS   0x60000000UL
 
#define IFLASH_END_ADDRESS   0x005FFFFFUL
 
#define IFLASH_PRIVILEGE_END_ADDRESS   (IFLASH_START_ADDRESS + 0xFFF)
 
#define IFLASH_PRIVILEGE_START_ADDRESS   (IFLASH_START_ADDRESS)
 
#define IFLASH_START_ADDRESS   0x00400000UL
 
#define IFLASH_UNPRIVILEGE_END_ADDRESS   (IFLASH_END_ADDRESS)
 
#define IFLASH_UNPRIVILEGE_START_ADDRESS   (IFLASH_PRIVILEGE_END_ADDRESS + 1)
 
#define INNER_NORMAL_WB_NWA_TYPE(x)   (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
 
#define INNER_NORMAL_WB_RWA_TYPE(x)   (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
 
#define ITCM_END_ADDRESS   0x003FFFFFUL
 
#define ITCM_START_ADDRESS   0x00000000UL
 
#define MPU_AP_FULL_ACCESS   ( 0x03 << MPU_RASR_AP_Pos )
 
#define MPU_AP_NO_ACCESS   ( 0x00 << MPU_RASR_AP_Pos )
 
#define MPU_AP_PRIVILEGED_READ_WRITE   ( 0x01 << MPU_RASR_AP_Pos )
 
#define MPU_AP_PRIVILEGED_READONLY   ( 0x05 << MPU_RASR_AP_Pos )
 
#define MPU_AP_READONLY   ( 0x06 << MPU_RASR_AP_Pos )
 
#define MPU_AP_READONLY2   ( 0x07 << MPU_RASR_AP_Pos )
 
#define MPU_AP_RES   ( 0x04 << MPU_RASR_AP_Pos )
 
#define MPU_AP_UNPRIVILEGED_READONLY   ( 0x02 << MPU_RASR_AP_Pos )
 
#define MPU_DEFAULT_DTCM_REGION   ( 3 )
 
#define MPU_DEFAULT_IFLASH_REGION   ( 2 )
 
#define MPU_DEFAULT_ITCM_REGION   ( 1 )
 
#define MPU_DEFAULT_SDRAM_REGION   ( 8 )
 
#define MPU_DEFAULT_SRAM_REGION_1   ( 4 )
 
#define MPU_DEFAULT_SRAM_REGION_2   ( 5 )
 
#define MPU_ENABLE   ( 0x1 << MPU_CTRL_ENABLE_Pos)
 
#define MPU_EXT_EBI_REGION   ( 7 )
 
#define MPU_HFNMIENA   ( 0x1 << MPU_CTRL_HFNMIENA_Pos )
 
#define MPU_PERIPHERALS_REGION   ( 6 )
 
#define MPU_PRIVDEFENA   ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos )
 
#define MPU_QSPIMEM_REGION   ( 9 )
 
#define MPU_REGION_BUFFERABLE   ( 0x01 << MPU_RASR_B_Pos )
 
#define MPU_REGION_CACHEABLE   ( 0x01 << MPU_RASR_C_Pos )
 
#define MPU_REGION_DISABLE   ( 0x0 )
 
#define MPU_REGION_ENABLE   ( 0x01 )
 
#define MPU_REGION_EXECUTE_NEVER   ( 0x01 << MPU_RASR_XN_Pos )
 
#define MPU_REGION_SHAREABLE   ( 0x01 << MPU_RASR_S_Pos )
 
#define MPU_REGION_VALID   ( 0x10 )
 
#define MPU_TEX_B000   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_TEX_B001   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_TEX_B010   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_TEX_B011   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_TEX_B100   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_TEX_B101   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_TEX_B110   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_TEX_B111   ( 0x01 << MPU_RASR_TEX_Pos )
 
#define MPU_USBHSRAM_REGION   ( 10 )
 
#define NON_SHAREABLE   0
 
#define PERIPHERALS_END_ADDRESS   0x5FFFFFFFUL
 
#define PERIPHERALS_START_ADDRESS   0x40000000UL
 
#define PRIVILEGE_MODE   0
 
#define QSPI_END_ADDRESS   0x9FFFFFFFUL
 
#define QSPI_START_ADDRESS   0x80000000UL
 
#define SDRAM_END_ADDRESS   0x7FFFFFFFUL
 
#define SDRAM_START_ADDRESS   0x70000000UL
 
#define SHAREABLE   1
 
#define SHAREABLE_DEVICE_TYPE   (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ))
 
#define SRAM_END_ADDRESS   0x2045FFFFUL
 
#define SRAM_FIRST_END_ADDRESS   (SRAM_FIRST_START_ADDRESS + 0x3FFFF)
 
#define SRAM_FIRST_START_ADDRESS   (SRAM_START_ADDRESS)
 
#define SRAM_SECOND_END_ADDRESS   (SRAM_END_ADDRESS)
 
#define SRAM_SECOND_START_ADDRESS   (SRAM_FIRST_END_ADDRESS + 1)
 
#define SRAM_START_ADDRESS   0x20400000UL
 
#define STRONGLY_ORDERED_SHAREABLE_TYPE   (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ))
 
#define USBHSRAM_END_ADDRESS   0xA01FFFFFUL
 
#define USBHSRAM_START_ADDRESS   0xA0100000UL
 
#define USER_MODE   1
 

Functions

uint32_t mpu_cal_mpu_region_size (uint32_t dw_actual_size_in_bytes)
 Calculate region size for the RASR. More...
 
void mpu_disable_region (void)
 Disable the current active region. More...
 
void mpu_enable (uint32_t dw_mpu_enable)
 Enables the MPU module. More...
 
void mpu_set_region (uint32_t dw_region_base_addr, uint32_t dw_region_attr)
 Setup a memory region. More...
 
void mpu_set_region_num (uint32_t dw_region_num)
 Set active memory region. More...
 
void mpu_update_regions (uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr)
 Update MPU regions. More...
 

Detailed Description

SAMV70/SAMV71/SAME70/SAMS70-XULTRA board mpu config.

Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.

Definition in file mpu.h.

Macro Definition Documentation

◆ ARM_MODE_USR

#define ARM_MODE_USR   0x10

Definition at line 46 of file mpu.h.

◆ DTCM_END_ADDRESS

#define DTCM_END_ADDRESS   0x203FFFFFUL

Definition at line 134 of file mpu.h.

◆ DTCM_START_ADDRESS

#define DTCM_START_ADDRESS   0x20000000UL

Definition at line 133 of file mpu.h.

◆ EXT_EBI_END_ADDRESS

#define EXT_EBI_END_ADDRESS   0x6FFFFFFFUL

Definition at line 165 of file mpu.h.

◆ EXT_EBI_START_ADDRESS

#define EXT_EBI_START_ADDRESS   0x60000000UL

Definition at line 164 of file mpu.h.

◆ IFLASH_END_ADDRESS

#define IFLASH_END_ADDRESS   0x005FFFFFUL

Definition at line 123 of file mpu.h.

◆ IFLASH_PRIVILEGE_END_ADDRESS

#define IFLASH_PRIVILEGE_END_ADDRESS   (IFLASH_START_ADDRESS + 0xFFF)

Definition at line 127 of file mpu.h.

◆ IFLASH_PRIVILEGE_START_ADDRESS

#define IFLASH_PRIVILEGE_START_ADDRESS   (IFLASH_START_ADDRESS)

Definition at line 126 of file mpu.h.

◆ IFLASH_START_ADDRESS

#define IFLASH_START_ADDRESS   0x00400000UL

Definition at line 122 of file mpu.h.

◆ IFLASH_UNPRIVILEGE_END_ADDRESS

#define IFLASH_UNPRIVILEGE_END_ADDRESS   (IFLASH_END_ADDRESS)

Definition at line 130 of file mpu.h.

◆ IFLASH_UNPRIVILEGE_START_ADDRESS

#define IFLASH_UNPRIVILEGE_START_ADDRESS   (IFLASH_PRIVILEGE_END_ADDRESS + 1)

Definition at line 129 of file mpu.h.

◆ INNER_NORMAL_WB_NWA_TYPE

#define INNER_NORMAL_WB_NWA_TYPE (   x)    (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))

Definition at line 102 of file mpu.h.

◆ INNER_NORMAL_WB_RWA_TYPE

#define INNER_NORMAL_WB_RWA_TYPE (   x)    (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))

Definition at line 101 of file mpu.h.

◆ ITCM_END_ADDRESS

#define ITCM_END_ADDRESS   0x003FFFFFUL

Definition at line 121 of file mpu.h.

◆ ITCM_START_ADDRESS

#define ITCM_START_ADDRESS   0x00000000UL

Definition at line 120 of file mpu.h.

◆ MPU_AP_FULL_ACCESS

#define MPU_AP_FULL_ACCESS   ( 0x03 << MPU_RASR_AP_Pos )

Definition at line 83 of file mpu.h.

◆ MPU_AP_NO_ACCESS

#define MPU_AP_NO_ACCESS   ( 0x00 << MPU_RASR_AP_Pos )

Definition at line 80 of file mpu.h.

◆ MPU_AP_PRIVILEGED_READ_WRITE

#define MPU_AP_PRIVILEGED_READ_WRITE   ( 0x01 << MPU_RASR_AP_Pos )

Definition at line 81 of file mpu.h.

◆ MPU_AP_PRIVILEGED_READONLY

#define MPU_AP_PRIVILEGED_READONLY   ( 0x05 << MPU_RASR_AP_Pos )

Definition at line 85 of file mpu.h.

◆ MPU_AP_READONLY

#define MPU_AP_READONLY   ( 0x06 << MPU_RASR_AP_Pos )

Definition at line 86 of file mpu.h.

◆ MPU_AP_READONLY2

#define MPU_AP_READONLY2   ( 0x07 << MPU_RASR_AP_Pos )

Definition at line 87 of file mpu.h.

◆ MPU_AP_RES

#define MPU_AP_RES   ( 0x04 << MPU_RASR_AP_Pos )

Definition at line 84 of file mpu.h.

◆ MPU_AP_UNPRIVILEGED_READONLY

#define MPU_AP_UNPRIVILEGED_READONLY   ( 0x02 << MPU_RASR_AP_Pos )

Definition at line 82 of file mpu.h.

◆ MPU_DEFAULT_DTCM_REGION

#define MPU_DEFAULT_DTCM_REGION   ( 3 )

Definition at line 53 of file mpu.h.

◆ MPU_DEFAULT_IFLASH_REGION

#define MPU_DEFAULT_IFLASH_REGION   ( 2 )

Definition at line 52 of file mpu.h.

◆ MPU_DEFAULT_ITCM_REGION

#define MPU_DEFAULT_ITCM_REGION   ( 1 )

Definition at line 51 of file mpu.h.

◆ MPU_DEFAULT_SDRAM_REGION

#define MPU_DEFAULT_SDRAM_REGION   ( 8 )

Definition at line 58 of file mpu.h.

◆ MPU_DEFAULT_SRAM_REGION_1

#define MPU_DEFAULT_SRAM_REGION_1   ( 4 )

Definition at line 54 of file mpu.h.

◆ MPU_DEFAULT_SRAM_REGION_2

#define MPU_DEFAULT_SRAM_REGION_2   ( 5 )

Definition at line 55 of file mpu.h.

◆ MPU_ENABLE

#define MPU_ENABLE   ( 0x1 << MPU_CTRL_ENABLE_Pos)

Definition at line 69 of file mpu.h.

◆ MPU_EXT_EBI_REGION

#define MPU_EXT_EBI_REGION   ( 7 )

Definition at line 57 of file mpu.h.

◆ MPU_HFNMIENA

#define MPU_HFNMIENA   ( 0x1 << MPU_CTRL_HFNMIENA_Pos )

Definition at line 70 of file mpu.h.

◆ MPU_PERIPHERALS_REGION

#define MPU_PERIPHERALS_REGION   ( 6 )

Definition at line 56 of file mpu.h.

◆ MPU_PRIVDEFENA

#define MPU_PRIVDEFENA   ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos )

Definition at line 71 of file mpu.h.

◆ MPU_QSPIMEM_REGION

#define MPU_QSPIMEM_REGION   ( 9 )

Definition at line 59 of file mpu.h.

◆ MPU_REGION_BUFFERABLE

#define MPU_REGION_BUFFERABLE   ( 0x01 << MPU_RASR_B_Pos )

Definition at line 74 of file mpu.h.

◆ MPU_REGION_CACHEABLE

#define MPU_REGION_CACHEABLE   ( 0x01 << MPU_RASR_C_Pos )

Definition at line 75 of file mpu.h.

◆ MPU_REGION_DISABLE

#define MPU_REGION_DISABLE   ( 0x0 )

Definition at line 67 of file mpu.h.

◆ MPU_REGION_ENABLE

#define MPU_REGION_ENABLE   ( 0x01 )

Definition at line 66 of file mpu.h.

◆ MPU_REGION_EXECUTE_NEVER

#define MPU_REGION_EXECUTE_NEVER   ( 0x01 << MPU_RASR_XN_Pos )

Definition at line 78 of file mpu.h.

◆ MPU_REGION_SHAREABLE

#define MPU_REGION_SHAREABLE   ( 0x01 << MPU_RASR_S_Pos )

Definition at line 76 of file mpu.h.

◆ MPU_REGION_VALID

#define MPU_REGION_VALID   ( 0x10 )

Definition at line 65 of file mpu.h.

◆ MPU_TEX_B000

#define MPU_TEX_B000   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 89 of file mpu.h.

◆ MPU_TEX_B001

#define MPU_TEX_B001   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 90 of file mpu.h.

◆ MPU_TEX_B010

#define MPU_TEX_B010   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 91 of file mpu.h.

◆ MPU_TEX_B011

#define MPU_TEX_B011   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 92 of file mpu.h.

◆ MPU_TEX_B100

#define MPU_TEX_B100   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 93 of file mpu.h.

◆ MPU_TEX_B101

#define MPU_TEX_B101   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 94 of file mpu.h.

◆ MPU_TEX_B110

#define MPU_TEX_B110   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 95 of file mpu.h.

◆ MPU_TEX_B111

#define MPU_TEX_B111   ( 0x01 << MPU_RASR_TEX_Pos )

Definition at line 96 of file mpu.h.

◆ MPU_USBHSRAM_REGION

#define MPU_USBHSRAM_REGION   ( 10 )

Definition at line 60 of file mpu.h.

◆ NON_SHAREABLE

#define NON_SHAREABLE   0

Definition at line 99 of file mpu.h.

◆ PERIPHERALS_END_ADDRESS

#define PERIPHERALS_END_ADDRESS   0x5FFFFFFFUL

Definition at line 161 of file mpu.h.

◆ PERIPHERALS_START_ADDRESS

#define PERIPHERALS_START_ADDRESS   0x40000000UL

Definition at line 160 of file mpu.h.

◆ PRIVILEGE_MODE

#define PRIVILEGE_MODE   0

Definition at line 48 of file mpu.h.

◆ QSPI_END_ADDRESS

#define QSPI_END_ADDRESS   0x9FFFFFFFUL

Definition at line 173 of file mpu.h.

◆ QSPI_START_ADDRESS

#define QSPI_START_ADDRESS   0x80000000UL

Definition at line 172 of file mpu.h.

◆ SDRAM_END_ADDRESS

#define SDRAM_END_ADDRESS   0x7FFFFFFFUL

Definition at line 169 of file mpu.h.

◆ SDRAM_START_ADDRESS

#define SDRAM_START_ADDRESS   0x70000000UL

Definition at line 168 of file mpu.h.

◆ SHAREABLE

#define SHAREABLE   1

Definition at line 98 of file mpu.h.

◆ SHAREABLE_DEVICE_TYPE

#define SHAREABLE_DEVICE_TYPE   (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ))

Definition at line 104 of file mpu.h.

◆ SRAM_END_ADDRESS

#define SRAM_END_ADDRESS   0x2045FFFFUL

Definition at line 140 of file mpu.h.

◆ SRAM_FIRST_END_ADDRESS

#define SRAM_FIRST_END_ADDRESS   (SRAM_FIRST_START_ADDRESS + 0x3FFFF)

Definition at line 148 of file mpu.h.

◆ SRAM_FIRST_START_ADDRESS

#define SRAM_FIRST_START_ADDRESS   (SRAM_START_ADDRESS)

Definition at line 147 of file mpu.h.

◆ SRAM_SECOND_END_ADDRESS

#define SRAM_SECOND_END_ADDRESS   (SRAM_END_ADDRESS)

Definition at line 157 of file mpu.h.

◆ SRAM_SECOND_START_ADDRESS

#define SRAM_SECOND_START_ADDRESS   (SRAM_FIRST_END_ADDRESS + 1)

Definition at line 156 of file mpu.h.

◆ SRAM_START_ADDRESS

#define SRAM_START_ADDRESS   0x20400000UL

Definition at line 139 of file mpu.h.

◆ STRONGLY_ORDERED_SHAREABLE_TYPE

#define STRONGLY_ORDERED_SHAREABLE_TYPE   (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ))

Definition at line 103 of file mpu.h.

◆ USBHSRAM_END_ADDRESS

#define USBHSRAM_END_ADDRESS   0xA01FFFFFUL

Definition at line 177 of file mpu.h.

◆ USBHSRAM_START_ADDRESS

#define USBHSRAM_START_ADDRESS   0xA0100000UL

Definition at line 176 of file mpu.h.

◆ USER_MODE

#define USER_MODE   1

Definition at line 49 of file mpu.h.



inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:06