instance/gmac.h
Go to the documentation of this file.
1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_GMAC_INSTANCE_
36 #define _SAME70_GMAC_INSTANCE_
37 
38 /* ========== Register definition for GMAC peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_GMAC_NCR (0x40050000U)
41  #define REG_GMAC_NCFGR (0x40050004U)
42  #define REG_GMAC_NSR (0x40050008U)
43  #define REG_GMAC_UR (0x4005000CU)
44  #define REG_GMAC_DCFGR (0x40050010U)
45  #define REG_GMAC_TSR (0x40050014U)
46  #define REG_GMAC_RBQB (0x40050018U)
47  #define REG_GMAC_TBQB (0x4005001CU)
48  #define REG_GMAC_RSR (0x40050020U)
49  #define REG_GMAC_ISR (0x40050024U)
50  #define REG_GMAC_IER (0x40050028U)
51  #define REG_GMAC_IDR (0x4005002CU)
52  #define REG_GMAC_IMR (0x40050030U)
53  #define REG_GMAC_MAN (0x40050034U)
54  #define REG_GMAC_RPQ (0x40050038U)
55  #define REG_GMAC_TPQ (0x4005003CU)
56  #define REG_GMAC_TPSF (0x40050040U)
57  #define REG_GMAC_RPSF (0x40050044U)
58  #define REG_GMAC_RJFML (0x40050048U)
59  #define REG_GMAC_HRB (0x40050080U)
60  #define REG_GMAC_HRT (0x40050084U)
61  #define REG_GMAC_SAB1 (0x40050088U)
62  #define REG_GMAC_SAT1 (0x4005008CU)
63  #define REG_GMAC_SAB2 (0x40050090U)
64  #define REG_GMAC_SAT2 (0x40050094U)
65  #define REG_GMAC_SAB3 (0x40050098U)
66  #define REG_GMAC_SAT3 (0x4005009CU)
67  #define REG_GMAC_SAB4 (0x400500A0U)
68  #define REG_GMAC_SAT4 (0x400500A4U)
69  #define REG_GMAC_TIDM1 (0x400500A8U)
70  #define REG_GMAC_TIDM2 (0x400500ACU)
71  #define REG_GMAC_TIDM3 (0x400500B0U)
72  #define REG_GMAC_TIDM4 (0x400500B4U)
73  #define REG_GMAC_WOL (0x400500B8U)
74  #define REG_GMAC_IPGS (0x400500BCU)
75  #define REG_GMAC_SVLAN (0x400500C0U)
76  #define REG_GMAC_TPFCP (0x400500C4U)
77  #define REG_GMAC_SAMB1 (0x400500C8U)
78  #define REG_GMAC_SAMT1 (0x400500CCU)
79  #define REG_GMAC_NSC (0x400500DCU)
80  #define REG_GMAC_SCL (0x400500E0U)
81  #define REG_GMAC_SCH (0x400500E4U)
82  #define REG_GMAC_EFTSH (0x400500E8U)
83  #define REG_GMAC_EFRSH (0x400500ECU)
84  #define REG_GMAC_PEFTSH (0x400500F0U)
85  #define REG_GMAC_PEFRSH (0x400500F4U)
86  #define REG_GMAC_MID (0x400500FCU)
87  #define REG_GMAC_OTLO (0x40050100U)
88  #define REG_GMAC_OTHI (0x40050104U)
89  #define REG_GMAC_FT (0x40050108U)
90  #define REG_GMAC_BCFT (0x4005010CU)
91  #define REG_GMAC_MFT (0x40050110U)
92  #define REG_GMAC_PFT (0x40050114U)
93  #define REG_GMAC_BFT64 (0x40050118U)
94  #define REG_GMAC_TBFT127 (0x4005011CU)
95  #define REG_GMAC_TBFT255 (0x40050120U)
96  #define REG_GMAC_TBFT511 (0x40050124U)
97  #define REG_GMAC_TBFT1023 (0x40050128U)
98  #define REG_GMAC_TBFT1518 (0x4005012CU)
99  #define REG_GMAC_GTBFT1518 (0x40050130U)
100  #define REG_GMAC_TUR (0x40050134U)
101  #define REG_GMAC_SCF (0x40050138U)
102  #define REG_GMAC_MCF (0x4005013CU)
103  #define REG_GMAC_EC (0x40050140U)
104  #define REG_GMAC_LC (0x40050144U)
105  #define REG_GMAC_DTF (0x40050148U)
106  #define REG_GMAC_CSE (0x4005014CU)
107  #define REG_GMAC_ORLO (0x40050150U)
108  #define REG_GMAC_ORHI (0x40050154U)
109  #define REG_GMAC_FR (0x40050158U)
110  #define REG_GMAC_BCFR (0x4005015CU)
111  #define REG_GMAC_MFR (0x40050160U)
112  #define REG_GMAC_PFR (0x40050164U)
113  #define REG_GMAC_BFR64 (0x40050168U)
114  #define REG_GMAC_TBFR127 (0x4005016CU)
115  #define REG_GMAC_TBFR255 (0x40050170U)
116  #define REG_GMAC_TBFR511 (0x40050174U)
117  #define REG_GMAC_TBFR1023 (0x40050178U)
118  #define REG_GMAC_TBFR1518 (0x4005017CU)
119  #define REG_GMAC_TMXBFR (0x40050180U)
120  #define REG_GMAC_UFR (0x40050184U)
121  #define REG_GMAC_OFR (0x40050188U)
122  #define REG_GMAC_JR (0x4005018CU)
123  #define REG_GMAC_FCSE (0x40050190U)
124  #define REG_GMAC_LFFE (0x40050194U)
125  #define REG_GMAC_RSE (0x40050198U)
126  #define REG_GMAC_AE (0x4005019CU)
127  #define REG_GMAC_RRE (0x400501A0U)
128  #define REG_GMAC_ROE (0x400501A4U)
129  #define REG_GMAC_IHCE (0x400501A8U)
130  #define REG_GMAC_TCE (0x400501ACU)
131  #define REG_GMAC_UCE (0x400501B0U)
132  #define REG_GMAC_TISUBN (0x400501BCU)
133  #define REG_GMAC_TSH (0x400501C0U)
134  #define REG_GMAC_TSL (0x400501D0U)
135  #define REG_GMAC_TN (0x400501D4U)
136  #define REG_GMAC_TA (0x400501D8U)
137  #define REG_GMAC_TI (0x400501DCU)
138  #define REG_GMAC_EFTSL (0x400501E0U)
139  #define REG_GMAC_EFTN (0x400501E4U)
140  #define REG_GMAC_EFRSL (0x400501E8U)
141  #define REG_GMAC_EFRN (0x400501ECU)
142  #define REG_GMAC_PEFTSL (0x400501F0U)
143  #define REG_GMAC_PEFTN (0x400501F4U)
144  #define REG_GMAC_PEFRSL (0x400501F8U)
145  #define REG_GMAC_PEFRN (0x400501FCU)
146  #define REG_GMAC_RXLPI (0x40050270U)
147  #define REG_GMAC_RXLPITIME (0x40050274U)
148  #define REG_GMAC_TXLPI (0x40050278U)
149  #define REG_GMAC_TXLPITIME (0x4005027CU)
150  #define REG_GMAC_ISRPQ (0x400503FCU)
151  #define REG_GMAC_TBQBAPQ (0x4005043CU)
152  #define REG_GMAC_RBQBAPQ (0x4005047CU)
153  #define REG_GMAC_RBSRPQ (0x4005049CU)
154  #define REG_GMAC_CBSCR (0x400504BCU)
155  #define REG_GMAC_CBSISQA (0x400504C0U)
156  #define REG_GMAC_CBSISQB (0x400504C4U)
157  #define REG_GMAC_ST1RPQ (0x40050500U)
158  #define REG_GMAC_ST2RPQ (0x40050540U)
159  #define REG_GMAC_IERPQ (0x400505FCU)
160  #define REG_GMAC_IDRPQ (0x4005061CU)
161  #define REG_GMAC_IMRPQ (0x4005063CU)
162  #define REG_GMAC_ST2ER (0x400506E0U)
163  #define REG_GMAC_ST2CW00 (0x40050700U)
164  #define REG_GMAC_ST2CW10 (0x40050704U)
165  #define REG_GMAC_ST2CW01 (0x40050708U)
166  #define REG_GMAC_ST2CW11 (0x4005070CU)
167  #define REG_GMAC_ST2CW02 (0x40050710U)
168  #define REG_GMAC_ST2CW12 (0x40050714U)
169  #define REG_GMAC_ST2CW03 (0x40050718U)
170  #define REG_GMAC_ST2CW13 (0x4005071CU)
171  #define REG_GMAC_ST2CW04 (0x40050720U)
172  #define REG_GMAC_ST2CW14 (0x40050724U)
173  #define REG_GMAC_ST2CW05 (0x40050728U)
174  #define REG_GMAC_ST2CW15 (0x4005072CU)
175  #define REG_GMAC_ST2CW06 (0x40050730U)
176  #define REG_GMAC_ST2CW16 (0x40050734U)
177  #define REG_GMAC_ST2CW07 (0x40050738U)
178  #define REG_GMAC_ST2CW17 (0x4005073CU)
179  #define REG_GMAC_ST2CW08 (0x40050740U)
180  #define REG_GMAC_ST2CW18 (0x40050744U)
181  #define REG_GMAC_ST2CW09 (0x40050748U)
182  #define REG_GMAC_ST2CW19 (0x4005074CU)
183  #define REG_GMAC_ST2CW010 (0x40050750U)
184  #define REG_GMAC_ST2CW110 (0x40050754U)
185  #define REG_GMAC_ST2CW011 (0x40050758U)
186  #define REG_GMAC_ST2CW111 (0x4005075CU)
187  #define REG_GMAC_ST2CW012 (0x40050760U)
188  #define REG_GMAC_ST2CW112 (0x40050764U)
189  #define REG_GMAC_ST2CW013 (0x40050768U)
190  #define REG_GMAC_ST2CW113 (0x4005076CU)
191  #define REG_GMAC_ST2CW014 (0x40050770U)
192  #define REG_GMAC_ST2CW114 (0x40050774U)
193  #define REG_GMAC_ST2CW015 (0x40050778U)
194  #define REG_GMAC_ST2CW115 (0x4005077CU)
195  #define REG_GMAC_ST2CW016 (0x40050780U)
196  #define REG_GMAC_ST2CW116 (0x40050784U)
197  #define REG_GMAC_ST2CW017 (0x40050788U)
198  #define REG_GMAC_ST2CW117 (0x4005078CU)
199  #define REG_GMAC_ST2CW018 (0x40050790U)
200  #define REG_GMAC_ST2CW118 (0x40050794U)
201  #define REG_GMAC_ST2CW019 (0x40050798U)
202  #define REG_GMAC_ST2CW119 (0x4005079CU)
203  #define REG_GMAC_ST2CW020 (0x400507A0U)
204  #define REG_GMAC_ST2CW120 (0x400507A4U)
205  #define REG_GMAC_ST2CW021 (0x400507A8U)
206  #define REG_GMAC_ST2CW121 (0x400507ACU)
207  #define REG_GMAC_ST2CW022 (0x400507B0U)
208  #define REG_GMAC_ST2CW122 (0x400507B4U)
209  #define REG_GMAC_ST2CW023 (0x400507B8U)
210  #define REG_GMAC_ST2CW123 (0x400507BCU)
211 #else
212  #define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U)
213  #define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U)
214  #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U)
215  #define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU)
216  #define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U)
217  #define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U)
218  #define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U)
219  #define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU)
220  #define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U)
221  #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U)
222  #define REG_GMAC_IER (*(__O uint32_t*)0x40050028U)
223  #define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU)
224  #define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U)
225  #define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U)
226  #define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U)
227  #define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU)
228  #define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U)
229  #define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U)
230  #define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U)
231  #define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U)
232  #define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U)
233  #define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U)
234  #define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU)
235  #define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U)
236  #define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U)
237  #define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U)
238  #define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU)
239  #define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U)
240  #define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U)
241  #define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U)
242  #define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU)
243  #define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U)
244  #define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U)
245  #define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U)
246  #define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU)
247  #define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U)
248  #define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U)
249  #define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U)
250  #define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU)
251  #define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU)
252  #define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U)
253  #define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U)
254  #define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U)
255  #define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU)
256  #define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U)
257  #define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U)
258  #define REG_GMAC_MID (*(__I uint32_t*)0x400500FCU)
259  #define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U)
260  #define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U)
261  #define REG_GMAC_FT (*(__I uint32_t*)0x40050108U)
262  #define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU)
263  #define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U)
264  #define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U)
265  #define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U)
266  #define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU)
267  #define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U)
268  #define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U)
269  #define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U)
270  #define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU)
271  #define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U)
272  #define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U)
273  #define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U)
274  #define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU)
275  #define REG_GMAC_EC (*(__I uint32_t*)0x40050140U)
276  #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U)
277  #define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U)
278  #define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU)
279  #define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U)
280  #define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U)
281  #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U)
282  #define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU)
283  #define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U)
284  #define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U)
285  #define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U)
286  #define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU)
287  #define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U)
288  #define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U)
289  #define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U)
290  #define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU)
291  #define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U)
292  #define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U)
293  #define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U)
294  #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU)
295  #define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U)
296  #define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U)
297  #define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U)
298  #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU)
299  #define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U)
300  #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U)
301  #define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U)
302  #define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU)
303  #define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U)
304  #define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU)
305  #define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U)
306  #define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U)
307  #define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U)
308  #define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U)
309  #define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU)
310  #define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U)
311  #define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U)
312  #define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U)
313  #define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU)
314  #define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U)
315  #define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U)
316  #define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U)
317  #define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU)
318  #define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U)
319  #define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U)
320  #define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U)
321  #define REG_GMAC_TXLPITIME (*(__I uint32_t*)0x4005027CU)
322  #define REG_GMAC_ISRPQ (*(__I uint32_t*)0x400503FCU)
323  #define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x4005043CU)
324  #define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x4005047CU)
325  #define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x4005049CU)
326  #define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU)
327  #define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U)
328  #define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U)
329  #define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U)
330  #define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U)
331  #define REG_GMAC_IERPQ (*(__O uint32_t*)0x400505FCU)
332  #define REG_GMAC_IDRPQ (*(__O uint32_t*)0x4005061CU)
333  #define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x4005063CU)
334  #define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U)
335  #define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U)
336  #define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U)
337  #define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U)
338  #define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU)
339  #define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U)
340  #define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U)
341  #define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U)
342  #define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU)
343  #define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U)
344  #define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U)
345  #define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U)
346  #define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU)
347  #define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U)
348  #define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U)
349  #define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U)
350  #define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU)
351  #define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U)
352  #define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U)
353  #define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U)
354  #define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU)
355  #define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U)
356  #define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U)
357  #define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U)
358  #define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU)
359  #define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U)
360  #define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U)
361  #define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U)
362  #define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU)
363  #define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U)
364  #define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U)
365  #define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U)
366  #define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU)
367  #define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U)
368  #define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U)
369  #define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U)
370  #define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU)
371  #define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U)
372  #define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U)
373  #define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U)
374  #define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU)
375  #define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U)
376  #define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U)
377  #define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U)
378  #define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU)
379  #define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U)
380  #define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U)
381  #define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U)
382  #define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU)
383 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
384 
385 #endif /* _SAME70_GMAC_INSTANCE_ */


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04