i2sc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_I2SC_COMPONENT_
36 #define _SAME70_I2SC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t I2SC_CR;
48  __IO uint32_t I2SC_MR;
49  __I uint32_t I2SC_SR;
50  __O uint32_t I2SC_SCR;
51  __O uint32_t I2SC_SSR;
52  __O uint32_t I2SC_IER;
53  __O uint32_t I2SC_IDR;
54  __I uint32_t I2SC_IMR;
55  __I uint32_t I2SC_RHR;
56  __O uint32_t I2SC_THR;
57  __I uint32_t I2SC_VERSION;
58 } I2sc;
59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
60 /* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */
61 #define I2SC_CR_RXEN (0x1u << 0)
62 #define I2SC_CR_RXDIS (0x1u << 1)
63 #define I2SC_CR_CKEN (0x1u << 2)
64 #define I2SC_CR_CKDIS (0x1u << 3)
65 #define I2SC_CR_TXEN (0x1u << 4)
66 #define I2SC_CR_TXDIS (0x1u << 5)
67 #define I2SC_CR_SWRST (0x1u << 7)
68 /* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */
69 #define I2SC_MR_MODE (0x1u << 0)
70 #define I2SC_MR_MODE_SLAVE (0x0u << 0)
71 #define I2SC_MR_MODE_MASTER (0x1u << 0)
72 #define I2SC_MR_DATALENGTH_Pos 2
73 #define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos)
74 #define I2SC_MR_DATALENGTH(value) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)))
75 #define I2SC_MR_DATALENGTH_32_BITS (0x0u << 2)
76 #define I2SC_MR_DATALENGTH_24_BITS (0x1u << 2)
77 #define I2SC_MR_DATALENGTH_20_BITS (0x2u << 2)
78 #define I2SC_MR_DATALENGTH_18_BITS (0x3u << 2)
79 #define I2SC_MR_DATALENGTH_16_BITS (0x4u << 2)
80 #define I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2)
81 #define I2SC_MR_DATALENGTH_8_BITS (0x6u << 2)
82 #define I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2)
83 #define I2SC_MR_FORMAT_Pos 6
84 #define I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos)
85 #define I2SC_MR_FORMAT(value) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos)))
86 #define I2SC_MR_FORMAT_I2S (0x0u << 6)
87 #define I2SC_MR_FORMAT_LJ (0x1u << 6)
88 #define I2SC_MR_RXMONO (0x1u << 8)
89 #define I2SC_MR_RXDMA (0x1u << 9)
90 #define I2SC_MR_RXLOOP (0x1u << 10)
91 #define I2SC_MR_TXMONO (0x1u << 12)
92 #define I2SC_MR_TXDMA (0x1u << 13)
93 #define I2SC_MR_TXSAME (0x1u << 14)
94 #define I2SC_MR_IMCKDIV_Pos 16
95 #define I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos)
96 #define I2SC_MR_IMCKDIV(value) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)))
97 #define I2SC_MR_IMCKFS_Pos 24
98 #define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos)
99 #define I2SC_MR_IMCKFS(value) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)))
100 #define I2SC_MR_IMCKFS_M2SF32 (0x0u << 24)
101 #define I2SC_MR_IMCKFS_M2SF64 (0x1u << 24)
102 #define I2SC_MR_IMCKFS_M2SF96 (0x2u << 24)
103 #define I2SC_MR_IMCKFS_M2SF128 (0x3u << 24)
104 #define I2SC_MR_IMCKFS_M2SF192 (0x5u << 24)
105 #define I2SC_MR_IMCKFS_M2SF256 (0x7u << 24)
106 #define I2SC_MR_IMCKFS_M2SF384 (0xBu << 24)
107 #define I2SC_MR_IMCKFS_M2SF512 (0xFu << 24)
108 #define I2SC_MR_IMCKFS_M2SF768 (0x17u << 24)
109 #define I2SC_MR_IMCKFS_M2SF1024 (0x1Fu << 24)
110 #define I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24)
111 #define I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24)
112 #define I2SC_MR_IMCKMODE (0x1u << 30)
113 #define I2SC_MR_IWS (0x1u << 31)
114 /* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */
115 #define I2SC_SR_RXEN (0x1u << 0)
116 #define I2SC_SR_RXRDY (0x1u << 1)
117 #define I2SC_SR_RXOR (0x1u << 2)
118 #define I2SC_SR_TXEN (0x1u << 4)
119 #define I2SC_SR_TXRDY (0x1u << 5)
120 #define I2SC_SR_TXUR (0x1u << 6)
121 #define I2SC_SR_RXORCH_Pos 8
122 #define I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos)
123 #define I2SC_SR_TXURCH_Pos 20
124 #define I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos)
125 /* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */
126 #define I2SC_SCR_RXOR (0x1u << 2)
127 #define I2SC_SCR_TXUR (0x1u << 6)
128 #define I2SC_SCR_RXORCH_Pos 8
129 #define I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos)
130 #define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)))
131 #define I2SC_SCR_TXURCH_Pos 20
132 #define I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos)
133 #define I2SC_SCR_TXURCH(value) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)))
134 /* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */
135 #define I2SC_SSR_RXOR (0x1u << 2)
136 #define I2SC_SSR_TXUR (0x1u << 6)
137 #define I2SC_SSR_RXORCH_Pos 8
138 #define I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos)
139 #define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)))
140 #define I2SC_SSR_TXURCH_Pos 20
141 #define I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos)
142 #define I2SC_SSR_TXURCH(value) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)))
143 /* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */
144 #define I2SC_IER_RXRDY (0x1u << 1)
145 #define I2SC_IER_RXOR (0x1u << 2)
146 #define I2SC_IER_TXRDY (0x1u << 5)
147 #define I2SC_IER_TXUR (0x1u << 6)
148 /* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */
149 #define I2SC_IDR_RXRDY (0x1u << 1)
150 #define I2SC_IDR_RXOR (0x1u << 2)
151 #define I2SC_IDR_TXRDY (0x1u << 5)
152 #define I2SC_IDR_TXUR (0x1u << 6)
153 /* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */
154 #define I2SC_IMR_RXRDY (0x1u << 1)
155 #define I2SC_IMR_RXOR (0x1u << 2)
156 #define I2SC_IMR_TXRDY (0x1u << 5)
157 #define I2SC_IMR_TXUR (0x1u << 6)
158 /* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */
159 #define I2SC_RHR_RHR_Pos 0
160 #define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos)
161 /* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */
162 #define I2SC_THR_THR_Pos 0
163 #define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos)
164 #define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)))
165 /* -------- I2SC_VERSION : (I2SC Offset: 0x28) Version Register -------- */
166 #define I2SC_VERSION_VERSION_Pos 0
167 #define I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos)
168 #define I2SC_VERSION_MFN_Pos 16
169 #define I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos)
172 
173 
174 #endif /* _SAME70_I2SC_COMPONENT_ */
__O uint32_t I2SC_SCR
(I2sc Offset: 0x0C) Status Clear Register
Definition: i2sc.h:50
__O uint32_t I2SC_SSR
(I2sc Offset: 0x10) Status Set Register
Definition: i2sc.h:51
__O uint32_t I2SC_IDR
(I2sc Offset: 0x18) Interrupt Disable Register
Definition: i2sc.h:53
__O uint32_t I2SC_IER
(I2sc Offset: 0x14) Interrupt Enable Register
Definition: i2sc.h:52
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__I uint32_t I2SC_VERSION
(I2sc Offset: 0x28) Version Register
Definition: i2sc.h:57
__O uint32_t I2SC_CR
(I2sc Offset: 0x00) Control Register
Definition: i2sc.h:47
__I uint32_t I2SC_SR
(I2sc Offset: 0x08) Status Register
Definition: i2sc.h:49
__I uint32_t I2SC_IMR
(I2sc Offset: 0x1C) Interrupt Mask Register
Definition: i2sc.h:54
I2sc hardware registers.
Definition: i2sc.h:46
__O uint32_t I2SC_THR
(I2sc Offset: 0x24) Transmitter Holding Register
Definition: i2sc.h:56
__I uint32_t I2SC_RHR
(I2sc Offset: 0x20) Receiver Holding Register
Definition: i2sc.h:55
#define __I
Definition: core_cm7.h:263
__IO uint32_t I2SC_MR
(I2sc Offset: 0x04) Mode Register
Definition: i2sc.h:48


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04