Classes | Macros
Reset Controller

Classes

struct  Rstc
 Rstc hardware registers. More...
 

Macros

#define RSTC_CR_EXTRST   (0x1u << 3)
 (RSTC_CR) External Reset More...
 
#define RSTC_CR_KEY(value)   ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
 
#define RSTC_CR_KEY_Msk   (0xffu << RSTC_CR_KEY_Pos)
 (RSTC_CR) System Reset Key More...
 
#define RSTC_CR_KEY_PASSWD   (0xA5u << 24)
 (RSTC_CR) Writing any other value in this field aborts the write operation. More...
 
#define RSTC_CR_KEY_Pos   24
 
#define RSTC_CR_PROCRST   (0x1u << 0)
 (RSTC_CR) Processor Reset More...
 
#define RSTC_MR_ERSTL(value)   ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
 
#define RSTC_MR_ERSTL_Msk   (0xfu << RSTC_MR_ERSTL_Pos)
 (RSTC_MR) External Reset Length More...
 
#define RSTC_MR_ERSTL_Pos   8
 
#define RSTC_MR_KEY(value)   ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
 
#define RSTC_MR_KEY_Msk   (0xffu << RSTC_MR_KEY_Pos)
 (RSTC_MR) Write Access Password More...
 
#define RSTC_MR_KEY_PASSWD   (0xA5u << 24)
 (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. More...
 
#define RSTC_MR_KEY_Pos   24
 
#define RSTC_MR_URSTEN   (0x1u << 0)
 (RSTC_MR) User Reset Enable More...
 
#define RSTC_MR_URSTIEN   (0x1u << 4)
 (RSTC_MR) User Reset Interrupt Enable More...
 
#define RSTC_SR_NRSTL   (0x1u << 16)
 (RSTC_SR) NRST Pin Level More...
 
#define RSTC_SR_RSTTYP_BACKUP_RST   (0x1u << 8)
 (RSTC_SR) Return from Backup Mode More...
 
#define RSTC_SR_RSTTYP_GENERAL_RST   (0x0u << 8)
 (RSTC_SR) First power-up reset More...
 
#define RSTC_SR_RSTTYP_Msk   (0x7u << RSTC_SR_RSTTYP_Pos)
 (RSTC_SR) Reset Type More...
 
#define RSTC_SR_RSTTYP_Pos   8
 
#define RSTC_SR_RSTTYP_SOFT_RST   (0x3u << 8)
 (RSTC_SR) Processor reset required by the software More...
 
#define RSTC_SR_RSTTYP_USER_RST   (0x4u << 8)
 (RSTC_SR) NRST pin detected low More...
 
#define RSTC_SR_RSTTYP_WDT_RST   (0x2u << 8)
 (RSTC_SR) Watchdog fault occurred More...
 
#define RSTC_SR_SRCMP   (0x1u << 17)
 (RSTC_SR) Software Reset Command in Progress More...
 
#define RSTC_SR_URSTS   (0x1u << 0)
 (RSTC_SR) User Reset Status More...
 

Detailed Description

SOFTWARE API DEFINITION FOR Reset Controller

Macro Definition Documentation

◆ RSTC_CR_EXTRST

#define RSTC_CR_EXTRST   (0x1u << 3)

(RSTC_CR) External Reset

Definition at line 54 of file component/rstc.h.

◆ RSTC_CR_KEY

#define RSTC_CR_KEY (   value)    ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))

Definition at line 57 of file component/rstc.h.

◆ RSTC_CR_KEY_Msk

#define RSTC_CR_KEY_Msk   (0xffu << RSTC_CR_KEY_Pos)

(RSTC_CR) System Reset Key

Definition at line 56 of file component/rstc.h.

◆ RSTC_CR_KEY_PASSWD

#define RSTC_CR_KEY_PASSWD   (0xA5u << 24)

(RSTC_CR) Writing any other value in this field aborts the write operation.

Definition at line 58 of file component/rstc.h.

◆ RSTC_CR_KEY_Pos

#define RSTC_CR_KEY_Pos   24

Definition at line 55 of file component/rstc.h.

◆ RSTC_CR_PROCRST

#define RSTC_CR_PROCRST   (0x1u << 0)

(RSTC_CR) Processor Reset

Definition at line 53 of file component/rstc.h.

◆ RSTC_MR_ERSTL

#define RSTC_MR_ERSTL (   value)    ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))

Definition at line 75 of file component/rstc.h.

◆ RSTC_MR_ERSTL_Msk

#define RSTC_MR_ERSTL_Msk   (0xfu << RSTC_MR_ERSTL_Pos)

(RSTC_MR) External Reset Length

Definition at line 74 of file component/rstc.h.

◆ RSTC_MR_ERSTL_Pos

#define RSTC_MR_ERSTL_Pos   8

Definition at line 73 of file component/rstc.h.

◆ RSTC_MR_KEY

#define RSTC_MR_KEY (   value)    ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))

Definition at line 78 of file component/rstc.h.

◆ RSTC_MR_KEY_Msk

#define RSTC_MR_KEY_Msk   (0xffu << RSTC_MR_KEY_Pos)

(RSTC_MR) Write Access Password

Definition at line 77 of file component/rstc.h.

◆ RSTC_MR_KEY_PASSWD

#define RSTC_MR_KEY_PASSWD   (0xA5u << 24)

(RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0.

Definition at line 79 of file component/rstc.h.

◆ RSTC_MR_KEY_Pos

#define RSTC_MR_KEY_Pos   24

Definition at line 76 of file component/rstc.h.

◆ RSTC_MR_URSTEN

#define RSTC_MR_URSTEN   (0x1u << 0)

(RSTC_MR) User Reset Enable

Definition at line 71 of file component/rstc.h.

◆ RSTC_MR_URSTIEN

#define RSTC_MR_URSTIEN   (0x1u << 4)

(RSTC_MR) User Reset Interrupt Enable

Definition at line 72 of file component/rstc.h.

◆ RSTC_SR_NRSTL

#define RSTC_SR_NRSTL   (0x1u << 16)

(RSTC_SR) NRST Pin Level

Definition at line 68 of file component/rstc.h.

◆ RSTC_SR_RSTTYP_BACKUP_RST

#define RSTC_SR_RSTTYP_BACKUP_RST   (0x1u << 8)

(RSTC_SR) Return from Backup Mode

Definition at line 64 of file component/rstc.h.

◆ RSTC_SR_RSTTYP_GENERAL_RST

#define RSTC_SR_RSTTYP_GENERAL_RST   (0x0u << 8)

(RSTC_SR) First power-up reset

Definition at line 63 of file component/rstc.h.

◆ RSTC_SR_RSTTYP_Msk

#define RSTC_SR_RSTTYP_Msk   (0x7u << RSTC_SR_RSTTYP_Pos)

(RSTC_SR) Reset Type

Definition at line 62 of file component/rstc.h.

◆ RSTC_SR_RSTTYP_Pos

#define RSTC_SR_RSTTYP_Pos   8

Definition at line 61 of file component/rstc.h.

◆ RSTC_SR_RSTTYP_SOFT_RST

#define RSTC_SR_RSTTYP_SOFT_RST   (0x3u << 8)

(RSTC_SR) Processor reset required by the software

Definition at line 66 of file component/rstc.h.

◆ RSTC_SR_RSTTYP_USER_RST

#define RSTC_SR_RSTTYP_USER_RST   (0x4u << 8)

(RSTC_SR) NRST pin detected low

Definition at line 67 of file component/rstc.h.

◆ RSTC_SR_RSTTYP_WDT_RST

#define RSTC_SR_RSTTYP_WDT_RST   (0x2u << 8)

(RSTC_SR) Watchdog fault occurred

Definition at line 65 of file component/rstc.h.

◆ RSTC_SR_SRCMP

#define RSTC_SR_SRCMP   (0x1u << 17)

(RSTC_SR) Software Reset Command in Progress

Definition at line 69 of file component/rstc.h.

◆ RSTC_SR_URSTS

#define RSTC_SR_URSTS   (0x1u << 0)

(RSTC_SR) User Reset Status

Definition at line 60 of file component/rstc.h.



inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:08