Classes | |
| struct | Gmac |
| struct | GmacSa |
| GmacSa hardware registers. More... | |
Macros | |
| #define | GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) |
| (GMAC_AE) Alignment Errors More... | |
| #define | GMAC_AE_AER_Pos 0 |
| #define | GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) |
| (GMAC_BCFR) Broadcast Frames Received without Error More... | |
| #define | GMAC_BCFR_BFRX_Pos 0 |
| #define | GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) |
| (GMAC_BCFT) Broadcast Frames Transmitted without Error More... | |
| #define | GMAC_BCFT_BFTX_Pos 0 |
| #define | GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) |
| (GMAC_BFR64) 64 Byte Frames Received without Error More... | |
| #define | GMAC_BFR64_NFRX_Pos 0 |
| #define | GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) |
| (GMAC_BFT64) 64 Byte Frames Transmitted without Error More... | |
| #define | GMAC_BFT64_NFTX_Pos 0 |
| #define | GMAC_CBSCR_QAE (0x1u << 1) |
| (GMAC_CBSCR) Queue A CBS Enable More... | |
| #define | GMAC_CBSCR_QBE (0x1u << 0) |
| (GMAC_CBSCR) Queue B CBS Enable More... | |
| #define | GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) |
| #define | GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) |
| (GMAC_CBSISQA) IdleSlope More... | |
| #define | GMAC_CBSISQA_IS_Pos 0 |
| #define | GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) |
| #define | GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) |
| (GMAC_CBSISQB) IdleSlope More... | |
| #define | GMAC_CBSISQB_IS_Pos 0 |
| #define | GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) |
| (GMAC_CSE) Carrier Sense Error More... | |
| #define | GMAC_CSE_CSR_Pos 0 |
| #define | GMAC_DCFGR_DDRP (0x1u << 24) |
| (GMAC_DCFGR) DMA Discard Receive Packets More... | |
| #define | GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) |
| #define | GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) |
| (GMAC_DCFGR) DMA Receive Buffer Size More... | |
| #define | GMAC_DCFGR_DRBS_Pos 16 |
| #define | GMAC_DCFGR_ESMA (0x1u << 6) |
| (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses More... | |
| #define | GMAC_DCFGR_ESPA (0x1u << 7) |
| (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses More... | |
| #define | GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) |
| #define | GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) |
| (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts More... | |
| #define | GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) |
| (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) More... | |
| #define | GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) |
| (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts More... | |
| #define | GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) |
| (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: More... | |
| #define | GMAC_DCFGR_FBLDO_Pos 0 |
| #define | GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) |
| (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts More... | |
| #define | GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) |
| #define | GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) |
| (GMAC_DCFGR) 4/8 Kbyte Memory Size More... | |
| #define | GMAC_DCFGR_RXBMS_FULL (0x3u << 8) |
| (GMAC_DCFGR) 4 Kbytes Memory Size More... | |
| #define | GMAC_DCFGR_RXBMS_HALF (0x2u << 8) |
| (GMAC_DCFGR) 4/2 Kbytes Memory Size More... | |
| #define | GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) |
| (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select More... | |
| #define | GMAC_DCFGR_RXBMS_Pos 8 |
| #define | GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) |
| (GMAC_DCFGR) 4/4 Kbytes Memory Size More... | |
| #define | GMAC_DCFGR_TXCOEN (0x1u << 11) |
| (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable More... | |
| #define | GMAC_DCFGR_TXPBMS (0x1u << 10) |
| (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select More... | |
| #define | GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) |
| (GMAC_DTF) Deferred Transmission More... | |
| #define | GMAC_DTF_DEFT_Pos 0 |
| #define | GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) |
| (GMAC_EC) Excessive Collisions More... | |
| #define | GMAC_EC_XCOL_Pos 0 |
| #define | GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) |
| (GMAC_EFRN) Register Update More... | |
| #define | GMAC_EFRN_RUD_Pos 0 |
| #define | GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) |
| (GMAC_EFRSH) Register Update More... | |
| #define | GMAC_EFRSH_RUD_Pos 0 |
| #define | GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) |
| (GMAC_EFRSL) Register Update More... | |
| #define | GMAC_EFRSL_RUD_Pos 0 |
| #define | GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) |
| (GMAC_EFTN) Register Update More... | |
| #define | GMAC_EFTN_RUD_Pos 0 |
| #define | GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) |
| (GMAC_EFTSH) Register Update More... | |
| #define | GMAC_EFTSH_RUD_Pos 0 |
| #define | GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) |
| (GMAC_EFTSL) Register Update More... | |
| #define | GMAC_EFTSL_RUD_Pos 0 |
| #define | GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) |
| (GMAC_FCSE) Frame Check Sequence Errors More... | |
| #define | GMAC_FCSE_FCKR_Pos 0 |
| #define | GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) |
| (GMAC_FR) Frames Received without Error More... | |
| #define | GMAC_FR_FRX_Pos 0 |
| #define | GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) |
| (GMAC_FT) Frames Transmitted without Error More... | |
| #define | GMAC_FT_FTX_Pos 0 |
| #define | GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) |
| (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error More... | |
| #define | GMAC_GTBFT1518_NFTX_Pos 0 |
| #define | GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) |
| #define | GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) |
| (GMAC_HRB) Hash Address More... | |
| #define | GMAC_HRB_ADDR_Pos 0 |
| #define | GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) |
| #define | GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) |
| (GMAC_HRT) Hash Address More... | |
| #define | GMAC_HRT_ADDR_Pos 0 |
| #define | GMAC_IDR_DRQFR (0x1u << 18) |
| (GMAC_IDR) PTP Delay Request Frame Received More... | |
| #define | GMAC_IDR_DRQFT (0x1u << 20) |
| (GMAC_IDR) PTP Delay Request Frame Transmitted More... | |
| #define | GMAC_IDR_EXINT (0x1u << 15) |
| (GMAC_IDR) External Interrupt More... | |
| #define | GMAC_IDR_HRESP (0x1u << 11) |
| (GMAC_IDR) HRESP Not OK More... | |
| #define | GMAC_IDR_MFS (0x1u << 0) |
| (GMAC_IDR) Management Frame Sent More... | |
| #define | GMAC_IDR_PDRQFR (0x1u << 22) |
| (GMAC_IDR) PDelay Request Frame Received More... | |
| #define | GMAC_IDR_PDRQFT (0x1u << 24) |
| (GMAC_IDR) PDelay Request Frame Transmitted More... | |
| #define | GMAC_IDR_PDRSFR (0x1u << 23) |
| (GMAC_IDR) PDelay Response Frame Received More... | |
| #define | GMAC_IDR_PDRSFT (0x1u << 25) |
| (GMAC_IDR) PDelay Response Frame Transmitted More... | |
| #define | GMAC_IDR_PFNZ (0x1u << 12) |
| (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received More... | |
| #define | GMAC_IDR_PFTR (0x1u << 14) |
| (GMAC_IDR) Pause Frame Transmitted More... | |
| #define | GMAC_IDR_PTZ (0x1u << 13) |
| (GMAC_IDR) Pause Time Zero More... | |
| #define | GMAC_IDR_RCOMP (0x1u << 1) |
| (GMAC_IDR) Receive Complete More... | |
| #define | GMAC_IDR_RLEX (0x1u << 5) |
| (GMAC_IDR) Retry Limit Exceeded or Late Collision More... | |
| #define | GMAC_IDR_ROVR (0x1u << 10) |
| (GMAC_IDR) Receive Overrun More... | |
| #define | GMAC_IDR_RXUBR (0x1u << 2) |
| (GMAC_IDR) RX Used Bit Read More... | |
| #define | GMAC_IDR_SFR (0x1u << 19) |
| (GMAC_IDR) PTP Sync Frame Received More... | |
| #define | GMAC_IDR_SFT (0x1u << 21) |
| (GMAC_IDR) PTP Sync Frame Transmitted More... | |
| #define | GMAC_IDR_SRI (0x1u << 26) |
| (GMAC_IDR) TSU Seconds Register Increment More... | |
| #define | GMAC_IDR_TCOMP (0x1u << 7) |
| (GMAC_IDR) Transmit Complete More... | |
| #define | GMAC_IDR_TFC (0x1u << 6) |
| (GMAC_IDR) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_IDR_TUR (0x1u << 4) |
| (GMAC_IDR) Transmit Underrun More... | |
| #define | GMAC_IDR_TXUBR (0x1u << 3) |
| (GMAC_IDR) TX Used Bit Read More... | |
| #define | GMAC_IDR_WOL (0x1u << 28) |
| (GMAC_IDR) Wake On LAN More... | |
| #define | GMAC_IDRPQ_HRESP (0x1u << 11) |
| (GMAC_IDRPQ[5]) HRESP Not OK More... | |
| #define | GMAC_IDRPQ_RCOMP (0x1u << 1) |
| (GMAC_IDRPQ[5]) Receive Complete More... | |
| #define | GMAC_IDRPQ_RLEX (0x1u << 5) |
| (GMAC_IDRPQ[5]) Retry Limit Exceeded or Late Collision More... | |
| #define | GMAC_IDRPQ_ROVR (0x1u << 10) |
| (GMAC_IDRPQ[5]) Receive Overrun More... | |
| #define | GMAC_IDRPQ_RXUBR (0x1u << 2) |
| (GMAC_IDRPQ[5]) RX Used Bit Read More... | |
| #define | GMAC_IDRPQ_TCOMP (0x1u << 7) |
| (GMAC_IDRPQ[5]) Transmit Complete More... | |
| #define | GMAC_IDRPQ_TFC (0x1u << 6) |
| (GMAC_IDRPQ[5]) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_IER_DRQFR (0x1u << 18) |
| (GMAC_IER) PTP Delay Request Frame Received More... | |
| #define | GMAC_IER_DRQFT (0x1u << 20) |
| (GMAC_IER) PTP Delay Request Frame Transmitted More... | |
| #define | GMAC_IER_EXINT (0x1u << 15) |
| (GMAC_IER) External Interrupt More... | |
| #define | GMAC_IER_HRESP (0x1u << 11) |
| (GMAC_IER) HRESP Not OK More... | |
| #define | GMAC_IER_MFS (0x1u << 0) |
| (GMAC_IER) Management Frame Sent More... | |
| #define | GMAC_IER_PDRQFR (0x1u << 22) |
| (GMAC_IER) PDelay Request Frame Received More... | |
| #define | GMAC_IER_PDRQFT (0x1u << 24) |
| (GMAC_IER) PDelay Request Frame Transmitted More... | |
| #define | GMAC_IER_PDRSFR (0x1u << 23) |
| (GMAC_IER) PDelay Response Frame Received More... | |
| #define | GMAC_IER_PDRSFT (0x1u << 25) |
| (GMAC_IER) PDelay Response Frame Transmitted More... | |
| #define | GMAC_IER_PFNZ (0x1u << 12) |
| (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received More... | |
| #define | GMAC_IER_PFTR (0x1u << 14) |
| (GMAC_IER) Pause Frame Transmitted More... | |
| #define | GMAC_IER_PTZ (0x1u << 13) |
| (GMAC_IER) Pause Time Zero More... | |
| #define | GMAC_IER_RCOMP (0x1u << 1) |
| (GMAC_IER) Receive Complete More... | |
| #define | GMAC_IER_RLEX (0x1u << 5) |
| (GMAC_IER) Retry Limit Exceeded or Late Collision More... | |
| #define | GMAC_IER_ROVR (0x1u << 10) |
| (GMAC_IER) Receive Overrun More... | |
| #define | GMAC_IER_RXUBR (0x1u << 2) |
| (GMAC_IER) RX Used Bit Read More... | |
| #define | GMAC_IER_SFR (0x1u << 19) |
| (GMAC_IER) PTP Sync Frame Received More... | |
| #define | GMAC_IER_SFT (0x1u << 21) |
| (GMAC_IER) PTP Sync Frame Transmitted More... | |
| #define | GMAC_IER_SRI (0x1u << 26) |
| (GMAC_IER) TSU Seconds Register Increment More... | |
| #define | GMAC_IER_TCOMP (0x1u << 7) |
| (GMAC_IER) Transmit Complete More... | |
| #define | GMAC_IER_TFC (0x1u << 6) |
| (GMAC_IER) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_IER_TUR (0x1u << 4) |
| (GMAC_IER) Transmit Underrun More... | |
| #define | GMAC_IER_TXUBR (0x1u << 3) |
| (GMAC_IER) TX Used Bit Read More... | |
| #define | GMAC_IER_WOL (0x1u << 28) |
| (GMAC_IER) Wake On LAN More... | |
| #define | GMAC_IERPQ_HRESP (0x1u << 11) |
| (GMAC_IERPQ[5]) HRESP Not OK More... | |
| #define | GMAC_IERPQ_RCOMP (0x1u << 1) |
| (GMAC_IERPQ[5]) Receive Complete More... | |
| #define | GMAC_IERPQ_RLEX (0x1u << 5) |
| (GMAC_IERPQ[5]) Retry Limit Exceeded or Late Collision More... | |
| #define | GMAC_IERPQ_ROVR (0x1u << 10) |
| (GMAC_IERPQ[5]) Receive Overrun More... | |
| #define | GMAC_IERPQ_RXUBR (0x1u << 2) |
| (GMAC_IERPQ[5]) RX Used Bit Read More... | |
| #define | GMAC_IERPQ_TCOMP (0x1u << 7) |
| (GMAC_IERPQ[5]) Transmit Complete More... | |
| #define | GMAC_IERPQ_TFC (0x1u << 6) |
| (GMAC_IERPQ[5]) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) |
| (GMAC_IHCE) IP Header Checksum Errors More... | |
| #define | GMAC_IHCE_HCKER_Pos 0 |
| #define | GMAC_IMR_DRQFR (0x1u << 18) |
| (GMAC_IMR) PTP Delay Request Frame Received More... | |
| #define | GMAC_IMR_DRQFT (0x1u << 20) |
| (GMAC_IMR) PTP Delay Request Frame Transmitted More... | |
| #define | GMAC_IMR_EXINT (0x1u << 15) |
| (GMAC_IMR) External Interrupt More... | |
| #define | GMAC_IMR_HRESP (0x1u << 11) |
| (GMAC_IMR) HRESP Not OK More... | |
| #define | GMAC_IMR_MFS (0x1u << 0) |
| (GMAC_IMR) Management Frame Sent More... | |
| #define | GMAC_IMR_PDRQFR (0x1u << 22) |
| (GMAC_IMR) PDelay Request Frame Received More... | |
| #define | GMAC_IMR_PDRQFT (0x1u << 24) |
| (GMAC_IMR) PDelay Request Frame Transmitted More... | |
| #define | GMAC_IMR_PDRSFR (0x1u << 23) |
| (GMAC_IMR) PDelay Response Frame Received More... | |
| #define | GMAC_IMR_PDRSFT (0x1u << 25) |
| (GMAC_IMR) PDelay Response Frame Transmitted More... | |
| #define | GMAC_IMR_PFNZ (0x1u << 12) |
| (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received More... | |
| #define | GMAC_IMR_PFTR (0x1u << 14) |
| (GMAC_IMR) Pause Frame Transmitted More... | |
| #define | GMAC_IMR_PTZ (0x1u << 13) |
| (GMAC_IMR) Pause Time Zero More... | |
| #define | GMAC_IMR_RCOMP (0x1u << 1) |
| (GMAC_IMR) Receive Complete More... | |
| #define | GMAC_IMR_RLEX (0x1u << 5) |
| (GMAC_IMR) Retry Limit Exceeded More... | |
| #define | GMAC_IMR_ROVR (0x1u << 10) |
| (GMAC_IMR) Receive Overrun More... | |
| #define | GMAC_IMR_RXUBR (0x1u << 2) |
| (GMAC_IMR) RX Used Bit Read More... | |
| #define | GMAC_IMR_SFR (0x1u << 19) |
| (GMAC_IMR) PTP Sync Frame Received More... | |
| #define | GMAC_IMR_SFT (0x1u << 21) |
| (GMAC_IMR) PTP Sync Frame Transmitted More... | |
| #define | GMAC_IMR_SRI (0x1u << 26) |
| (GMAC_IMR) TSU Seconds Register Increment More... | |
| #define | GMAC_IMR_TCOMP (0x1u << 7) |
| (GMAC_IMR) Transmit Complete More... | |
| #define | GMAC_IMR_TFC (0x1u << 6) |
| (GMAC_IMR) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_IMR_TUR (0x1u << 4) |
| (GMAC_IMR) Transmit Underrun More... | |
| #define | GMAC_IMR_TXUBR (0x1u << 3) |
| (GMAC_IMR) TX Used Bit Read More... | |
| #define | GMAC_IMR_WOL (0x1u << 28) |
| (GMAC_IMR) Wake On LAN More... | |
| #define | GMAC_IMRPQ_AHB (0x1u << 6) |
| (GMAC_IMRPQ[5]) AHB Error More... | |
| #define | GMAC_IMRPQ_HRESP (0x1u << 11) |
| (GMAC_IMRPQ[5]) HRESP Not OK More... | |
| #define | GMAC_IMRPQ_RCOMP (0x1u << 1) |
| (GMAC_IMRPQ[5]) Receive Complete More... | |
| #define | GMAC_IMRPQ_RLEX (0x1u << 5) |
| (GMAC_IMRPQ[5]) Retry Limit Exceeded or Late Collision More... | |
| #define | GMAC_IMRPQ_ROVR (0x1u << 10) |
| (GMAC_IMRPQ[5]) Receive Overrun More... | |
| #define | GMAC_IMRPQ_RXUBR (0x1u << 2) |
| (GMAC_IMRPQ[5]) RX Used Bit Read More... | |
| #define | GMAC_IMRPQ_TCOMP (0x1u << 7) |
| (GMAC_IMRPQ[5]) Transmit Complete More... | |
| #define | GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) |
| #define | GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) |
| (GMAC_IPGS) Frame Length More... | |
| #define | GMAC_IPGS_FL_Pos 0 |
| #define | GMAC_ISR_DRQFR (0x1u << 18) |
| (GMAC_ISR) PTP Delay Request Frame Received More... | |
| #define | GMAC_ISR_DRQFT (0x1u << 20) |
| (GMAC_ISR) PTP Delay Request Frame Transmitted More... | |
| #define | GMAC_ISR_HRESP (0x1u << 11) |
| (GMAC_ISR) HRESP Not OK More... | |
| #define | GMAC_ISR_MFS (0x1u << 0) |
| (GMAC_ISR) Management Frame Sent More... | |
| #define | GMAC_ISR_PDRQFR (0x1u << 22) |
| (GMAC_ISR) PDelay Request Frame Received More... | |
| #define | GMAC_ISR_PDRQFT (0x1u << 24) |
| (GMAC_ISR) PDelay Request Frame Transmitted More... | |
| #define | GMAC_ISR_PDRSFR (0x1u << 23) |
| (GMAC_ISR) PDelay Response Frame Received More... | |
| #define | GMAC_ISR_PDRSFT (0x1u << 25) |
| (GMAC_ISR) PDelay Response Frame Transmitted More... | |
| #define | GMAC_ISR_PFNZ (0x1u << 12) |
| (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received More... | |
| #define | GMAC_ISR_PFTR (0x1u << 14) |
| (GMAC_ISR) Pause Frame Transmitted More... | |
| #define | GMAC_ISR_PTZ (0x1u << 13) |
| (GMAC_ISR) Pause Time Zero More... | |
| #define | GMAC_ISR_RCOMP (0x1u << 1) |
| (GMAC_ISR) Receive Complete More... | |
| #define | GMAC_ISR_RLEX (0x1u << 5) |
| (GMAC_ISR) Retry Limit Exceeded More... | |
| #define | GMAC_ISR_ROVR (0x1u << 10) |
| (GMAC_ISR) Receive Overrun More... | |
| #define | GMAC_ISR_RXUBR (0x1u << 2) |
| (GMAC_ISR) RX Used Bit Read More... | |
| #define | GMAC_ISR_SFR (0x1u << 19) |
| (GMAC_ISR) PTP Sync Frame Received More... | |
| #define | GMAC_ISR_SFT (0x1u << 21) |
| (GMAC_ISR) PTP Sync Frame Transmitted More... | |
| #define | GMAC_ISR_SRI (0x1u << 26) |
| (GMAC_ISR) TSU Seconds Register Increment More... | |
| #define | GMAC_ISR_TCOMP (0x1u << 7) |
| (GMAC_ISR) Transmit Complete More... | |
| #define | GMAC_ISR_TFC (0x1u << 6) |
| (GMAC_ISR) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_ISR_TUR (0x1u << 4) |
| (GMAC_ISR) Transmit Underrun More... | |
| #define | GMAC_ISR_TXUBR (0x1u << 3) |
| (GMAC_ISR) TX Used Bit Read More... | |
| #define | GMAC_ISR_WOL (0x1u << 28) |
| (GMAC_ISR) Wake On LAN More... | |
| #define | GMAC_ISRPQ_HRESP (0x1u << 11) |
| (GMAC_ISRPQ[5]) HRESP Not OK More... | |
| #define | GMAC_ISRPQ_RCOMP (0x1u << 1) |
| (GMAC_ISRPQ[5]) Receive Complete More... | |
| #define | GMAC_ISRPQ_RLEX (0x1u << 5) |
| (GMAC_ISRPQ[5]) Retry Limit Exceeded or Late Collision More... | |
| #define | GMAC_ISRPQ_ROVR (0x1u << 10) |
| (GMAC_ISRPQ[5]) Receive Overrun More... | |
| #define | GMAC_ISRPQ_RXUBR (0x1u << 2) |
| (GMAC_ISRPQ[5]) RX Used Bit Read More... | |
| #define | GMAC_ISRPQ_TCOMP (0x1u << 7) |
| (GMAC_ISRPQ[5]) Transmit Complete More... | |
| #define | GMAC_ISRPQ_TFC (0x1u << 6) |
| (GMAC_ISRPQ[5]) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) |
| (GMAC_JR) Jabbers Received More... | |
| #define | GMAC_JR_JRX_Pos 0 |
| #define | GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) |
| (GMAC_LC) Late Collisions More... | |
| #define | GMAC_LC_LCOL_Pos 0 |
| #define | GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) |
| (GMAC_LFFE) Length Field Frame Errors More... | |
| #define | GMAC_LFFE_LFER_Pos 0 |
| #define | GMAC_MAN_CLTTO (0x1u << 30) |
| (GMAC_MAN) Clause 22 Operation More... | |
| #define | GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) |
| #define | GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) |
| (GMAC_MAN) PHY Data More... | |
| #define | GMAC_MAN_DATA_Pos 0 |
| #define | GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) |
| #define | GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) |
| (GMAC_MAN) Operation More... | |
| #define | GMAC_MAN_OP_Pos 28 |
| #define | GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) |
| #define | GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) |
| (GMAC_MAN) PHY Address More... | |
| #define | GMAC_MAN_PHYA_Pos 23 |
| #define | GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) |
| #define | GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) |
| (GMAC_MAN) Register Address More... | |
| #define | GMAC_MAN_REGA_Pos 18 |
| #define | GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) |
| #define | GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) |
| (GMAC_MAN) Write Ten More... | |
| #define | GMAC_MAN_WTN_Pos 16 |
| #define | GMAC_MAN_WZO (0x1u << 31) |
| (GMAC_MAN) Write ZERO More... | |
| #define | GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) |
| (GMAC_MCF) Multiple Collision More... | |
| #define | GMAC_MCF_MCOL_Pos 0 |
| #define | GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) |
| (GMAC_MFR) Multicast Frames Received without Error More... | |
| #define | GMAC_MFR_MFRX_Pos 0 |
| #define | GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) |
| (GMAC_MFT) Multicast Frames Transmitted without Error More... | |
| #define | GMAC_MFT_MFTX_Pos 0 |
| #define | GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) |
| (GMAC_MID) Module Identification Number More... | |
| #define | GMAC_MID_MID_Pos 16 |
| #define | GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) |
| (GMAC_MID) Module Revision More... | |
| #define | GMAC_MID_MREV_Pos 0 |
| #define | GMAC_NCFGR_CAF (0x1u << 4) |
| (GMAC_NCFGR) Copy All Frames More... | |
| #define | GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) |
| #define | GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) |
| (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) More... | |
| #define | GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) |
| (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) More... | |
| #define | GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) |
| (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) More... | |
| #define | GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) |
| (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) More... | |
| #define | GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) |
| (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) More... | |
| #define | GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) |
| (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) More... | |
| #define | GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) |
| (GMAC_NCFGR) MDC CLock Division More... | |
| #define | GMAC_NCFGR_CLK_Pos 18 |
| #define | GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) |
| #define | GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) |
| (GMAC_NCFGR) Data Bus Width More... | |
| #define | GMAC_NCFGR_DBW_Pos 21 |
| #define | GMAC_NCFGR_DCPF (0x1u << 23) |
| (GMAC_NCFGR) Disable Copy of Pause Frames More... | |
| #define | GMAC_NCFGR_DNVLAN (0x1u << 2) |
| (GMAC_NCFGR) Discard Non-VLAN FRAMES More... | |
| #define | GMAC_NCFGR_EFRHD (0x1u << 25) |
| (GMAC_NCFGR) Enable Frames Received in Half Duplex More... | |
| #define | GMAC_NCFGR_FD (0x1u << 1) |
| (GMAC_NCFGR) Full Duplex More... | |
| #define | GMAC_NCFGR_IPGSEN (0x1u << 28) |
| (GMAC_NCFGR) IP Stretch Enable More... | |
| #define | GMAC_NCFGR_IRXER (0x1u << 30) |
| (GMAC_NCFGR) Ignore IPG GRXER More... | |
| #define | GMAC_NCFGR_IRXFCS (0x1u << 26) |
| (GMAC_NCFGR) Ignore RX FCS More... | |
| #define | GMAC_NCFGR_JFRAME (0x1u << 3) |
| (GMAC_NCFGR) Jumbo Frame Size More... | |
| #define | GMAC_NCFGR_LFERD (0x1u << 16) |
| (GMAC_NCFGR) Length Field Error Frame Discard More... | |
| #define | GMAC_NCFGR_MAXFS (0x1u << 8) |
| (GMAC_NCFGR) 1536 Maximum Frame Size More... | |
| #define | GMAC_NCFGR_MTIHEN (0x1u << 6) |
| (GMAC_NCFGR) Multicast Hash Enable More... | |
| #define | GMAC_NCFGR_NBC (0x1u << 5) |
| (GMAC_NCFGR) No Broadcast More... | |
| #define | GMAC_NCFGR_PEN (0x1u << 13) |
| (GMAC_NCFGR) Pause Enable More... | |
| #define | GMAC_NCFGR_RFCS (0x1u << 17) |
| (GMAC_NCFGR) Remove FCS More... | |
| #define | GMAC_NCFGR_RTY (0x1u << 12) |
| (GMAC_NCFGR) Retry Test More... | |
| #define | GMAC_NCFGR_RXBP (0x1u << 29) |
| (GMAC_NCFGR) Receive Bad Preamble More... | |
| #define | GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) |
| #define | GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) |
| (GMAC_NCFGR) Receive Buffer Offset More... | |
| #define | GMAC_NCFGR_RXBUFO_Pos 14 |
| #define | GMAC_NCFGR_RXCOEN (0x1u << 24) |
| (GMAC_NCFGR) Receive Checksum Offload Enable More... | |
| #define | GMAC_NCFGR_SPD (0x1u << 0) |
| (GMAC_NCFGR) Speed More... | |
| #define | GMAC_NCFGR_UNIHEN (0x1u << 7) |
| (GMAC_NCFGR) Unicast Hash Enable More... | |
| #define | GMAC_NCR_BP (0x1u << 8) |
| (GMAC_NCR) Back pressure More... | |
| #define | GMAC_NCR_CLRSTAT (0x1u << 5) |
| (GMAC_NCR) Clear Statistics Registers More... | |
| #define | GMAC_NCR_ENPBPR (0x1u << 16) |
| (GMAC_NCR) Enable PFC Priority-based Pause Reception More... | |
| #define | GMAC_NCR_FNP (0x1u << 18) |
| (GMAC_NCR) Flush Next Packet More... | |
| #define | GMAC_NCR_INCSTAT (0x1u << 6) |
| (GMAC_NCR) Increment Statistics Registers More... | |
| #define | GMAC_NCR_LBL (0x1u << 1) |
| (GMAC_NCR) Loop Back Local More... | |
| #define | GMAC_NCR_MPE (0x1u << 4) |
| (GMAC_NCR) Management Port Enable More... | |
| #define | GMAC_NCR_RXEN (0x1u << 2) |
| (GMAC_NCR) Receive Enable More... | |
| #define | GMAC_NCR_SRTSM (0x1u << 15) |
| (GMAC_NCR) Store Receive Time Stamp to Memory More... | |
| #define | GMAC_NCR_THALT (0x1u << 10) |
| (GMAC_NCR) Transmit Halt More... | |
| #define | GMAC_NCR_TSTART (0x1u << 9) |
| (GMAC_NCR) Start Transmission More... | |
| #define | GMAC_NCR_TXEN (0x1u << 3) |
| (GMAC_NCR) Transmit Enable More... | |
| #define | GMAC_NCR_TXPBPF (0x1u << 17) |
| (GMAC_NCR) Transmit PFC Priority-based Pause Frame More... | |
| #define | GMAC_NCR_TXPF (0x1u << 11) |
| (GMAC_NCR) Transmit Pause Frame More... | |
| #define | GMAC_NCR_TXZQPF (0x1u << 12) |
| (GMAC_NCR) Transmit Zero Quantum Pause Frame More... | |
| #define | GMAC_NCR_WESTAT (0x1u << 7) |
| (GMAC_NCR) Write Enable for Statistics Registers More... | |
| #define | GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) |
| #define | GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) |
| (GMAC_NSC) 1588 Timer Nanosecond Comparison Value More... | |
| #define | GMAC_NSC_NANOSEC_Pos 0 |
| #define | GMAC_NSR_IDLE (0x1u << 2) |
| (GMAC_NSR) PHY Management Logic Idle More... | |
| #define | GMAC_NSR_MDIO (0x1u << 1) |
| (GMAC_NSR) MDIO Input Status More... | |
| #define | GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) |
| (GMAC_OFR) Oversized Frames Received More... | |
| #define | GMAC_OFR_OFRX_Pos 0 |
| #define | GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) |
| (GMAC_ORHI) Received Octets More... | |
| #define | GMAC_ORHI_RXO_Pos 0 |
| #define | GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) |
| (GMAC_ORLO) Received Octets More... | |
| #define | GMAC_ORLO_RXO_Pos 0 |
| #define | GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) |
| (GMAC_OTHI) Transmitted Octets More... | |
| #define | GMAC_OTHI_TXO_Pos 0 |
| #define | GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) |
| (GMAC_OTLO) Transmitted Octets More... | |
| #define | GMAC_OTLO_TXO_Pos 0 |
| #define | GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) |
| (GMAC_PEFRN) Register Update More... | |
| #define | GMAC_PEFRN_RUD_Pos 0 |
| #define | GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) |
| (GMAC_PEFRSH) Register Update More... | |
| #define | GMAC_PEFRSH_RUD_Pos 0 |
| #define | GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) |
| (GMAC_PEFRSL) Register Update More... | |
| #define | GMAC_PEFRSL_RUD_Pos 0 |
| #define | GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) |
| (GMAC_PEFTN) Register Update More... | |
| #define | GMAC_PEFTN_RUD_Pos 0 |
| #define | GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) |
| (GMAC_PEFTSH) Register Update More... | |
| #define | GMAC_PEFTSH_RUD_Pos 0 |
| #define | GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) |
| (GMAC_PEFTSL) Register Update More... | |
| #define | GMAC_PEFTSL_RUD_Pos 0 |
| #define | GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) |
| (GMAC_PFR) Pause Frames Received Register More... | |
| #define | GMAC_PFR_PFRX_Pos 0 |
| #define | GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) |
| (GMAC_PFT) Pause Frames Transmitted Register More... | |
| #define | GMAC_PFT_PFTX_Pos 0 |
| #define | GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) |
| #define | GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) |
| (GMAC_RBQB) Receive Buffer Queue Base Address More... | |
| #define | GMAC_RBQB_ADDR_Pos 2 |
| #define | GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) |
| #define | GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) |
| (GMAC_RBQBAPQ[5]) Receive Buffer Queue Base Address More... | |
| #define | GMAC_RBQBAPQ_RXBQBA_Pos 2 |
| #define | GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) |
| #define | GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) |
| (GMAC_RBSRPQ[5]) Receive Buffer Size More... | |
| #define | GMAC_RBSRPQ_RBS_Pos 0 |
| #define | GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) |
| #define | GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) |
| (GMAC_RJFML) Frame Max Length More... | |
| #define | GMAC_RJFML_FML_Pos 0 |
| #define | GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) |
| (GMAC_ROE) Receive Overruns More... | |
| #define | GMAC_ROE_RXOVR_Pos 0 |
| #define | GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) |
| (GMAC_RPQ) Received Pause Quantum More... | |
| #define | GMAC_RPQ_RPQ_Pos 0 |
| #define | GMAC_RPSF_ENRXP (0x1u << 31) |
| (GMAC_RPSF) Enable RX Partial Store and Forward Operation More... | |
| #define | GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) |
| #define | GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) |
| (GMAC_RPSF) Receive Partial Store and Forward Address More... | |
| #define | GMAC_RPSF_RPB1ADR_Pos 0 |
| #define | GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) |
| (GMAC_RRE) Receive Resource Errors More... | |
| #define | GMAC_RRE_RXRER_Pos 0 |
| #define | GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) |
| (GMAC_RSE) Receive Symbol Errors More... | |
| #define | GMAC_RSE_RXSE_Pos 0 |
| #define | GMAC_RSR_BNA (0x1u << 0) |
| (GMAC_RSR) Buffer Not Available More... | |
| #define | GMAC_RSR_HNO (0x1u << 3) |
| (GMAC_RSR) HRESP Not OK More... | |
| #define | GMAC_RSR_REC (0x1u << 1) |
| (GMAC_RSR) Frame Received More... | |
| #define | GMAC_RSR_RXOVR (0x1u << 2) |
| (GMAC_RSR) Receive Overrun More... | |
| #define | GMAC_RXLPI_COUNT_Msk (0xffffu << GMAC_RXLPI_COUNT_Pos) |
| (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) More... | |
| #define | GMAC_RXLPI_COUNT_Pos 0 |
| #define | GMAC_RXLPITIME_LPITIME_Msk (0xffffffu << GMAC_RXLPITIME_LPITIME_Pos) |
| (GMAC_RXLPITIME) Time in LPI (cleared on read) More... | |
| #define | GMAC_RXLPITIME_LPITIME_Pos 0 |
| #define | GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) |
| #define | GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) |
| (GMAC_SAB) Specific Address 1 More... | |
| #define | GMAC_SAB_ADDR_Pos 0 |
| #define | GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) |
| #define | GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) |
| (GMAC_SAMB1) Specific Address 1 Mask More... | |
| #define | GMAC_SAMB1_ADDR_Pos 0 |
| #define | GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) |
| #define | GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) |
| (GMAC_SAMT1) Specific Address 1 Mask More... | |
| #define | GMAC_SAMT1_ADDR_Pos 0 |
| #define | GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) |
| #define | GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) |
| (GMAC_SAT) Specific Address 1 More... | |
| #define | GMAC_SAT_ADDR_Pos 0 |
| #define | GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) |
| (GMAC_SCF) Single Collision More... | |
| #define | GMAC_SCF_SCOL_Pos 0 |
| #define | GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) |
| #define | GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) |
| (GMAC_SCH) 1588 Timer Second Comparison Value More... | |
| #define | GMAC_SCH_SEC_Pos 0 |
| #define | GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) |
| #define | GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) |
| (GMAC_SCL) 1588 Timer Second Comparison Value More... | |
| #define | GMAC_SCL_SEC_Pos 0 |
| #define | GMAC_ST1RPQ_DSTCE (0x1u << 28) |
| (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable More... | |
| #define | GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) |
| #define | GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) |
| (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match More... | |
| #define | GMAC_ST1RPQ_DSTCM_Pos 4 |
| #define | GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) |
| #define | GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) |
| (GMAC_ST1RPQ[4]) Queue Number (0-5) More... | |
| #define | GMAC_ST1RPQ_QNB_Pos 0 |
| #define | GMAC_ST1RPQ_UDPE (0x1u << 29) |
| (GMAC_ST1RPQ[4]) UDP Port Match Enable More... | |
| #define | GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) |
| #define | GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) |
| (GMAC_ST1RPQ[4]) UDP Port Match More... | |
| #define | GMAC_ST1RPQ_UDPM_Pos 12 |
| #define | GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) |
| #define | GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) |
| (GMAC_ST2CW00) Compare Value More... | |
| #define | GMAC_ST2CW00_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) |
| #define | GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) |
| (GMAC_ST2CW00) Mask Value More... | |
| #define | GMAC_ST2CW00_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) |
| #define | GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) |
| (GMAC_ST2CW010) Compare Value More... | |
| #define | GMAC_ST2CW010_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) |
| #define | GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) |
| (GMAC_ST2CW010) Mask Value More... | |
| #define | GMAC_ST2CW010_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) |
| #define | GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) |
| (GMAC_ST2CW011) Compare Value More... | |
| #define | GMAC_ST2CW011_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) |
| #define | GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) |
| (GMAC_ST2CW011) Mask Value More... | |
| #define | GMAC_ST2CW011_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) |
| #define | GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) |
| (GMAC_ST2CW012) Compare Value More... | |
| #define | GMAC_ST2CW012_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) |
| #define | GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) |
| (GMAC_ST2CW012) Mask Value More... | |
| #define | GMAC_ST2CW012_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) |
| #define | GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) |
| (GMAC_ST2CW013) Compare Value More... | |
| #define | GMAC_ST2CW013_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) |
| #define | GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) |
| (GMAC_ST2CW013) Mask Value More... | |
| #define | GMAC_ST2CW013_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) |
| #define | GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) |
| (GMAC_ST2CW014) Compare Value More... | |
| #define | GMAC_ST2CW014_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) |
| #define | GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) |
| (GMAC_ST2CW014) Mask Value More... | |
| #define | GMAC_ST2CW014_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) |
| #define | GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) |
| (GMAC_ST2CW015) Compare Value More... | |
| #define | GMAC_ST2CW015_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) |
| #define | GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) |
| (GMAC_ST2CW015) Mask Value More... | |
| #define | GMAC_ST2CW015_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) |
| #define | GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) |
| (GMAC_ST2CW016) Compare Value More... | |
| #define | GMAC_ST2CW016_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) |
| #define | GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) |
| (GMAC_ST2CW016) Mask Value More... | |
| #define | GMAC_ST2CW016_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) |
| #define | GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) |
| (GMAC_ST2CW017) Compare Value More... | |
| #define | GMAC_ST2CW017_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) |
| #define | GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) |
| (GMAC_ST2CW017) Mask Value More... | |
| #define | GMAC_ST2CW017_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) |
| #define | GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) |
| (GMAC_ST2CW018) Compare Value More... | |
| #define | GMAC_ST2CW018_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) |
| #define | GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) |
| (GMAC_ST2CW018) Mask Value More... | |
| #define | GMAC_ST2CW018_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) |
| #define | GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) |
| (GMAC_ST2CW019) Compare Value More... | |
| #define | GMAC_ST2CW019_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) |
| #define | GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) |
| (GMAC_ST2CW019) Mask Value More... | |
| #define | GMAC_ST2CW019_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) |
| #define | GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) |
| (GMAC_ST2CW01) Compare Value More... | |
| #define | GMAC_ST2CW01_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) |
| #define | GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) |
| (GMAC_ST2CW01) Mask Value More... | |
| #define | GMAC_ST2CW01_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) |
| #define | GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) |
| (GMAC_ST2CW020) Compare Value More... | |
| #define | GMAC_ST2CW020_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) |
| #define | GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) |
| (GMAC_ST2CW020) Mask Value More... | |
| #define | GMAC_ST2CW020_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) |
| #define | GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) |
| (GMAC_ST2CW021) Compare Value More... | |
| #define | GMAC_ST2CW021_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) |
| #define | GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) |
| (GMAC_ST2CW021) Mask Value More... | |
| #define | GMAC_ST2CW021_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) |
| #define | GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) |
| (GMAC_ST2CW022) Compare Value More... | |
| #define | GMAC_ST2CW022_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) |
| #define | GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) |
| (GMAC_ST2CW022) Mask Value More... | |
| #define | GMAC_ST2CW022_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) |
| #define | GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) |
| (GMAC_ST2CW023) Compare Value More... | |
| #define | GMAC_ST2CW023_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) |
| #define | GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) |
| (GMAC_ST2CW023) Mask Value More... | |
| #define | GMAC_ST2CW023_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) |
| #define | GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) |
| (GMAC_ST2CW02) Compare Value More... | |
| #define | GMAC_ST2CW02_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) |
| #define | GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) |
| (GMAC_ST2CW02) Mask Value More... | |
| #define | GMAC_ST2CW02_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) |
| #define | GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) |
| (GMAC_ST2CW03) Compare Value More... | |
| #define | GMAC_ST2CW03_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) |
| #define | GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) |
| (GMAC_ST2CW03) Mask Value More... | |
| #define | GMAC_ST2CW03_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) |
| #define | GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) |
| (GMAC_ST2CW04) Compare Value More... | |
| #define | GMAC_ST2CW04_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) |
| #define | GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) |
| (GMAC_ST2CW04) Mask Value More... | |
| #define | GMAC_ST2CW04_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) |
| #define | GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) |
| (GMAC_ST2CW05) Compare Value More... | |
| #define | GMAC_ST2CW05_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) |
| #define | GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) |
| (GMAC_ST2CW05) Mask Value More... | |
| #define | GMAC_ST2CW05_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) |
| #define | GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) |
| (GMAC_ST2CW06) Compare Value More... | |
| #define | GMAC_ST2CW06_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) |
| #define | GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) |
| (GMAC_ST2CW06) Mask Value More... | |
| #define | GMAC_ST2CW06_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) |
| #define | GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) |
| (GMAC_ST2CW07) Compare Value More... | |
| #define | GMAC_ST2CW07_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) |
| #define | GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) |
| (GMAC_ST2CW07) Mask Value More... | |
| #define | GMAC_ST2CW07_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) |
| #define | GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) |
| (GMAC_ST2CW08) Compare Value More... | |
| #define | GMAC_ST2CW08_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) |
| #define | GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) |
| (GMAC_ST2CW08) Mask Value More... | |
| #define | GMAC_ST2CW08_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) |
| #define | GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) |
| (GMAC_ST2CW09) Compare Value More... | |
| #define | GMAC_ST2CW09_COMPVAL_Pos 16 |
| #define | GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) |
| #define | GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) |
| (GMAC_ST2CW09) Mask Value More... | |
| #define | GMAC_ST2CW09_MASKVAL_Pos 0 |
| #define | GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW10) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW10) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW10) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) |
| (GMAC_ST2CW10) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW10_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) |
| (GMAC_ST2CW10) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW10_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW110) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW110) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW110) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) |
| (GMAC_ST2CW110) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW110_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) |
| (GMAC_ST2CW110) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW110_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW111) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW111) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW111) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) |
| (GMAC_ST2CW111) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW111_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) |
| (GMAC_ST2CW111) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW111_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW112) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW112) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW112) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) |
| (GMAC_ST2CW112) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW112_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) |
| (GMAC_ST2CW112) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW112_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW113) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW113) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW113) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) |
| (GMAC_ST2CW113) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW113_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) |
| (GMAC_ST2CW113) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW113_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW114) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW114) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW114) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) |
| (GMAC_ST2CW114) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW114_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) |
| (GMAC_ST2CW114) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW114_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW115) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW115) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW115) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) |
| (GMAC_ST2CW115) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW115_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) |
| (GMAC_ST2CW115) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW115_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW116) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW116) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW116) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) |
| (GMAC_ST2CW116) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW116_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) |
| (GMAC_ST2CW116) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW116_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW117) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW117) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW117) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) |
| (GMAC_ST2CW117) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW117_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) |
| (GMAC_ST2CW117) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW117_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW118) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW118) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW118) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) |
| (GMAC_ST2CW118) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW118_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) |
| (GMAC_ST2CW118) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW118_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW119) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW119) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW119) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) |
| (GMAC_ST2CW119) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW119_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) |
| (GMAC_ST2CW119) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW119_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW11) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW11) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW11) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) |
| (GMAC_ST2CW11) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW11_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) |
| (GMAC_ST2CW11) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW11_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW120) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW120) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW120) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) |
| (GMAC_ST2CW120) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW120_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) |
| (GMAC_ST2CW120) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW120_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW121) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW121) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW121) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) |
| (GMAC_ST2CW121) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW121_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) |
| (GMAC_ST2CW121) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW121_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW122) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW122) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW122) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) |
| (GMAC_ST2CW122) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW122_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) |
| (GMAC_ST2CW122) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW122_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW123) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW123) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW123) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) |
| (GMAC_ST2CW123) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW123_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) |
| (GMAC_ST2CW123) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW123_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW12) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW12) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW12) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) |
| (GMAC_ST2CW12) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW12_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) |
| (GMAC_ST2CW12) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW12_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW13) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW13) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW13) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) |
| (GMAC_ST2CW13) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW13_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) |
| (GMAC_ST2CW13) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW13_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW14) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW14) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW14) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) |
| (GMAC_ST2CW14) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW14_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) |
| (GMAC_ST2CW14) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW14_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW15) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW15) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW15) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) |
| (GMAC_ST2CW15) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW15_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) |
| (GMAC_ST2CW15) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW15_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW16) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW16) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW16) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) |
| (GMAC_ST2CW16) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW16_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) |
| (GMAC_ST2CW16) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW16_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW17) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW17) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW17) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) |
| (GMAC_ST2CW17) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW17_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) |
| (GMAC_ST2CW17) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW17_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW18) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW18) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW18) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) |
| (GMAC_ST2CW18) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW18_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) |
| (GMAC_ST2CW18) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW18_OFFSVAL_Pos 0 |
| #define | GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) |
| #define | GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) |
| (GMAC_ST2CW19) Offset from the byte after the EtherType field More... | |
| #define | GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) |
| (GMAC_ST2CW19) Offset from the start of the frame More... | |
| #define | GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) |
| (GMAC_ST2CW19) Offset from the byte after the IP header field More... | |
| #define | GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) |
| (GMAC_ST2CW19) Ethernet Frame Offset Start More... | |
| #define | GMAC_ST2CW19_OFFSSTRT_Pos 7 |
| #define | GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) |
| (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field More... | |
| #define | GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) |
| #define | GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) |
| (GMAC_ST2CW19) Offset Value in Bytes More... | |
| #define | GMAC_ST2CW19_OFFSVAL_Pos 0 |
| #define | GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) |
| #define | GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) |
| (GMAC_ST2ER[4]) Ethertype Compare Value More... | |
| #define | GMAC_ST2ER_COMPVAL_Pos 0 |
| #define | GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) |
| #define | GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) |
| (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x More... | |
| #define | GMAC_ST2RPQ_COMPA_Pos 13 |
| #define | GMAC_ST2RPQ_COMPAE (0x1u << 18) |
| (GMAC_ST2RPQ[8]) Compare A Enable More... | |
| #define | GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) |
| #define | GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) |
| (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x More... | |
| #define | GMAC_ST2RPQ_COMPB_Pos 19 |
| #define | GMAC_ST2RPQ_COMPBE (0x1u << 24) |
| (GMAC_ST2RPQ[8]) Compare B Enable More... | |
| #define | GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) |
| #define | GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) |
| (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x More... | |
| #define | GMAC_ST2RPQ_COMPC_Pos 25 |
| #define | GMAC_ST2RPQ_COMPCE (0x1u << 30) |
| (GMAC_ST2RPQ[8]) Compare C Enable More... | |
| #define | GMAC_ST2RPQ_ETHE (0x1u << 12) |
| (GMAC_ST2RPQ[8]) EtherType Enable More... | |
| #define | GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) |
| #define | GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) |
| (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x More... | |
| #define | GMAC_ST2RPQ_I2ETH_Pos 9 |
| #define | GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) |
| #define | GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) |
| (GMAC_ST2RPQ[8]) Queue Number (0-5) More... | |
| #define | GMAC_ST2RPQ_QNB_Pos 0 |
| #define | GMAC_ST2RPQ_VLANE (0x1u << 8) |
| (GMAC_ST2RPQ[8]) VLAN Enable More... | |
| #define | GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) |
| #define | GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) |
| (GMAC_ST2RPQ[8]) VLAN Priority More... | |
| #define | GMAC_ST2RPQ_VLANP_Pos 4 |
| #define | GMAC_SVLAN_ESVLAN (0x1u << 31) |
| (GMAC_SVLAN) Enable Stacked VLAN Processing Mode More... | |
| #define | GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) |
| #define | GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) |
| (GMAC_SVLAN) User Defined VLAN_TYPE Field More... | |
| #define | GMAC_SVLAN_VLAN_TYPE_Pos 0 |
| #define | GMAC_TA_ADJ (0x1u << 31) |
| (GMAC_TA) Adjust 1588 Timer More... | |
| #define | GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) |
| #define | GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) |
| (GMAC_TA) Increment/Decrement More... | |
| #define | GMAC_TA_ITDT_Pos 0 |
| #define | GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) |
| (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error More... | |
| #define | GMAC_TBFR1023_NFRX_Pos 0 |
| #define | GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) |
| (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error More... | |
| #define | GMAC_TBFR127_NFRX_Pos 0 |
| #define | GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) |
| (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error More... | |
| #define | GMAC_TBFR1518_NFRX_Pos 0 |
| #define | GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) |
| (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error More... | |
| #define | GMAC_TBFR255_NFRX_Pos 0 |
| #define | GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) |
| (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error More... | |
| #define | GMAC_TBFR511_NFRX_Pos 0 |
| #define | GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) |
| (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error More... | |
| #define | GMAC_TBFT1023_NFTX_Pos 0 |
| #define | GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) |
| (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error More... | |
| #define | GMAC_TBFT127_NFTX_Pos 0 |
| #define | GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) |
| (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error More... | |
| #define | GMAC_TBFT1518_NFTX_Pos 0 |
| #define | GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) |
| (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error More... | |
| #define | GMAC_TBFT255_NFTX_Pos 0 |
| #define | GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) |
| (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error More... | |
| #define | GMAC_TBFT511_NFTX_Pos 0 |
| #define | GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) |
| #define | GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) |
| (GMAC_TBQB) Transmit Buffer Queue Base Address More... | |
| #define | GMAC_TBQB_ADDR_Pos 2 |
| #define | GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) |
| #define | GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) |
| (GMAC_TBQBAPQ[5]) Transmit Buffer Queue Base Address More... | |
| #define | GMAC_TBQBAPQ_TXBQBA_Pos 2 |
| #define | GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) |
| (GMAC_TCE) TCP Checksum Errors More... | |
| #define | GMAC_TCE_TCKER_Pos 0 |
| #define | GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) |
| #define | GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) |
| (GMAC_TI) Alternative Count Nanoseconds More... | |
| #define | GMAC_TI_ACNS_Pos 8 |
| #define | GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) |
| #define | GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) |
| (GMAC_TI) Count Nanoseconds More... | |
| #define | GMAC_TI_CNS_Pos 0 |
| #define | GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) |
| #define | GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) |
| (GMAC_TI) Number of Increments More... | |
| #define | GMAC_TI_NIT_Pos 16 |
| #define | GMAC_TIDM1_ENID1 (0x1u << 31) |
| (GMAC_TIDM1) Enable Copying of TID Matched Frames More... | |
| #define | GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) |
| #define | GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) |
| (GMAC_TIDM1) Type ID Match 1 More... | |
| #define | GMAC_TIDM1_TID_Pos 0 |
| #define | GMAC_TIDM2_ENID2 (0x1u << 31) |
| (GMAC_TIDM2) Enable Copying of TID Matched Frames More... | |
| #define | GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) |
| #define | GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) |
| (GMAC_TIDM2) Type ID Match 2 More... | |
| #define | GMAC_TIDM2_TID_Pos 0 |
| #define | GMAC_TIDM3_ENID3 (0x1u << 31) |
| (GMAC_TIDM3) Enable Copying of TID Matched Frames More... | |
| #define | GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) |
| #define | GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) |
| (GMAC_TIDM3) Type ID Match 3 More... | |
| #define | GMAC_TIDM3_TID_Pos 0 |
| #define | GMAC_TIDM4_ENID4 (0x1u << 31) |
| (GMAC_TIDM4) Enable Copying of TID Matched Frames More... | |
| #define | GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) |
| #define | GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) |
| (GMAC_TIDM4) Type ID Match 4 More... | |
| #define | GMAC_TIDM4_TID_Pos 0 |
| #define | GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) |
| #define | GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) |
| (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register More... | |
| #define | GMAC_TISUBN_LSBTIR_Pos 0 |
| #define | GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) |
| (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error More... | |
| #define | GMAC_TMXBFR_NFRX_Pos 0 |
| #define | GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) |
| #define | GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) |
| (GMAC_TN) Timer Count in Nanoseconds More... | |
| #define | GMAC_TN_TNS_Pos 0 |
| #define | GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) |
| #define | GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) |
| (GMAC_TPFCP) Priority Enable Vector More... | |
| #define | GMAC_TPFCP_PEV_Pos 0 |
| #define | GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) |
| #define | GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) |
| (GMAC_TPFCP) Pause Quantum More... | |
| #define | GMAC_TPFCP_PQ_Pos 8 |
| #define | GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) |
| #define | GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) |
| (GMAC_TPQ) Transmit Pause Quantum More... | |
| #define | GMAC_TPQ_TPQ_Pos 0 |
| #define | GMAC_TPSF_ENTXP (0x1u << 31) |
| (GMAC_TPSF) Enable TX Partial Store and Forward Operation More... | |
| #define | GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) |
| #define | GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) |
| (GMAC_TPSF) Transmit Partial Store and Forward Address More... | |
| #define | GMAC_TPSF_TPB1ADR_Pos 0 |
| #define | GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) |
| #define | GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) |
| (GMAC_TSH) Timer Count in Seconds More... | |
| #define | GMAC_TSH_TCS_Pos 0 |
| #define | GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) |
| #define | GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) |
| (GMAC_TSL) Timer Count in Seconds More... | |
| #define | GMAC_TSL_TCS_Pos 0 |
| #define | GMAC_TSR_COL (0x1u << 1) |
| (GMAC_TSR) Collision Occurred More... | |
| #define | GMAC_TSR_HRESP (0x1u << 8) |
| (GMAC_TSR) HRESP Not OK More... | |
| #define | GMAC_TSR_RLE (0x1u << 2) |
| (GMAC_TSR) Retry Limit Exceeded More... | |
| #define | GMAC_TSR_TFC (0x1u << 4) |
| (GMAC_TSR) Transmit Frame Corruption Due to AHB Error More... | |
| #define | GMAC_TSR_TXCOMP (0x1u << 5) |
| (GMAC_TSR) Transmit Complete More... | |
| #define | GMAC_TSR_TXGO (0x1u << 3) |
| (GMAC_TSR) Transmit Go More... | |
| #define | GMAC_TSR_UBR (0x1u << 0) |
| (GMAC_TSR) Used Bit Read More... | |
| #define | GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) |
| (GMAC_TUR) Transmit Underruns More... | |
| #define | GMAC_TUR_TXUNR_Pos 0 |
| #define | GMAC_TXLPI_COUNT_Msk (0xffffu << GMAC_TXLPI_COUNT_Pos) |
| (GMAC_TXLPI) Count of LPI transitions (cleared on read) More... | |
| #define | GMAC_TXLPI_COUNT_Pos 0 |
| #define | GMAC_TXLPITIME_LPITIME_Msk (0xffffffu << GMAC_TXLPITIME_LPITIME_Pos) |
| (GMAC_TXLPITIME) Time in LPI (cleared on read) More... | |
| #define | GMAC_TXLPITIME_LPITIME_Pos 0 |
| #define | GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) |
| (GMAC_UCE) UDP Checksum Errors More... | |
| #define | GMAC_UCE_UCKER_Pos 0 |
| #define | GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) |
| (GMAC_UFR) Undersize Frames Received More... | |
| #define | GMAC_UFR_UFRX_Pos 0 |
| #define | GMAC_UR_RMII (0x1u << 0) |
| (GMAC_UR) Reduced MII Mode More... | |
| #define | GMAC_WOL_ARP (0x1u << 17) |
| (GMAC_WOL) ARP Request IP Address More... | |
| #define | GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) |
| #define | GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) |
| (GMAC_WOL) ARP Request IP Address More... | |
| #define | GMAC_WOL_IP_Pos 0 |
| #define | GMAC_WOL_MAG (0x1u << 16) |
| (GMAC_WOL) Magic Packet Event Enable More... | |
| #define | GMAC_WOL_MTI (0x1u << 19) |
| (GMAC_WOL) Multicast Hash Event Enable More... | |
| #define | GMAC_WOL_SA1 (0x1u << 18) |
| (GMAC_WOL) Specific Address Register 1 Event Enable More... | |
| #define | GMACSA_NUMBER 4 |
| Gmac hardware registers. More... | |
SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC
| #define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) |
(GMAC_AE) Alignment Errors
Definition at line 693 of file component/gmac.h.
| #define GMAC_AE_AER_Pos 0 |
Definition at line 692 of file component/gmac.h.
| #define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) |
(GMAC_BCFR) Broadcast Frames Received without Error
Definition at line 645 of file component/gmac.h.
| #define GMAC_BCFR_BFRX_Pos 0 |
Definition at line 644 of file component/gmac.h.
| #define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) |
(GMAC_BCFT) Broadcast Frames Transmitted without Error
Definition at line 585 of file component/gmac.h.
| #define GMAC_BCFT_BFTX_Pos 0 |
Definition at line 584 of file component/gmac.h.
| #define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) |
(GMAC_BFR64) 64 Byte Frames Received without Error
Definition at line 654 of file component/gmac.h.
| #define GMAC_BFR64_NFRX_Pos 0 |
Definition at line 653 of file component/gmac.h.
| #define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) |
(GMAC_BFT64) 64 Byte Frames Transmitted without Error
Definition at line 594 of file component/gmac.h.
| #define GMAC_BFT64_NFTX_Pos 0 |
Definition at line 593 of file component/gmac.h.
| #define GMAC_CBSCR_QAE (0x1u << 1) |
(GMAC_CBSCR) Queue A CBS Enable
Definition at line 798 of file component/gmac.h.
| #define GMAC_CBSCR_QBE (0x1u << 0) |
(GMAC_CBSCR) Queue B CBS Enable
Definition at line 797 of file component/gmac.h.
| #define GMAC_CBSISQA_IS | ( | value | ) | ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) |
Definition at line 802 of file component/gmac.h.
| #define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) |
(GMAC_CBSISQA) IdleSlope
Definition at line 801 of file component/gmac.h.
| #define GMAC_CBSISQA_IS_Pos 0 |
Definition at line 800 of file component/gmac.h.
| #define GMAC_CBSISQB_IS | ( | value | ) | ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) |
Definition at line 806 of file component/gmac.h.
| #define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) |
(GMAC_CBSISQB) IdleSlope
Definition at line 805 of file component/gmac.h.
| #define GMAC_CBSISQB_IS_Pos 0 |
Definition at line 804 of file component/gmac.h.
| #define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) |
(GMAC_CSE) Carrier Sense Error
Definition at line 633 of file component/gmac.h.
| #define GMAC_CSE_CSR_Pos 0 |
Definition at line 632 of file component/gmac.h.
| #define GMAC_DCFGR_DDRP (0x1u << 24) |
(GMAC_DCFGR) DMA Discard Receive Packets
Definition at line 317 of file component/gmac.h.
| #define GMAC_DCFGR_DRBS | ( | value | ) | ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) |
Definition at line 316 of file component/gmac.h.
| #define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) |
(GMAC_DCFGR) DMA Receive Buffer Size
Definition at line 315 of file component/gmac.h.
| #define GMAC_DCFGR_DRBS_Pos 16 |
Definition at line 314 of file component/gmac.h.
| #define GMAC_DCFGR_ESMA (0x1u << 6) |
(GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses
Definition at line 303 of file component/gmac.h.
| #define GMAC_DCFGR_ESPA (0x1u << 7) |
(GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses
Definition at line 304 of file component/gmac.h.
| #define GMAC_DCFGR_FBLDO | ( | value | ) | ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) |
Definition at line 298 of file component/gmac.h.
| #define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) |
(GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts
Definition at line 302 of file component/gmac.h.
| #define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) |
(GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default)
Definition at line 300 of file component/gmac.h.
| #define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) |
(GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts
Definition at line 301 of file component/gmac.h.
| #define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) |
(GMAC_DCFGR) Fixed Burst Length for DMA Data Operations:
Definition at line 297 of file component/gmac.h.
| #define GMAC_DCFGR_FBLDO_Pos 0 |
Definition at line 296 of file component/gmac.h.
| #define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) |
(GMAC_DCFGR) 00001: Always use SINGLE AHB bursts
Definition at line 299 of file component/gmac.h.
| #define GMAC_DCFGR_RXBMS | ( | value | ) | ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) |
Definition at line 307 of file component/gmac.h.
| #define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) |
(GMAC_DCFGR) 4/8 Kbyte Memory Size
Definition at line 308 of file component/gmac.h.
| #define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) |
(GMAC_DCFGR) 4 Kbytes Memory Size
Definition at line 311 of file component/gmac.h.
| #define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) |
(GMAC_DCFGR) 4/2 Kbytes Memory Size
Definition at line 310 of file component/gmac.h.
| #define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) |
(GMAC_DCFGR) Receiver Packet Buffer Memory Size Select
Definition at line 306 of file component/gmac.h.
| #define GMAC_DCFGR_RXBMS_Pos 8 |
Definition at line 305 of file component/gmac.h.
| #define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) |
(GMAC_DCFGR) 4/4 Kbytes Memory Size
Definition at line 309 of file component/gmac.h.
| #define GMAC_DCFGR_TXCOEN (0x1u << 11) |
(GMAC_DCFGR) Transmitter Checksum Generation Offload Enable
Definition at line 313 of file component/gmac.h.
| #define GMAC_DCFGR_TXPBMS (0x1u << 10) |
(GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select
Definition at line 312 of file component/gmac.h.
| #define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) |
(GMAC_DTF) Deferred Transmission
Definition at line 630 of file component/gmac.h.
| #define GMAC_DTF_DEFT_Pos 0 |
Definition at line 629 of file component/gmac.h.
| #define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) |
(GMAC_EC) Excessive Collisions
Definition at line 624 of file component/gmac.h.
| #define GMAC_EC_XCOL_Pos 0 |
Definition at line 623 of file component/gmac.h.
| #define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) |
(GMAC_EFRN) Register Update
Definition at line 751 of file component/gmac.h.
| #define GMAC_EFRN_RUD_Pos 0 |
Definition at line 750 of file component/gmac.h.
| #define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) |
(GMAC_EFRSH) Register Update
Definition at line 562 of file component/gmac.h.
| #define GMAC_EFRSH_RUD_Pos 0 |
Definition at line 561 of file component/gmac.h.
| #define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) |
(GMAC_EFRSL) Register Update
Definition at line 748 of file component/gmac.h.
| #define GMAC_EFRSL_RUD_Pos 0 |
Definition at line 747 of file component/gmac.h.
| #define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) |
(GMAC_EFTN) Register Update
Definition at line 745 of file component/gmac.h.
| #define GMAC_EFTN_RUD_Pos 0 |
Definition at line 744 of file component/gmac.h.
| #define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) |
(GMAC_EFTSH) Register Update
Definition at line 559 of file component/gmac.h.
| #define GMAC_EFTSH_RUD_Pos 0 |
Definition at line 558 of file component/gmac.h.
| #define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) |
(GMAC_EFTSL) Register Update
Definition at line 742 of file component/gmac.h.
| #define GMAC_EFTSL_RUD_Pos 0 |
Definition at line 741 of file component/gmac.h.
| #define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) |
(GMAC_FCSE) Frame Check Sequence Errors
Definition at line 684 of file component/gmac.h.
| #define GMAC_FCSE_FCKR_Pos 0 |
Definition at line 683 of file component/gmac.h.
| #define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) |
(GMAC_FR) Frames Received without Error
Definition at line 642 of file component/gmac.h.
| #define GMAC_FR_FRX_Pos 0 |
Definition at line 641 of file component/gmac.h.
| #define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) |
(GMAC_FT) Frames Transmitted without Error
Definition at line 582 of file component/gmac.h.
| #define GMAC_FT_FTX_Pos 0 |
Definition at line 581 of file component/gmac.h.
| #define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) |
(GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error
Definition at line 612 of file component/gmac.h.
| #define GMAC_GTBFT1518_NFTX_Pos 0 |
Definition at line 611 of file component/gmac.h.
| #define GMAC_HRB_ADDR | ( | value | ) | ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) |
Definition at line 480 of file component/gmac.h.
| #define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) |
(GMAC_HRB) Hash Address
Definition at line 479 of file component/gmac.h.
| #define GMAC_HRB_ADDR_Pos 0 |
Definition at line 478 of file component/gmac.h.
| #define GMAC_HRT_ADDR | ( | value | ) | ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) |
Definition at line 484 of file component/gmac.h.
| #define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) |
(GMAC_HRT) Hash Address
Definition at line 483 of file component/gmac.h.
| #define GMAC_HRT_ADDR_Pos 0 |
Definition at line 482 of file component/gmac.h.
| #define GMAC_IDR_DRQFR (0x1u << 18) |
(GMAC_IDR) PTP Delay Request Frame Received
Definition at line 403 of file component/gmac.h.
| #define GMAC_IDR_DRQFT (0x1u << 20) |
(GMAC_IDR) PTP Delay Request Frame Transmitted
Definition at line 405 of file component/gmac.h.
| #define GMAC_IDR_EXINT (0x1u << 15) |
(GMAC_IDR) External Interrupt
Definition at line 402 of file component/gmac.h.
| #define GMAC_IDR_HRESP (0x1u << 11) |
(GMAC_IDR) HRESP Not OK
Definition at line 398 of file component/gmac.h.
| #define GMAC_IDR_MFS (0x1u << 0) |
(GMAC_IDR) Management Frame Sent
Definition at line 389 of file component/gmac.h.
| #define GMAC_IDR_PDRQFR (0x1u << 22) |
(GMAC_IDR) PDelay Request Frame Received
Definition at line 407 of file component/gmac.h.
| #define GMAC_IDR_PDRQFT (0x1u << 24) |
(GMAC_IDR) PDelay Request Frame Transmitted
Definition at line 409 of file component/gmac.h.
| #define GMAC_IDR_PDRSFR (0x1u << 23) |
(GMAC_IDR) PDelay Response Frame Received
Definition at line 408 of file component/gmac.h.
| #define GMAC_IDR_PDRSFT (0x1u << 25) |
(GMAC_IDR) PDelay Response Frame Transmitted
Definition at line 410 of file component/gmac.h.
| #define GMAC_IDR_PFNZ (0x1u << 12) |
(GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received
Definition at line 399 of file component/gmac.h.
| #define GMAC_IDR_PFTR (0x1u << 14) |
(GMAC_IDR) Pause Frame Transmitted
Definition at line 401 of file component/gmac.h.
| #define GMAC_IDR_PTZ (0x1u << 13) |
(GMAC_IDR) Pause Time Zero
Definition at line 400 of file component/gmac.h.
| #define GMAC_IDR_RCOMP (0x1u << 1) |
(GMAC_IDR) Receive Complete
Definition at line 390 of file component/gmac.h.
| #define GMAC_IDR_RLEX (0x1u << 5) |
(GMAC_IDR) Retry Limit Exceeded or Late Collision
Definition at line 394 of file component/gmac.h.
| #define GMAC_IDR_ROVR (0x1u << 10) |
(GMAC_IDR) Receive Overrun
Definition at line 397 of file component/gmac.h.
| #define GMAC_IDR_RXUBR (0x1u << 2) |
(GMAC_IDR) RX Used Bit Read
Definition at line 391 of file component/gmac.h.
| #define GMAC_IDR_SFR (0x1u << 19) |
(GMAC_IDR) PTP Sync Frame Received
Definition at line 404 of file component/gmac.h.
| #define GMAC_IDR_SFT (0x1u << 21) |
(GMAC_IDR) PTP Sync Frame Transmitted
Definition at line 406 of file component/gmac.h.
| #define GMAC_IDR_SRI (0x1u << 26) |
(GMAC_IDR) TSU Seconds Register Increment
Definition at line 411 of file component/gmac.h.
| #define GMAC_IDR_TCOMP (0x1u << 7) |
(GMAC_IDR) Transmit Complete
Definition at line 396 of file component/gmac.h.
| #define GMAC_IDR_TFC (0x1u << 6) |
(GMAC_IDR) Transmit Frame Corruption Due to AHB Error
Definition at line 395 of file component/gmac.h.
| #define GMAC_IDR_TUR (0x1u << 4) |
(GMAC_IDR) Transmit Underrun
Definition at line 393 of file component/gmac.h.
| #define GMAC_IDR_TXUBR (0x1u << 3) |
(GMAC_IDR) TX Used Bit Read
Definition at line 392 of file component/gmac.h.
| #define GMAC_IDR_WOL (0x1u << 28) |
(GMAC_IDR) Wake On LAN
Definition at line 412 of file component/gmac.h.
| #define GMAC_IDRPQ_HRESP (0x1u << 11) |
(GMAC_IDRPQ[5]) HRESP Not OK
Definition at line 858 of file component/gmac.h.
| #define GMAC_IDRPQ_RCOMP (0x1u << 1) |
(GMAC_IDRPQ[5]) Receive Complete
Definition at line 852 of file component/gmac.h.
| #define GMAC_IDRPQ_RLEX (0x1u << 5) |
(GMAC_IDRPQ[5]) Retry Limit Exceeded or Late Collision
Definition at line 854 of file component/gmac.h.
| #define GMAC_IDRPQ_ROVR (0x1u << 10) |
(GMAC_IDRPQ[5]) Receive Overrun
Definition at line 857 of file component/gmac.h.
| #define GMAC_IDRPQ_RXUBR (0x1u << 2) |
(GMAC_IDRPQ[5]) RX Used Bit Read
Definition at line 853 of file component/gmac.h.
| #define GMAC_IDRPQ_TCOMP (0x1u << 7) |
(GMAC_IDRPQ[5]) Transmit Complete
Definition at line 856 of file component/gmac.h.
| #define GMAC_IDRPQ_TFC (0x1u << 6) |
(GMAC_IDRPQ[5]) Transmit Frame Corruption Due to AHB Error
Definition at line 855 of file component/gmac.h.
| #define GMAC_IER_DRQFR (0x1u << 18) |
(GMAC_IER) PTP Delay Request Frame Received
Definition at line 378 of file component/gmac.h.
| #define GMAC_IER_DRQFT (0x1u << 20) |
(GMAC_IER) PTP Delay Request Frame Transmitted
Definition at line 380 of file component/gmac.h.
| #define GMAC_IER_EXINT (0x1u << 15) |
(GMAC_IER) External Interrupt
Definition at line 377 of file component/gmac.h.
| #define GMAC_IER_HRESP (0x1u << 11) |
(GMAC_IER) HRESP Not OK
Definition at line 373 of file component/gmac.h.
| #define GMAC_IER_MFS (0x1u << 0) |
(GMAC_IER) Management Frame Sent
Definition at line 364 of file component/gmac.h.
| #define GMAC_IER_PDRQFR (0x1u << 22) |
(GMAC_IER) PDelay Request Frame Received
Definition at line 382 of file component/gmac.h.
| #define GMAC_IER_PDRQFT (0x1u << 24) |
(GMAC_IER) PDelay Request Frame Transmitted
Definition at line 384 of file component/gmac.h.
| #define GMAC_IER_PDRSFR (0x1u << 23) |
(GMAC_IER) PDelay Response Frame Received
Definition at line 383 of file component/gmac.h.
| #define GMAC_IER_PDRSFT (0x1u << 25) |
(GMAC_IER) PDelay Response Frame Transmitted
Definition at line 385 of file component/gmac.h.
| #define GMAC_IER_PFNZ (0x1u << 12) |
(GMAC_IER) Pause Frame with Non-zero Pause Quantum Received
Definition at line 374 of file component/gmac.h.
| #define GMAC_IER_PFTR (0x1u << 14) |
(GMAC_IER) Pause Frame Transmitted
Definition at line 376 of file component/gmac.h.
| #define GMAC_IER_PTZ (0x1u << 13) |
(GMAC_IER) Pause Time Zero
Definition at line 375 of file component/gmac.h.
| #define GMAC_IER_RCOMP (0x1u << 1) |
(GMAC_IER) Receive Complete
Definition at line 365 of file component/gmac.h.
| #define GMAC_IER_RLEX (0x1u << 5) |
(GMAC_IER) Retry Limit Exceeded or Late Collision
Definition at line 369 of file component/gmac.h.
| #define GMAC_IER_ROVR (0x1u << 10) |
(GMAC_IER) Receive Overrun
Definition at line 372 of file component/gmac.h.
| #define GMAC_IER_RXUBR (0x1u << 2) |
(GMAC_IER) RX Used Bit Read
Definition at line 366 of file component/gmac.h.
| #define GMAC_IER_SFR (0x1u << 19) |
(GMAC_IER) PTP Sync Frame Received
Definition at line 379 of file component/gmac.h.
| #define GMAC_IER_SFT (0x1u << 21) |
(GMAC_IER) PTP Sync Frame Transmitted
Definition at line 381 of file component/gmac.h.
| #define GMAC_IER_SRI (0x1u << 26) |
(GMAC_IER) TSU Seconds Register Increment
Definition at line 386 of file component/gmac.h.
| #define GMAC_IER_TCOMP (0x1u << 7) |
(GMAC_IER) Transmit Complete
Definition at line 371 of file component/gmac.h.
| #define GMAC_IER_TFC (0x1u << 6) |
(GMAC_IER) Transmit Frame Corruption Due to AHB Error
Definition at line 370 of file component/gmac.h.
| #define GMAC_IER_TUR (0x1u << 4) |
(GMAC_IER) Transmit Underrun
Definition at line 368 of file component/gmac.h.
| #define GMAC_IER_TXUBR (0x1u << 3) |
(GMAC_IER) TX Used Bit Read
Definition at line 367 of file component/gmac.h.
| #define GMAC_IER_WOL (0x1u << 28) |
(GMAC_IER) Wake On LAN
Definition at line 387 of file component/gmac.h.
| #define GMAC_IERPQ_HRESP (0x1u << 11) |
(GMAC_IERPQ[5]) HRESP Not OK
Definition at line 850 of file component/gmac.h.
| #define GMAC_IERPQ_RCOMP (0x1u << 1) |
(GMAC_IERPQ[5]) Receive Complete
Definition at line 844 of file component/gmac.h.
| #define GMAC_IERPQ_RLEX (0x1u << 5) |
(GMAC_IERPQ[5]) Retry Limit Exceeded or Late Collision
Definition at line 846 of file component/gmac.h.
| #define GMAC_IERPQ_ROVR (0x1u << 10) |
(GMAC_IERPQ[5]) Receive Overrun
Definition at line 849 of file component/gmac.h.
| #define GMAC_IERPQ_RXUBR (0x1u << 2) |
(GMAC_IERPQ[5]) RX Used Bit Read
Definition at line 845 of file component/gmac.h.
| #define GMAC_IERPQ_TCOMP (0x1u << 7) |
(GMAC_IERPQ[5]) Transmit Complete
Definition at line 848 of file component/gmac.h.
| #define GMAC_IERPQ_TFC (0x1u << 6) |
(GMAC_IERPQ[5]) Transmit Frame Corruption Due to AHB Error
Definition at line 847 of file component/gmac.h.
| #define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) |
(GMAC_IHCE) IP Header Checksum Errors
Definition at line 702 of file component/gmac.h.
| #define GMAC_IHCE_HCKER_Pos 0 |
Definition at line 701 of file component/gmac.h.
| #define GMAC_IMR_DRQFR (0x1u << 18) |
(GMAC_IMR) PTP Delay Request Frame Received
Definition at line 428 of file component/gmac.h.
| #define GMAC_IMR_DRQFT (0x1u << 20) |
(GMAC_IMR) PTP Delay Request Frame Transmitted
Definition at line 430 of file component/gmac.h.
| #define GMAC_IMR_EXINT (0x1u << 15) |
(GMAC_IMR) External Interrupt
Definition at line 427 of file component/gmac.h.
| #define GMAC_IMR_HRESP (0x1u << 11) |
(GMAC_IMR) HRESP Not OK
Definition at line 423 of file component/gmac.h.
| #define GMAC_IMR_MFS (0x1u << 0) |
(GMAC_IMR) Management Frame Sent
Definition at line 414 of file component/gmac.h.
| #define GMAC_IMR_PDRQFR (0x1u << 22) |
(GMAC_IMR) PDelay Request Frame Received
Definition at line 432 of file component/gmac.h.
| #define GMAC_IMR_PDRQFT (0x1u << 24) |
(GMAC_IMR) PDelay Request Frame Transmitted
Definition at line 434 of file component/gmac.h.
| #define GMAC_IMR_PDRSFR (0x1u << 23) |
(GMAC_IMR) PDelay Response Frame Received
Definition at line 433 of file component/gmac.h.
| #define GMAC_IMR_PDRSFT (0x1u << 25) |
(GMAC_IMR) PDelay Response Frame Transmitted
Definition at line 435 of file component/gmac.h.
| #define GMAC_IMR_PFNZ (0x1u << 12) |
(GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received
Definition at line 424 of file component/gmac.h.
| #define GMAC_IMR_PFTR (0x1u << 14) |
(GMAC_IMR) Pause Frame Transmitted
Definition at line 426 of file component/gmac.h.
| #define GMAC_IMR_PTZ (0x1u << 13) |
(GMAC_IMR) Pause Time Zero
Definition at line 425 of file component/gmac.h.
| #define GMAC_IMR_RCOMP (0x1u << 1) |
(GMAC_IMR) Receive Complete
Definition at line 415 of file component/gmac.h.
| #define GMAC_IMR_RLEX (0x1u << 5) |
(GMAC_IMR) Retry Limit Exceeded
Definition at line 419 of file component/gmac.h.
| #define GMAC_IMR_ROVR (0x1u << 10) |
(GMAC_IMR) Receive Overrun
Definition at line 422 of file component/gmac.h.
| #define GMAC_IMR_RXUBR (0x1u << 2) |
(GMAC_IMR) RX Used Bit Read
Definition at line 416 of file component/gmac.h.
| #define GMAC_IMR_SFR (0x1u << 19) |
(GMAC_IMR) PTP Sync Frame Received
Definition at line 429 of file component/gmac.h.
| #define GMAC_IMR_SFT (0x1u << 21) |
(GMAC_IMR) PTP Sync Frame Transmitted
Definition at line 431 of file component/gmac.h.
| #define GMAC_IMR_SRI (0x1u << 26) |
(GMAC_IMR) TSU Seconds Register Increment
Definition at line 436 of file component/gmac.h.
| #define GMAC_IMR_TCOMP (0x1u << 7) |
(GMAC_IMR) Transmit Complete
Definition at line 421 of file component/gmac.h.
| #define GMAC_IMR_TFC (0x1u << 6) |
(GMAC_IMR) Transmit Frame Corruption Due to AHB Error
Definition at line 420 of file component/gmac.h.
| #define GMAC_IMR_TUR (0x1u << 4) |
(GMAC_IMR) Transmit Underrun
Definition at line 418 of file component/gmac.h.
| #define GMAC_IMR_TXUBR (0x1u << 3) |
(GMAC_IMR) TX Used Bit Read
Definition at line 417 of file component/gmac.h.
| #define GMAC_IMR_WOL (0x1u << 28) |
(GMAC_IMR) Wake On LAN
Definition at line 437 of file component/gmac.h.
| #define GMAC_IMRPQ_AHB (0x1u << 6) |
(GMAC_IMRPQ[5]) AHB Error
Definition at line 863 of file component/gmac.h.
| #define GMAC_IMRPQ_HRESP (0x1u << 11) |
(GMAC_IMRPQ[5]) HRESP Not OK
Definition at line 866 of file component/gmac.h.
| #define GMAC_IMRPQ_RCOMP (0x1u << 1) |
(GMAC_IMRPQ[5]) Receive Complete
Definition at line 860 of file component/gmac.h.
| #define GMAC_IMRPQ_RLEX (0x1u << 5) |
(GMAC_IMRPQ[5]) Retry Limit Exceeded or Late Collision
Definition at line 862 of file component/gmac.h.
| #define GMAC_IMRPQ_ROVR (0x1u << 10) |
(GMAC_IMRPQ[5]) Receive Overrun
Definition at line 865 of file component/gmac.h.
| #define GMAC_IMRPQ_RXUBR (0x1u << 2) |
(GMAC_IMRPQ[5]) RX Used Bit Read
Definition at line 861 of file component/gmac.h.
| #define GMAC_IMRPQ_TCOMP (0x1u << 7) |
(GMAC_IMRPQ[5]) Transmit Complete
Definition at line 864 of file component/gmac.h.
| #define GMAC_IPGS_FL | ( | value | ) | ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) |
Definition at line 524 of file component/gmac.h.
| #define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) |
(GMAC_IPGS) Frame Length
Definition at line 523 of file component/gmac.h.
| #define GMAC_IPGS_FL_Pos 0 |
Definition at line 522 of file component/gmac.h.
| #define GMAC_ISR_DRQFR (0x1u << 18) |
(GMAC_ISR) PTP Delay Request Frame Received
Definition at line 353 of file component/gmac.h.
| #define GMAC_ISR_DRQFT (0x1u << 20) |
(GMAC_ISR) PTP Delay Request Frame Transmitted
Definition at line 355 of file component/gmac.h.
| #define GMAC_ISR_HRESP (0x1u << 11) |
(GMAC_ISR) HRESP Not OK
Definition at line 349 of file component/gmac.h.
| #define GMAC_ISR_MFS (0x1u << 0) |
(GMAC_ISR) Management Frame Sent
Definition at line 340 of file component/gmac.h.
| #define GMAC_ISR_PDRQFR (0x1u << 22) |
(GMAC_ISR) PDelay Request Frame Received
Definition at line 357 of file component/gmac.h.
| #define GMAC_ISR_PDRQFT (0x1u << 24) |
(GMAC_ISR) PDelay Request Frame Transmitted
Definition at line 359 of file component/gmac.h.
| #define GMAC_ISR_PDRSFR (0x1u << 23) |
(GMAC_ISR) PDelay Response Frame Received
Definition at line 358 of file component/gmac.h.
| #define GMAC_ISR_PDRSFT (0x1u << 25) |
(GMAC_ISR) PDelay Response Frame Transmitted
Definition at line 360 of file component/gmac.h.
| #define GMAC_ISR_PFNZ (0x1u << 12) |
(GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received
Definition at line 350 of file component/gmac.h.
| #define GMAC_ISR_PFTR (0x1u << 14) |
(GMAC_ISR) Pause Frame Transmitted
Definition at line 352 of file component/gmac.h.
| #define GMAC_ISR_PTZ (0x1u << 13) |
(GMAC_ISR) Pause Time Zero
Definition at line 351 of file component/gmac.h.
| #define GMAC_ISR_RCOMP (0x1u << 1) |
(GMAC_ISR) Receive Complete
Definition at line 341 of file component/gmac.h.
| #define GMAC_ISR_RLEX (0x1u << 5) |
(GMAC_ISR) Retry Limit Exceeded
Definition at line 345 of file component/gmac.h.
| #define GMAC_ISR_ROVR (0x1u << 10) |
(GMAC_ISR) Receive Overrun
Definition at line 348 of file component/gmac.h.
| #define GMAC_ISR_RXUBR (0x1u << 2) |
(GMAC_ISR) RX Used Bit Read
Definition at line 342 of file component/gmac.h.
| #define GMAC_ISR_SFR (0x1u << 19) |
(GMAC_ISR) PTP Sync Frame Received
Definition at line 354 of file component/gmac.h.
| #define GMAC_ISR_SFT (0x1u << 21) |
(GMAC_ISR) PTP Sync Frame Transmitted
Definition at line 356 of file component/gmac.h.
| #define GMAC_ISR_SRI (0x1u << 26) |
(GMAC_ISR) TSU Seconds Register Increment
Definition at line 361 of file component/gmac.h.
| #define GMAC_ISR_TCOMP (0x1u << 7) |
(GMAC_ISR) Transmit Complete
Definition at line 347 of file component/gmac.h.
| #define GMAC_ISR_TFC (0x1u << 6) |
(GMAC_ISR) Transmit Frame Corruption Due to AHB Error
Definition at line 346 of file component/gmac.h.
| #define GMAC_ISR_TUR (0x1u << 4) |
(GMAC_ISR) Transmit Underrun
Definition at line 344 of file component/gmac.h.
| #define GMAC_ISR_TXUBR (0x1u << 3) |
(GMAC_ISR) TX Used Bit Read
Definition at line 343 of file component/gmac.h.
| #define GMAC_ISR_WOL (0x1u << 28) |
(GMAC_ISR) Wake On LAN
Definition at line 362 of file component/gmac.h.
| #define GMAC_ISRPQ_HRESP (0x1u << 11) |
(GMAC_ISRPQ[5]) HRESP Not OK
Definition at line 783 of file component/gmac.h.
| #define GMAC_ISRPQ_RCOMP (0x1u << 1) |
(GMAC_ISRPQ[5]) Receive Complete
Definition at line 777 of file component/gmac.h.
| #define GMAC_ISRPQ_RLEX (0x1u << 5) |
(GMAC_ISRPQ[5]) Retry Limit Exceeded or Late Collision
Definition at line 779 of file component/gmac.h.
| #define GMAC_ISRPQ_ROVR (0x1u << 10) |
(GMAC_ISRPQ[5]) Receive Overrun
Definition at line 782 of file component/gmac.h.
| #define GMAC_ISRPQ_RXUBR (0x1u << 2) |
(GMAC_ISRPQ[5]) RX Used Bit Read
Definition at line 778 of file component/gmac.h.
| #define GMAC_ISRPQ_TCOMP (0x1u << 7) |
(GMAC_ISRPQ[5]) Transmit Complete
Definition at line 781 of file component/gmac.h.
| #define GMAC_ISRPQ_TFC (0x1u << 6) |
(GMAC_ISRPQ[5]) Transmit Frame Corruption Due to AHB Error
Definition at line 780 of file component/gmac.h.
| #define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) |
(GMAC_JR) Jabbers Received
Definition at line 681 of file component/gmac.h.
| #define GMAC_JR_JRX_Pos 0 |
Definition at line 680 of file component/gmac.h.
| #define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) |
(GMAC_LC) Late Collisions
Definition at line 627 of file component/gmac.h.
| #define GMAC_LC_LCOL_Pos 0 |
Definition at line 626 of file component/gmac.h.
| #define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) |
(GMAC_LFFE) Length Field Frame Errors
Definition at line 687 of file component/gmac.h.
| #define GMAC_LFFE_LFER_Pos 0 |
Definition at line 686 of file component/gmac.h.
| #define GMAC_MAN_CLTTO (0x1u << 30) |
(GMAC_MAN) Clause 22 Operation
Definition at line 454 of file component/gmac.h.
| #define GMAC_MAN_DATA | ( | value | ) | ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) |
Definition at line 441 of file component/gmac.h.
| #define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) |
(GMAC_MAN) PHY Data
Definition at line 440 of file component/gmac.h.
| #define GMAC_MAN_DATA_Pos 0 |
Definition at line 439 of file component/gmac.h.
| #define GMAC_MAN_OP | ( | value | ) | ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) |
Definition at line 453 of file component/gmac.h.
| #define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) |
(GMAC_MAN) Operation
Definition at line 452 of file component/gmac.h.
| #define GMAC_MAN_OP_Pos 28 |
Definition at line 451 of file component/gmac.h.
| #define GMAC_MAN_PHYA | ( | value | ) | ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) |
Definition at line 450 of file component/gmac.h.
| #define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) |
(GMAC_MAN) PHY Address
Definition at line 449 of file component/gmac.h.
| #define GMAC_MAN_PHYA_Pos 23 |
Definition at line 448 of file component/gmac.h.
| #define GMAC_MAN_REGA | ( | value | ) | ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) |
Definition at line 447 of file component/gmac.h.
| #define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) |
(GMAC_MAN) Register Address
Definition at line 446 of file component/gmac.h.
| #define GMAC_MAN_REGA_Pos 18 |
Definition at line 445 of file component/gmac.h.
| #define GMAC_MAN_WTN | ( | value | ) | ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) |
Definition at line 444 of file component/gmac.h.
| #define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) |
(GMAC_MAN) Write Ten
Definition at line 443 of file component/gmac.h.
| #define GMAC_MAN_WTN_Pos 16 |
Definition at line 442 of file component/gmac.h.
| #define GMAC_MAN_WZO (0x1u << 31) |
(GMAC_MAN) Write ZERO
Definition at line 455 of file component/gmac.h.
| #define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) |
(GMAC_MCF) Multiple Collision
Definition at line 621 of file component/gmac.h.
| #define GMAC_MCF_MCOL_Pos 0 |
Definition at line 620 of file component/gmac.h.
| #define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) |
(GMAC_MFR) Multicast Frames Received without Error
Definition at line 648 of file component/gmac.h.
| #define GMAC_MFR_MFRX_Pos 0 |
Definition at line 647 of file component/gmac.h.
| #define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) |
(GMAC_MFT) Multicast Frames Transmitted without Error
Definition at line 588 of file component/gmac.h.
| #define GMAC_MFT_MFTX_Pos 0 |
Definition at line 587 of file component/gmac.h.
| #define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) |
(GMAC_MID) Module Identification Number
Definition at line 573 of file component/gmac.h.
| #define GMAC_MID_MID_Pos 16 |
Definition at line 572 of file component/gmac.h.
| #define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) |
(GMAC_MID) Module Revision
Definition at line 571 of file component/gmac.h.
| #define GMAC_MID_MREV_Pos 0 |
Definition at line 570 of file component/gmac.h.
| #define GMAC_NCFGR_CAF (0x1u << 4) |
(GMAC_NCFGR) Copy All Frames
Definition at line 259 of file component/gmac.h.
| #define GMAC_NCFGR_CLK | ( | value | ) | ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) |
Definition at line 273 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) |
(GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz)
Definition at line 275 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) |
(GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz)
Definition at line 276 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) |
(GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz)
Definition at line 277 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) |
(GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz)
Definition at line 278 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) |
(GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz)
Definition at line 274 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) |
(GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz)
Definition at line 279 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) |
(GMAC_NCFGR) MDC CLock Division
Definition at line 272 of file component/gmac.h.
| #define GMAC_NCFGR_CLK_Pos 18 |
Definition at line 271 of file component/gmac.h.
| #define GMAC_NCFGR_DBW | ( | value | ) | ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) |
Definition at line 282 of file component/gmac.h.
| #define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) |
(GMAC_NCFGR) Data Bus Width
Definition at line 281 of file component/gmac.h.
| #define GMAC_NCFGR_DBW_Pos 21 |
Definition at line 280 of file component/gmac.h.
| #define GMAC_NCFGR_DCPF (0x1u << 23) |
(GMAC_NCFGR) Disable Copy of Pause Frames
Definition at line 283 of file component/gmac.h.
| #define GMAC_NCFGR_DNVLAN (0x1u << 2) |
(GMAC_NCFGR) Discard Non-VLAN FRAMES
Definition at line 257 of file component/gmac.h.
| #define GMAC_NCFGR_EFRHD (0x1u << 25) |
(GMAC_NCFGR) Enable Frames Received in Half Duplex
Definition at line 285 of file component/gmac.h.
| #define GMAC_NCFGR_FD (0x1u << 1) |
(GMAC_NCFGR) Full Duplex
Definition at line 256 of file component/gmac.h.
| #define GMAC_NCFGR_IPGSEN (0x1u << 28) |
(GMAC_NCFGR) IP Stretch Enable
Definition at line 287 of file component/gmac.h.
| #define GMAC_NCFGR_IRXER (0x1u << 30) |
(GMAC_NCFGR) Ignore IPG GRXER
Definition at line 289 of file component/gmac.h.
| #define GMAC_NCFGR_IRXFCS (0x1u << 26) |
(GMAC_NCFGR) Ignore RX FCS
Definition at line 286 of file component/gmac.h.
| #define GMAC_NCFGR_JFRAME (0x1u << 3) |
(GMAC_NCFGR) Jumbo Frame Size
Definition at line 258 of file component/gmac.h.
| #define GMAC_NCFGR_LFERD (0x1u << 16) |
(GMAC_NCFGR) Length Field Error Frame Discard
Definition at line 269 of file component/gmac.h.
| #define GMAC_NCFGR_MAXFS (0x1u << 8) |
(GMAC_NCFGR) 1536 Maximum Frame Size
Definition at line 263 of file component/gmac.h.
| #define GMAC_NCFGR_MTIHEN (0x1u << 6) |
(GMAC_NCFGR) Multicast Hash Enable
Definition at line 261 of file component/gmac.h.
| #define GMAC_NCFGR_NBC (0x1u << 5) |
(GMAC_NCFGR) No Broadcast
Definition at line 260 of file component/gmac.h.
| #define GMAC_NCFGR_PEN (0x1u << 13) |
(GMAC_NCFGR) Pause Enable
Definition at line 265 of file component/gmac.h.
| #define GMAC_NCFGR_RFCS (0x1u << 17) |
(GMAC_NCFGR) Remove FCS
Definition at line 270 of file component/gmac.h.
| #define GMAC_NCFGR_RTY (0x1u << 12) |
(GMAC_NCFGR) Retry Test
Definition at line 264 of file component/gmac.h.
| #define GMAC_NCFGR_RXBP (0x1u << 29) |
(GMAC_NCFGR) Receive Bad Preamble
Definition at line 288 of file component/gmac.h.
| #define GMAC_NCFGR_RXBUFO | ( | value | ) | ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) |
Definition at line 268 of file component/gmac.h.
| #define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) |
(GMAC_NCFGR) Receive Buffer Offset
Definition at line 267 of file component/gmac.h.
| #define GMAC_NCFGR_RXBUFO_Pos 14 |
Definition at line 266 of file component/gmac.h.
| #define GMAC_NCFGR_RXCOEN (0x1u << 24) |
(GMAC_NCFGR) Receive Checksum Offload Enable
Definition at line 284 of file component/gmac.h.
| #define GMAC_NCFGR_SPD (0x1u << 0) |
(GMAC_NCFGR) Speed
Definition at line 255 of file component/gmac.h.
| #define GMAC_NCFGR_UNIHEN (0x1u << 7) |
(GMAC_NCFGR) Unicast Hash Enable
Definition at line 262 of file component/gmac.h.
| #define GMAC_NCR_BP (0x1u << 8) |
(GMAC_NCR) Back pressure
Definition at line 245 of file component/gmac.h.
| #define GMAC_NCR_CLRSTAT (0x1u << 5) |
(GMAC_NCR) Clear Statistics Registers
Definition at line 242 of file component/gmac.h.
| #define GMAC_NCR_ENPBPR (0x1u << 16) |
(GMAC_NCR) Enable PFC Priority-based Pause Reception
Definition at line 251 of file component/gmac.h.
| #define GMAC_NCR_FNP (0x1u << 18) |
(GMAC_NCR) Flush Next Packet
Definition at line 253 of file component/gmac.h.
| #define GMAC_NCR_INCSTAT (0x1u << 6) |
(GMAC_NCR) Increment Statistics Registers
Definition at line 243 of file component/gmac.h.
| #define GMAC_NCR_LBL (0x1u << 1) |
(GMAC_NCR) Loop Back Local
Definition at line 238 of file component/gmac.h.
| #define GMAC_NCR_MPE (0x1u << 4) |
(GMAC_NCR) Management Port Enable
Definition at line 241 of file component/gmac.h.
| #define GMAC_NCR_RXEN (0x1u << 2) |
(GMAC_NCR) Receive Enable
Definition at line 239 of file component/gmac.h.
| #define GMAC_NCR_SRTSM (0x1u << 15) |
(GMAC_NCR) Store Receive Time Stamp to Memory
Definition at line 250 of file component/gmac.h.
| #define GMAC_NCR_THALT (0x1u << 10) |
(GMAC_NCR) Transmit Halt
Definition at line 247 of file component/gmac.h.
| #define GMAC_NCR_TSTART (0x1u << 9) |
(GMAC_NCR) Start Transmission
Definition at line 246 of file component/gmac.h.
| #define GMAC_NCR_TXEN (0x1u << 3) |
(GMAC_NCR) Transmit Enable
Definition at line 240 of file component/gmac.h.
| #define GMAC_NCR_TXPBPF (0x1u << 17) |
(GMAC_NCR) Transmit PFC Priority-based Pause Frame
Definition at line 252 of file component/gmac.h.
| #define GMAC_NCR_TXPF (0x1u << 11) |
(GMAC_NCR) Transmit Pause Frame
Definition at line 248 of file component/gmac.h.
| #define GMAC_NCR_TXZQPF (0x1u << 12) |
(GMAC_NCR) Transmit Zero Quantum Pause Frame
Definition at line 249 of file component/gmac.h.
| #define GMAC_NCR_WESTAT (0x1u << 7) |
(GMAC_NCR) Write Enable for Statistics Registers
Definition at line 244 of file component/gmac.h.
| #define GMAC_NSC_NANOSEC | ( | value | ) | ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) |
Definition at line 548 of file component/gmac.h.
| #define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) |
(GMAC_NSC) 1588 Timer Nanosecond Comparison Value
Definition at line 547 of file component/gmac.h.
| #define GMAC_NSC_NANOSEC_Pos 0 |
Definition at line 546 of file component/gmac.h.
| #define GMAC_NSR_IDLE (0x1u << 2) |
(GMAC_NSR) PHY Management Logic Idle
Definition at line 292 of file component/gmac.h.
| #define GMAC_NSR_MDIO (0x1u << 1) |
(GMAC_NSR) MDIO Input Status
Definition at line 291 of file component/gmac.h.
| #define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) |
(GMAC_OFR) Oversized Frames Received
Definition at line 678 of file component/gmac.h.
| #define GMAC_OFR_OFRX_Pos 0 |
Definition at line 677 of file component/gmac.h.
| #define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) |
(GMAC_ORHI) Received Octets
Definition at line 639 of file component/gmac.h.
| #define GMAC_ORHI_RXO_Pos 0 |
Definition at line 638 of file component/gmac.h.
| #define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) |
(GMAC_ORLO) Received Octets
Definition at line 636 of file component/gmac.h.
| #define GMAC_ORLO_RXO_Pos 0 |
Definition at line 635 of file component/gmac.h.
| #define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) |
(GMAC_OTHI) Transmitted Octets
Definition at line 579 of file component/gmac.h.
| #define GMAC_OTHI_TXO_Pos 0 |
Definition at line 578 of file component/gmac.h.
| #define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) |
(GMAC_OTLO) Transmitted Octets
Definition at line 576 of file component/gmac.h.
| #define GMAC_OTLO_TXO_Pos 0 |
Definition at line 575 of file component/gmac.h.
| #define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) |
(GMAC_PEFRN) Register Update
Definition at line 763 of file component/gmac.h.
| #define GMAC_PEFRN_RUD_Pos 0 |
Definition at line 762 of file component/gmac.h.
| #define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) |
(GMAC_PEFRSH) Register Update
Definition at line 568 of file component/gmac.h.
| #define GMAC_PEFRSH_RUD_Pos 0 |
Definition at line 567 of file component/gmac.h.
| #define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) |
(GMAC_PEFRSL) Register Update
Definition at line 760 of file component/gmac.h.
| #define GMAC_PEFRSL_RUD_Pos 0 |
Definition at line 759 of file component/gmac.h.
| #define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) |
(GMAC_PEFTN) Register Update
Definition at line 757 of file component/gmac.h.
| #define GMAC_PEFTN_RUD_Pos 0 |
Definition at line 756 of file component/gmac.h.
| #define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) |
(GMAC_PEFTSH) Register Update
Definition at line 565 of file component/gmac.h.
| #define GMAC_PEFTSH_RUD_Pos 0 |
Definition at line 564 of file component/gmac.h.
| #define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) |
(GMAC_PEFTSL) Register Update
Definition at line 754 of file component/gmac.h.
| #define GMAC_PEFTSL_RUD_Pos 0 |
Definition at line 753 of file component/gmac.h.
| #define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) |
(GMAC_PFR) Pause Frames Received Register
Definition at line 651 of file component/gmac.h.
| #define GMAC_PFR_PFRX_Pos 0 |
Definition at line 650 of file component/gmac.h.
| #define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) |
(GMAC_PFT) Pause Frames Transmitted Register
Definition at line 591 of file component/gmac.h.
| #define GMAC_PFT_PFTX_Pos 0 |
Definition at line 590 of file component/gmac.h.
| #define GMAC_RBQB_ADDR | ( | value | ) | ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) |
Definition at line 329 of file component/gmac.h.
| #define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) |
(GMAC_RBQB) Receive Buffer Queue Base Address
Definition at line 328 of file component/gmac.h.
| #define GMAC_RBQB_ADDR_Pos 2 |
Definition at line 327 of file component/gmac.h.
| #define GMAC_RBQBAPQ_RXBQBA | ( | value | ) | ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) |
Definition at line 791 of file component/gmac.h.
| #define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) |
(GMAC_RBQBAPQ[5]) Receive Buffer Queue Base Address
Definition at line 790 of file component/gmac.h.
| #define GMAC_RBQBAPQ_RXBQBA_Pos 2 |
Definition at line 789 of file component/gmac.h.
| #define GMAC_RBSRPQ_RBS | ( | value | ) | ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) |
Definition at line 795 of file component/gmac.h.
| #define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) |
(GMAC_RBSRPQ[5]) Receive Buffer Size
Definition at line 794 of file component/gmac.h.
| #define GMAC_RBSRPQ_RBS_Pos 0 |
Definition at line 793 of file component/gmac.h.
| #define GMAC_RJFML_FML | ( | value | ) | ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) |
Definition at line 476 of file component/gmac.h.
| #define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) |
(GMAC_RJFML) Frame Max Length
Definition at line 475 of file component/gmac.h.
| #define GMAC_RJFML_FML_Pos 0 |
Definition at line 474 of file component/gmac.h.
| #define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) |
(GMAC_ROE) Receive Overruns
Definition at line 699 of file component/gmac.h.
| #define GMAC_ROE_RXOVR_Pos 0 |
Definition at line 698 of file component/gmac.h.
| #define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) |
(GMAC_RPQ) Received Pause Quantum
Definition at line 458 of file component/gmac.h.
| #define GMAC_RPQ_RPQ_Pos 0 |
Definition at line 457 of file component/gmac.h.
| #define GMAC_RPSF_ENRXP (0x1u << 31) |
(GMAC_RPSF) Enable RX Partial Store and Forward Operation
Definition at line 472 of file component/gmac.h.
| #define GMAC_RPSF_RPB1ADR | ( | value | ) | ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) |
Definition at line 471 of file component/gmac.h.
| #define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) |
(GMAC_RPSF) Receive Partial Store and Forward Address
Definition at line 470 of file component/gmac.h.
| #define GMAC_RPSF_RPB1ADR_Pos 0 |
Definition at line 469 of file component/gmac.h.
| #define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) |
(GMAC_RRE) Receive Resource Errors
Definition at line 696 of file component/gmac.h.
| #define GMAC_RRE_RXRER_Pos 0 |
Definition at line 695 of file component/gmac.h.
| #define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) |
(GMAC_RSE) Receive Symbol Errors
Definition at line 690 of file component/gmac.h.
| #define GMAC_RSE_RXSE_Pos 0 |
Definition at line 689 of file component/gmac.h.
| #define GMAC_RSR_BNA (0x1u << 0) |
(GMAC_RSR) Buffer Not Available
Definition at line 335 of file component/gmac.h.
| #define GMAC_RSR_HNO (0x1u << 3) |
(GMAC_RSR) HRESP Not OK
Definition at line 338 of file component/gmac.h.
| #define GMAC_RSR_REC (0x1u << 1) |
(GMAC_RSR) Frame Received
Definition at line 336 of file component/gmac.h.
| #define GMAC_RSR_RXOVR (0x1u << 2) |
(GMAC_RSR) Receive Overrun
Definition at line 337 of file component/gmac.h.
| #define GMAC_RXLPI_COUNT_Msk (0xffffu << GMAC_RXLPI_COUNT_Pos) |
(GMAC_RXLPI) Count of RX LPI transitions (cleared on read)
Definition at line 766 of file component/gmac.h.
| #define GMAC_RXLPI_COUNT_Pos 0 |
Definition at line 765 of file component/gmac.h.
| #define GMAC_RXLPITIME_LPITIME_Msk (0xffffffu << GMAC_RXLPITIME_LPITIME_Pos) |
(GMAC_RXLPITIME) Time in LPI (cleared on read)
Definition at line 769 of file component/gmac.h.
| #define GMAC_RXLPITIME_LPITIME_Pos 0 |
Definition at line 768 of file component/gmac.h.
| #define GMAC_SAB_ADDR | ( | value | ) | ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) |
Definition at line 488 of file component/gmac.h.
| #define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) |
(GMAC_SAB) Specific Address 1
Definition at line 487 of file component/gmac.h.
| #define GMAC_SAB_ADDR_Pos 0 |
Definition at line 486 of file component/gmac.h.
| #define GMAC_SAMB1_ADDR | ( | value | ) | ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) |
Definition at line 540 of file component/gmac.h.
| #define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) |
(GMAC_SAMB1) Specific Address 1 Mask
Definition at line 539 of file component/gmac.h.
| #define GMAC_SAMB1_ADDR_Pos 0 |
Definition at line 538 of file component/gmac.h.
| #define GMAC_SAMT1_ADDR | ( | value | ) | ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) |
Definition at line 544 of file component/gmac.h.
| #define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) |
(GMAC_SAMT1) Specific Address 1 Mask
Definition at line 543 of file component/gmac.h.
| #define GMAC_SAMT1_ADDR_Pos 0 |
Definition at line 542 of file component/gmac.h.
| #define GMAC_SAT_ADDR | ( | value | ) | ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) |
Definition at line 492 of file component/gmac.h.
| #define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) |
(GMAC_SAT) Specific Address 1
Definition at line 491 of file component/gmac.h.
| #define GMAC_SAT_ADDR_Pos 0 |
Definition at line 490 of file component/gmac.h.
| #define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) |
(GMAC_SCF) Single Collision
Definition at line 618 of file component/gmac.h.
| #define GMAC_SCF_SCOL_Pos 0 |
Definition at line 617 of file component/gmac.h.
| #define GMAC_SCH_SEC | ( | value | ) | ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) |
Definition at line 556 of file component/gmac.h.
| #define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) |
(GMAC_SCH) 1588 Timer Second Comparison Value
Definition at line 555 of file component/gmac.h.
| #define GMAC_SCH_SEC_Pos 0 |
Definition at line 554 of file component/gmac.h.
| #define GMAC_SCL_SEC | ( | value | ) | ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) |
Definition at line 552 of file component/gmac.h.
| #define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) |
(GMAC_SCL) 1588 Timer Second Comparison Value
Definition at line 551 of file component/gmac.h.
| #define GMAC_SCL_SEC_Pos 0 |
Definition at line 550 of file component/gmac.h.
| #define GMAC_ST1RPQ_DSTCE (0x1u << 28) |
(GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable
Definition at line 817 of file component/gmac.h.
| #define GMAC_ST1RPQ_DSTCM | ( | value | ) | ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) |
Definition at line 813 of file component/gmac.h.
| #define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) |
(GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match
Definition at line 812 of file component/gmac.h.
| #define GMAC_ST1RPQ_DSTCM_Pos 4 |
Definition at line 811 of file component/gmac.h.
| #define GMAC_ST1RPQ_QNB | ( | value | ) | ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) |
Definition at line 810 of file component/gmac.h.
| #define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) |
(GMAC_ST1RPQ[4]) Queue Number (0-5)
Definition at line 809 of file component/gmac.h.
| #define GMAC_ST1RPQ_QNB_Pos 0 |
Definition at line 808 of file component/gmac.h.
| #define GMAC_ST1RPQ_UDPE (0x1u << 29) |
(GMAC_ST1RPQ[4]) UDP Port Match Enable
Definition at line 818 of file component/gmac.h.
| #define GMAC_ST1RPQ_UDPM | ( | value | ) | ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) |
Definition at line 816 of file component/gmac.h.
| #define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) |
(GMAC_ST1RPQ[4]) UDP Port Match
Definition at line 815 of file component/gmac.h.
| #define GMAC_ST1RPQ_UDPM_Pos 12 |
Definition at line 814 of file component/gmac.h.
| #define GMAC_ST2CW00_COMPVAL | ( | value | ) | ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos))) |
Definition at line 877 of file component/gmac.h.
| #define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) |
(GMAC_ST2CW00) Compare Value
Definition at line 876 of file component/gmac.h.
| #define GMAC_ST2CW00_COMPVAL_Pos 16 |
Definition at line 875 of file component/gmac.h.
| #define GMAC_ST2CW00_MASKVAL | ( | value | ) | ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos))) |
Definition at line 874 of file component/gmac.h.
| #define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) |
(GMAC_ST2CW00) Mask Value
Definition at line 873 of file component/gmac.h.
| #define GMAC_ST2CW00_MASKVAL_Pos 0 |
Definition at line 872 of file component/gmac.h.
| #define GMAC_ST2CW010_COMPVAL | ( | value | ) | ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos))) |
Definition at line 1057 of file component/gmac.h.
| #define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) |
(GMAC_ST2CW010) Compare Value
Definition at line 1056 of file component/gmac.h.
| #define GMAC_ST2CW010_COMPVAL_Pos 16 |
Definition at line 1055 of file component/gmac.h.
| #define GMAC_ST2CW010_MASKVAL | ( | value | ) | ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos))) |
Definition at line 1054 of file component/gmac.h.
| #define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) |
(GMAC_ST2CW010) Mask Value
Definition at line 1053 of file component/gmac.h.
| #define GMAC_ST2CW010_MASKVAL_Pos 0 |
Definition at line 1052 of file component/gmac.h.
| #define GMAC_ST2CW011_COMPVAL | ( | value | ) | ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos))) |
Definition at line 1075 of file component/gmac.h.
| #define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) |
(GMAC_ST2CW011) Compare Value
Definition at line 1074 of file component/gmac.h.
| #define GMAC_ST2CW011_COMPVAL_Pos 16 |
Definition at line 1073 of file component/gmac.h.
| #define GMAC_ST2CW011_MASKVAL | ( | value | ) | ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos))) |
Definition at line 1072 of file component/gmac.h.
| #define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) |
(GMAC_ST2CW011) Mask Value
Definition at line 1071 of file component/gmac.h.
| #define GMAC_ST2CW011_MASKVAL_Pos 0 |
Definition at line 1070 of file component/gmac.h.
| #define GMAC_ST2CW012_COMPVAL | ( | value | ) | ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos))) |
Definition at line 1093 of file component/gmac.h.
| #define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) |
(GMAC_ST2CW012) Compare Value
Definition at line 1092 of file component/gmac.h.
| #define GMAC_ST2CW012_COMPVAL_Pos 16 |
Definition at line 1091 of file component/gmac.h.
| #define GMAC_ST2CW012_MASKVAL | ( | value | ) | ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos))) |
Definition at line 1090 of file component/gmac.h.
| #define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) |
(GMAC_ST2CW012) Mask Value
Definition at line 1089 of file component/gmac.h.
| #define GMAC_ST2CW012_MASKVAL_Pos 0 |
Definition at line 1088 of file component/gmac.h.
| #define GMAC_ST2CW013_COMPVAL | ( | value | ) | ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos))) |
Definition at line 1111 of file component/gmac.h.
| #define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) |
(GMAC_ST2CW013) Compare Value
Definition at line 1110 of file component/gmac.h.
| #define GMAC_ST2CW013_COMPVAL_Pos 16 |
Definition at line 1109 of file component/gmac.h.
| #define GMAC_ST2CW013_MASKVAL | ( | value | ) | ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos))) |
Definition at line 1108 of file component/gmac.h.
| #define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) |
(GMAC_ST2CW013) Mask Value
Definition at line 1107 of file component/gmac.h.
| #define GMAC_ST2CW013_MASKVAL_Pos 0 |
Definition at line 1106 of file component/gmac.h.
| #define GMAC_ST2CW014_COMPVAL | ( | value | ) | ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos))) |
Definition at line 1129 of file component/gmac.h.
| #define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) |
(GMAC_ST2CW014) Compare Value
Definition at line 1128 of file component/gmac.h.
| #define GMAC_ST2CW014_COMPVAL_Pos 16 |
Definition at line 1127 of file component/gmac.h.
| #define GMAC_ST2CW014_MASKVAL | ( | value | ) | ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos))) |
Definition at line 1126 of file component/gmac.h.
| #define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) |
(GMAC_ST2CW014) Mask Value
Definition at line 1125 of file component/gmac.h.
| #define GMAC_ST2CW014_MASKVAL_Pos 0 |
Definition at line 1124 of file component/gmac.h.
| #define GMAC_ST2CW015_COMPVAL | ( | value | ) | ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos))) |
Definition at line 1147 of file component/gmac.h.
| #define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) |
(GMAC_ST2CW015) Compare Value
Definition at line 1146 of file component/gmac.h.
| #define GMAC_ST2CW015_COMPVAL_Pos 16 |
Definition at line 1145 of file component/gmac.h.
| #define GMAC_ST2CW015_MASKVAL | ( | value | ) | ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos))) |
Definition at line 1144 of file component/gmac.h.
| #define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) |
(GMAC_ST2CW015) Mask Value
Definition at line 1143 of file component/gmac.h.
| #define GMAC_ST2CW015_MASKVAL_Pos 0 |
Definition at line 1142 of file component/gmac.h.
| #define GMAC_ST2CW016_COMPVAL | ( | value | ) | ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos))) |
Definition at line 1165 of file component/gmac.h.
| #define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) |
(GMAC_ST2CW016) Compare Value
Definition at line 1164 of file component/gmac.h.
| #define GMAC_ST2CW016_COMPVAL_Pos 16 |
Definition at line 1163 of file component/gmac.h.
| #define GMAC_ST2CW016_MASKVAL | ( | value | ) | ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos))) |
Definition at line 1162 of file component/gmac.h.
| #define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) |
(GMAC_ST2CW016) Mask Value
Definition at line 1161 of file component/gmac.h.
| #define GMAC_ST2CW016_MASKVAL_Pos 0 |
Definition at line 1160 of file component/gmac.h.
| #define GMAC_ST2CW017_COMPVAL | ( | value | ) | ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos))) |
Definition at line 1183 of file component/gmac.h.
| #define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) |
(GMAC_ST2CW017) Compare Value
Definition at line 1182 of file component/gmac.h.
| #define GMAC_ST2CW017_COMPVAL_Pos 16 |
Definition at line 1181 of file component/gmac.h.
| #define GMAC_ST2CW017_MASKVAL | ( | value | ) | ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos))) |
Definition at line 1180 of file component/gmac.h.
| #define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) |
(GMAC_ST2CW017) Mask Value
Definition at line 1179 of file component/gmac.h.
| #define GMAC_ST2CW017_MASKVAL_Pos 0 |
Definition at line 1178 of file component/gmac.h.
| #define GMAC_ST2CW018_COMPVAL | ( | value | ) | ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos))) |
Definition at line 1201 of file component/gmac.h.
| #define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) |
(GMAC_ST2CW018) Compare Value
Definition at line 1200 of file component/gmac.h.
| #define GMAC_ST2CW018_COMPVAL_Pos 16 |
Definition at line 1199 of file component/gmac.h.
| #define GMAC_ST2CW018_MASKVAL | ( | value | ) | ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos))) |
Definition at line 1198 of file component/gmac.h.
| #define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) |
(GMAC_ST2CW018) Mask Value
Definition at line 1197 of file component/gmac.h.
| #define GMAC_ST2CW018_MASKVAL_Pos 0 |
Definition at line 1196 of file component/gmac.h.
| #define GMAC_ST2CW019_COMPVAL | ( | value | ) | ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos))) |
Definition at line 1219 of file component/gmac.h.
| #define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) |
(GMAC_ST2CW019) Compare Value
Definition at line 1218 of file component/gmac.h.
| #define GMAC_ST2CW019_COMPVAL_Pos 16 |
Definition at line 1217 of file component/gmac.h.
| #define GMAC_ST2CW019_MASKVAL | ( | value | ) | ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos))) |
Definition at line 1216 of file component/gmac.h.
| #define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) |
(GMAC_ST2CW019) Mask Value
Definition at line 1215 of file component/gmac.h.
| #define GMAC_ST2CW019_MASKVAL_Pos 0 |
Definition at line 1214 of file component/gmac.h.
| #define GMAC_ST2CW01_COMPVAL | ( | value | ) | ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos))) |
Definition at line 895 of file component/gmac.h.
| #define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) |
(GMAC_ST2CW01) Compare Value
Definition at line 894 of file component/gmac.h.
| #define GMAC_ST2CW01_COMPVAL_Pos 16 |
Definition at line 893 of file component/gmac.h.
| #define GMAC_ST2CW01_MASKVAL | ( | value | ) | ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos))) |
Definition at line 892 of file component/gmac.h.
| #define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) |
(GMAC_ST2CW01) Mask Value
Definition at line 891 of file component/gmac.h.
| #define GMAC_ST2CW01_MASKVAL_Pos 0 |
Definition at line 890 of file component/gmac.h.
| #define GMAC_ST2CW020_COMPVAL | ( | value | ) | ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos))) |
Definition at line 1237 of file component/gmac.h.
| #define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) |
(GMAC_ST2CW020) Compare Value
Definition at line 1236 of file component/gmac.h.
| #define GMAC_ST2CW020_COMPVAL_Pos 16 |
Definition at line 1235 of file component/gmac.h.
| #define GMAC_ST2CW020_MASKVAL | ( | value | ) | ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos))) |
Definition at line 1234 of file component/gmac.h.
| #define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) |
(GMAC_ST2CW020) Mask Value
Definition at line 1233 of file component/gmac.h.
| #define GMAC_ST2CW020_MASKVAL_Pos 0 |
Definition at line 1232 of file component/gmac.h.
| #define GMAC_ST2CW021_COMPVAL | ( | value | ) | ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos))) |
Definition at line 1255 of file component/gmac.h.
| #define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) |
(GMAC_ST2CW021) Compare Value
Definition at line 1254 of file component/gmac.h.
| #define GMAC_ST2CW021_COMPVAL_Pos 16 |
Definition at line 1253 of file component/gmac.h.
| #define GMAC_ST2CW021_MASKVAL | ( | value | ) | ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos))) |
Definition at line 1252 of file component/gmac.h.
| #define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) |
(GMAC_ST2CW021) Mask Value
Definition at line 1251 of file component/gmac.h.
| #define GMAC_ST2CW021_MASKVAL_Pos 0 |
Definition at line 1250 of file component/gmac.h.
| #define GMAC_ST2CW022_COMPVAL | ( | value | ) | ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos))) |
Definition at line 1273 of file component/gmac.h.
| #define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) |
(GMAC_ST2CW022) Compare Value
Definition at line 1272 of file component/gmac.h.
| #define GMAC_ST2CW022_COMPVAL_Pos 16 |
Definition at line 1271 of file component/gmac.h.
| #define GMAC_ST2CW022_MASKVAL | ( | value | ) | ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos))) |
Definition at line 1270 of file component/gmac.h.
| #define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) |
(GMAC_ST2CW022) Mask Value
Definition at line 1269 of file component/gmac.h.
| #define GMAC_ST2CW022_MASKVAL_Pos 0 |
Definition at line 1268 of file component/gmac.h.
| #define GMAC_ST2CW023_COMPVAL | ( | value | ) | ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos))) |
Definition at line 1291 of file component/gmac.h.
| #define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) |
(GMAC_ST2CW023) Compare Value
Definition at line 1290 of file component/gmac.h.
| #define GMAC_ST2CW023_COMPVAL_Pos 16 |
Definition at line 1289 of file component/gmac.h.
| #define GMAC_ST2CW023_MASKVAL | ( | value | ) | ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos))) |
Definition at line 1288 of file component/gmac.h.
| #define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) |
(GMAC_ST2CW023) Mask Value
Definition at line 1287 of file component/gmac.h.
| #define GMAC_ST2CW023_MASKVAL_Pos 0 |
Definition at line 1286 of file component/gmac.h.
| #define GMAC_ST2CW02_COMPVAL | ( | value | ) | ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos))) |
Definition at line 913 of file component/gmac.h.
| #define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) |
(GMAC_ST2CW02) Compare Value
Definition at line 912 of file component/gmac.h.
| #define GMAC_ST2CW02_COMPVAL_Pos 16 |
Definition at line 911 of file component/gmac.h.
| #define GMAC_ST2CW02_MASKVAL | ( | value | ) | ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos))) |
Definition at line 910 of file component/gmac.h.
| #define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) |
(GMAC_ST2CW02) Mask Value
Definition at line 909 of file component/gmac.h.
| #define GMAC_ST2CW02_MASKVAL_Pos 0 |
Definition at line 908 of file component/gmac.h.
| #define GMAC_ST2CW03_COMPVAL | ( | value | ) | ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos))) |
Definition at line 931 of file component/gmac.h.
| #define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) |
(GMAC_ST2CW03) Compare Value
Definition at line 930 of file component/gmac.h.
| #define GMAC_ST2CW03_COMPVAL_Pos 16 |
Definition at line 929 of file component/gmac.h.
| #define GMAC_ST2CW03_MASKVAL | ( | value | ) | ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos))) |
Definition at line 928 of file component/gmac.h.
| #define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) |
(GMAC_ST2CW03) Mask Value
Definition at line 927 of file component/gmac.h.
| #define GMAC_ST2CW03_MASKVAL_Pos 0 |
Definition at line 926 of file component/gmac.h.
| #define GMAC_ST2CW04_COMPVAL | ( | value | ) | ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos))) |
Definition at line 949 of file component/gmac.h.
| #define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) |
(GMAC_ST2CW04) Compare Value
Definition at line 948 of file component/gmac.h.
| #define GMAC_ST2CW04_COMPVAL_Pos 16 |
Definition at line 947 of file component/gmac.h.
| #define GMAC_ST2CW04_MASKVAL | ( | value | ) | ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos))) |
Definition at line 946 of file component/gmac.h.
| #define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) |
(GMAC_ST2CW04) Mask Value
Definition at line 945 of file component/gmac.h.
| #define GMAC_ST2CW04_MASKVAL_Pos 0 |
Definition at line 944 of file component/gmac.h.
| #define GMAC_ST2CW05_COMPVAL | ( | value | ) | ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos))) |
Definition at line 967 of file component/gmac.h.
| #define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) |
(GMAC_ST2CW05) Compare Value
Definition at line 966 of file component/gmac.h.
| #define GMAC_ST2CW05_COMPVAL_Pos 16 |
Definition at line 965 of file component/gmac.h.
| #define GMAC_ST2CW05_MASKVAL | ( | value | ) | ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos))) |
Definition at line 964 of file component/gmac.h.
| #define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) |
(GMAC_ST2CW05) Mask Value
Definition at line 963 of file component/gmac.h.
| #define GMAC_ST2CW05_MASKVAL_Pos 0 |
Definition at line 962 of file component/gmac.h.
| #define GMAC_ST2CW06_COMPVAL | ( | value | ) | ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos))) |
Definition at line 985 of file component/gmac.h.
| #define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) |
(GMAC_ST2CW06) Compare Value
Definition at line 984 of file component/gmac.h.
| #define GMAC_ST2CW06_COMPVAL_Pos 16 |
Definition at line 983 of file component/gmac.h.
| #define GMAC_ST2CW06_MASKVAL | ( | value | ) | ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos))) |
Definition at line 982 of file component/gmac.h.
| #define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) |
(GMAC_ST2CW06) Mask Value
Definition at line 981 of file component/gmac.h.
| #define GMAC_ST2CW06_MASKVAL_Pos 0 |
Definition at line 980 of file component/gmac.h.
| #define GMAC_ST2CW07_COMPVAL | ( | value | ) | ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos))) |
Definition at line 1003 of file component/gmac.h.
| #define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) |
(GMAC_ST2CW07) Compare Value
Definition at line 1002 of file component/gmac.h.
| #define GMAC_ST2CW07_COMPVAL_Pos 16 |
Definition at line 1001 of file component/gmac.h.
| #define GMAC_ST2CW07_MASKVAL | ( | value | ) | ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos))) |
Definition at line 1000 of file component/gmac.h.
| #define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) |
(GMAC_ST2CW07) Mask Value
Definition at line 999 of file component/gmac.h.
| #define GMAC_ST2CW07_MASKVAL_Pos 0 |
Definition at line 998 of file component/gmac.h.
| #define GMAC_ST2CW08_COMPVAL | ( | value | ) | ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos))) |
Definition at line 1021 of file component/gmac.h.
| #define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) |
(GMAC_ST2CW08) Compare Value
Definition at line 1020 of file component/gmac.h.
| #define GMAC_ST2CW08_COMPVAL_Pos 16 |
Definition at line 1019 of file component/gmac.h.
| #define GMAC_ST2CW08_MASKVAL | ( | value | ) | ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos))) |
Definition at line 1018 of file component/gmac.h.
| #define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) |
(GMAC_ST2CW08) Mask Value
Definition at line 1017 of file component/gmac.h.
| #define GMAC_ST2CW08_MASKVAL_Pos 0 |
Definition at line 1016 of file component/gmac.h.
| #define GMAC_ST2CW09_COMPVAL | ( | value | ) | ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos))) |
Definition at line 1039 of file component/gmac.h.
| #define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) |
(GMAC_ST2CW09) Compare Value
Definition at line 1038 of file component/gmac.h.
| #define GMAC_ST2CW09_COMPVAL_Pos 16 |
Definition at line 1037 of file component/gmac.h.
| #define GMAC_ST2CW09_MASKVAL | ( | value | ) | ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos))) |
Definition at line 1036 of file component/gmac.h.
| #define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) |
(GMAC_ST2CW09) Mask Value
Definition at line 1035 of file component/gmac.h.
| #define GMAC_ST2CW09_MASKVAL_Pos 0 |
Definition at line 1034 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos))) |
Definition at line 884 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW10) Offset from the byte after the EtherType field
Definition at line 886 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW10) Offset from the start of the frame
Definition at line 885 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW10) Offset from the byte after the IP header field
Definition at line 887 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) |
(GMAC_ST2CW10) Ethernet Frame Offset Start
Definition at line 883 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSSTRT_Pos 7 |
Definition at line 882 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field
Definition at line 888 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSVAL | ( | value | ) | ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos))) |
Definition at line 881 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) |
(GMAC_ST2CW10) Offset Value in Bytes
Definition at line 880 of file component/gmac.h.
| #define GMAC_ST2CW10_OFFSVAL_Pos 0 |
Definition at line 879 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos))) |
Definition at line 1064 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW110) Offset from the byte after the EtherType field
Definition at line 1066 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW110) Offset from the start of the frame
Definition at line 1065 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW110) Offset from the byte after the IP header field
Definition at line 1067 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) |
(GMAC_ST2CW110) Ethernet Frame Offset Start
Definition at line 1063 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSSTRT_Pos 7 |
Definition at line 1062 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field
Definition at line 1068 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSVAL | ( | value | ) | ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos))) |
Definition at line 1061 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) |
(GMAC_ST2CW110) Offset Value in Bytes
Definition at line 1060 of file component/gmac.h.
| #define GMAC_ST2CW110_OFFSVAL_Pos 0 |
Definition at line 1059 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos))) |
Definition at line 1082 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW111) Offset from the byte after the EtherType field
Definition at line 1084 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW111) Offset from the start of the frame
Definition at line 1083 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW111) Offset from the byte after the IP header field
Definition at line 1085 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) |
(GMAC_ST2CW111) Ethernet Frame Offset Start
Definition at line 1081 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSSTRT_Pos 7 |
Definition at line 1080 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field
Definition at line 1086 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSVAL | ( | value | ) | ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos))) |
Definition at line 1079 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) |
(GMAC_ST2CW111) Offset Value in Bytes
Definition at line 1078 of file component/gmac.h.
| #define GMAC_ST2CW111_OFFSVAL_Pos 0 |
Definition at line 1077 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos))) |
Definition at line 1100 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW112) Offset from the byte after the EtherType field
Definition at line 1102 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW112) Offset from the start of the frame
Definition at line 1101 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW112) Offset from the byte after the IP header field
Definition at line 1103 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) |
(GMAC_ST2CW112) Ethernet Frame Offset Start
Definition at line 1099 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSSTRT_Pos 7 |
Definition at line 1098 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field
Definition at line 1104 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSVAL | ( | value | ) | ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos))) |
Definition at line 1097 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) |
(GMAC_ST2CW112) Offset Value in Bytes
Definition at line 1096 of file component/gmac.h.
| #define GMAC_ST2CW112_OFFSVAL_Pos 0 |
Definition at line 1095 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos))) |
Definition at line 1118 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW113) Offset from the byte after the EtherType field
Definition at line 1120 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW113) Offset from the start of the frame
Definition at line 1119 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW113) Offset from the byte after the IP header field
Definition at line 1121 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) |
(GMAC_ST2CW113) Ethernet Frame Offset Start
Definition at line 1117 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSSTRT_Pos 7 |
Definition at line 1116 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field
Definition at line 1122 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSVAL | ( | value | ) | ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos))) |
Definition at line 1115 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) |
(GMAC_ST2CW113) Offset Value in Bytes
Definition at line 1114 of file component/gmac.h.
| #define GMAC_ST2CW113_OFFSVAL_Pos 0 |
Definition at line 1113 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos))) |
Definition at line 1136 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW114) Offset from the byte after the EtherType field
Definition at line 1138 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW114) Offset from the start of the frame
Definition at line 1137 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW114) Offset from the byte after the IP header field
Definition at line 1139 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) |
(GMAC_ST2CW114) Ethernet Frame Offset Start
Definition at line 1135 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSSTRT_Pos 7 |
Definition at line 1134 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field
Definition at line 1140 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSVAL | ( | value | ) | ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos))) |
Definition at line 1133 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) |
(GMAC_ST2CW114) Offset Value in Bytes
Definition at line 1132 of file component/gmac.h.
| #define GMAC_ST2CW114_OFFSVAL_Pos 0 |
Definition at line 1131 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos))) |
Definition at line 1154 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW115) Offset from the byte after the EtherType field
Definition at line 1156 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW115) Offset from the start of the frame
Definition at line 1155 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW115) Offset from the byte after the IP header field
Definition at line 1157 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) |
(GMAC_ST2CW115) Ethernet Frame Offset Start
Definition at line 1153 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSSTRT_Pos 7 |
Definition at line 1152 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field
Definition at line 1158 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSVAL | ( | value | ) | ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos))) |
Definition at line 1151 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) |
(GMAC_ST2CW115) Offset Value in Bytes
Definition at line 1150 of file component/gmac.h.
| #define GMAC_ST2CW115_OFFSVAL_Pos 0 |
Definition at line 1149 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos))) |
Definition at line 1172 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW116) Offset from the byte after the EtherType field
Definition at line 1174 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW116) Offset from the start of the frame
Definition at line 1173 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW116) Offset from the byte after the IP header field
Definition at line 1175 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) |
(GMAC_ST2CW116) Ethernet Frame Offset Start
Definition at line 1171 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSSTRT_Pos 7 |
Definition at line 1170 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field
Definition at line 1176 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSVAL | ( | value | ) | ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos))) |
Definition at line 1169 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) |
(GMAC_ST2CW116) Offset Value in Bytes
Definition at line 1168 of file component/gmac.h.
| #define GMAC_ST2CW116_OFFSVAL_Pos 0 |
Definition at line 1167 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos))) |
Definition at line 1190 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW117) Offset from the byte after the EtherType field
Definition at line 1192 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW117) Offset from the start of the frame
Definition at line 1191 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW117) Offset from the byte after the IP header field
Definition at line 1193 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) |
(GMAC_ST2CW117) Ethernet Frame Offset Start
Definition at line 1189 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSSTRT_Pos 7 |
Definition at line 1188 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field
Definition at line 1194 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSVAL | ( | value | ) | ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos))) |
Definition at line 1187 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) |
(GMAC_ST2CW117) Offset Value in Bytes
Definition at line 1186 of file component/gmac.h.
| #define GMAC_ST2CW117_OFFSVAL_Pos 0 |
Definition at line 1185 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos))) |
Definition at line 1208 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW118) Offset from the byte after the EtherType field
Definition at line 1210 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW118) Offset from the start of the frame
Definition at line 1209 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW118) Offset from the byte after the IP header field
Definition at line 1211 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) |
(GMAC_ST2CW118) Ethernet Frame Offset Start
Definition at line 1207 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSSTRT_Pos 7 |
Definition at line 1206 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field
Definition at line 1212 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSVAL | ( | value | ) | ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos))) |
Definition at line 1205 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) |
(GMAC_ST2CW118) Offset Value in Bytes
Definition at line 1204 of file component/gmac.h.
| #define GMAC_ST2CW118_OFFSVAL_Pos 0 |
Definition at line 1203 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos))) |
Definition at line 1226 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW119) Offset from the byte after the EtherType field
Definition at line 1228 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW119) Offset from the start of the frame
Definition at line 1227 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW119) Offset from the byte after the IP header field
Definition at line 1229 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) |
(GMAC_ST2CW119) Ethernet Frame Offset Start
Definition at line 1225 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSSTRT_Pos 7 |
Definition at line 1224 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field
Definition at line 1230 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSVAL | ( | value | ) | ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos))) |
Definition at line 1223 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) |
(GMAC_ST2CW119) Offset Value in Bytes
Definition at line 1222 of file component/gmac.h.
| #define GMAC_ST2CW119_OFFSVAL_Pos 0 |
Definition at line 1221 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos))) |
Definition at line 902 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW11) Offset from the byte after the EtherType field
Definition at line 904 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW11) Offset from the start of the frame
Definition at line 903 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW11) Offset from the byte after the IP header field
Definition at line 905 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) |
(GMAC_ST2CW11) Ethernet Frame Offset Start
Definition at line 901 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSSTRT_Pos 7 |
Definition at line 900 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field
Definition at line 906 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSVAL | ( | value | ) | ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos))) |
Definition at line 899 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) |
(GMAC_ST2CW11) Offset Value in Bytes
Definition at line 898 of file component/gmac.h.
| #define GMAC_ST2CW11_OFFSVAL_Pos 0 |
Definition at line 897 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos))) |
Definition at line 1244 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW120) Offset from the byte after the EtherType field
Definition at line 1246 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW120) Offset from the start of the frame
Definition at line 1245 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW120) Offset from the byte after the IP header field
Definition at line 1247 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) |
(GMAC_ST2CW120) Ethernet Frame Offset Start
Definition at line 1243 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSSTRT_Pos 7 |
Definition at line 1242 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field
Definition at line 1248 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSVAL | ( | value | ) | ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos))) |
Definition at line 1241 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) |
(GMAC_ST2CW120) Offset Value in Bytes
Definition at line 1240 of file component/gmac.h.
| #define GMAC_ST2CW120_OFFSVAL_Pos 0 |
Definition at line 1239 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos))) |
Definition at line 1262 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW121) Offset from the byte after the EtherType field
Definition at line 1264 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW121) Offset from the start of the frame
Definition at line 1263 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW121) Offset from the byte after the IP header field
Definition at line 1265 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) |
(GMAC_ST2CW121) Ethernet Frame Offset Start
Definition at line 1261 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSSTRT_Pos 7 |
Definition at line 1260 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field
Definition at line 1266 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSVAL | ( | value | ) | ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos))) |
Definition at line 1259 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) |
(GMAC_ST2CW121) Offset Value in Bytes
Definition at line 1258 of file component/gmac.h.
| #define GMAC_ST2CW121_OFFSVAL_Pos 0 |
Definition at line 1257 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos))) |
Definition at line 1280 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW122) Offset from the byte after the EtherType field
Definition at line 1282 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW122) Offset from the start of the frame
Definition at line 1281 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW122) Offset from the byte after the IP header field
Definition at line 1283 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) |
(GMAC_ST2CW122) Ethernet Frame Offset Start
Definition at line 1279 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSSTRT_Pos 7 |
Definition at line 1278 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field
Definition at line 1284 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSVAL | ( | value | ) | ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos))) |
Definition at line 1277 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) |
(GMAC_ST2CW122) Offset Value in Bytes
Definition at line 1276 of file component/gmac.h.
| #define GMAC_ST2CW122_OFFSVAL_Pos 0 |
Definition at line 1275 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos))) |
Definition at line 1298 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW123) Offset from the byte after the EtherType field
Definition at line 1300 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW123) Offset from the start of the frame
Definition at line 1299 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW123) Offset from the byte after the IP header field
Definition at line 1301 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) |
(GMAC_ST2CW123) Ethernet Frame Offset Start
Definition at line 1297 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSSTRT_Pos 7 |
Definition at line 1296 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field
Definition at line 1302 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSVAL | ( | value | ) | ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos))) |
Definition at line 1295 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) |
(GMAC_ST2CW123) Offset Value in Bytes
Definition at line 1294 of file component/gmac.h.
| #define GMAC_ST2CW123_OFFSVAL_Pos 0 |
Definition at line 1293 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos))) |
Definition at line 920 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW12) Offset from the byte after the EtherType field
Definition at line 922 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW12) Offset from the start of the frame
Definition at line 921 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW12) Offset from the byte after the IP header field
Definition at line 923 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) |
(GMAC_ST2CW12) Ethernet Frame Offset Start
Definition at line 919 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSSTRT_Pos 7 |
Definition at line 918 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field
Definition at line 924 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSVAL | ( | value | ) | ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos))) |
Definition at line 917 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) |
(GMAC_ST2CW12) Offset Value in Bytes
Definition at line 916 of file component/gmac.h.
| #define GMAC_ST2CW12_OFFSVAL_Pos 0 |
Definition at line 915 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos))) |
Definition at line 938 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW13) Offset from the byte after the EtherType field
Definition at line 940 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW13) Offset from the start of the frame
Definition at line 939 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW13) Offset from the byte after the IP header field
Definition at line 941 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) |
(GMAC_ST2CW13) Ethernet Frame Offset Start
Definition at line 937 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSSTRT_Pos 7 |
Definition at line 936 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field
Definition at line 942 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSVAL | ( | value | ) | ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos))) |
Definition at line 935 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) |
(GMAC_ST2CW13) Offset Value in Bytes
Definition at line 934 of file component/gmac.h.
| #define GMAC_ST2CW13_OFFSVAL_Pos 0 |
Definition at line 933 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos))) |
Definition at line 956 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW14) Offset from the byte after the EtherType field
Definition at line 958 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW14) Offset from the start of the frame
Definition at line 957 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW14) Offset from the byte after the IP header field
Definition at line 959 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) |
(GMAC_ST2CW14) Ethernet Frame Offset Start
Definition at line 955 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSSTRT_Pos 7 |
Definition at line 954 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field
Definition at line 960 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSVAL | ( | value | ) | ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos))) |
Definition at line 953 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) |
(GMAC_ST2CW14) Offset Value in Bytes
Definition at line 952 of file component/gmac.h.
| #define GMAC_ST2CW14_OFFSVAL_Pos 0 |
Definition at line 951 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos))) |
Definition at line 974 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW15) Offset from the byte after the EtherType field
Definition at line 976 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW15) Offset from the start of the frame
Definition at line 975 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW15) Offset from the byte after the IP header field
Definition at line 977 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) |
(GMAC_ST2CW15) Ethernet Frame Offset Start
Definition at line 973 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSSTRT_Pos 7 |
Definition at line 972 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field
Definition at line 978 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSVAL | ( | value | ) | ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos))) |
Definition at line 971 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) |
(GMAC_ST2CW15) Offset Value in Bytes
Definition at line 970 of file component/gmac.h.
| #define GMAC_ST2CW15_OFFSVAL_Pos 0 |
Definition at line 969 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos))) |
Definition at line 992 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW16) Offset from the byte after the EtherType field
Definition at line 994 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW16) Offset from the start of the frame
Definition at line 993 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW16) Offset from the byte after the IP header field
Definition at line 995 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) |
(GMAC_ST2CW16) Ethernet Frame Offset Start
Definition at line 991 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSSTRT_Pos 7 |
Definition at line 990 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field
Definition at line 996 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSVAL | ( | value | ) | ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos))) |
Definition at line 989 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) |
(GMAC_ST2CW16) Offset Value in Bytes
Definition at line 988 of file component/gmac.h.
| #define GMAC_ST2CW16_OFFSVAL_Pos 0 |
Definition at line 987 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos))) |
Definition at line 1010 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW17) Offset from the byte after the EtherType field
Definition at line 1012 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW17) Offset from the start of the frame
Definition at line 1011 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW17) Offset from the byte after the IP header field
Definition at line 1013 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) |
(GMAC_ST2CW17) Ethernet Frame Offset Start
Definition at line 1009 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSSTRT_Pos 7 |
Definition at line 1008 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field
Definition at line 1014 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSVAL | ( | value | ) | ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos))) |
Definition at line 1007 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) |
(GMAC_ST2CW17) Offset Value in Bytes
Definition at line 1006 of file component/gmac.h.
| #define GMAC_ST2CW17_OFFSVAL_Pos 0 |
Definition at line 1005 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos))) |
Definition at line 1028 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW18) Offset from the byte after the EtherType field
Definition at line 1030 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW18) Offset from the start of the frame
Definition at line 1029 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW18) Offset from the byte after the IP header field
Definition at line 1031 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) |
(GMAC_ST2CW18) Ethernet Frame Offset Start
Definition at line 1027 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSSTRT_Pos 7 |
Definition at line 1026 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field
Definition at line 1032 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSVAL | ( | value | ) | ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos))) |
Definition at line 1025 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) |
(GMAC_ST2CW18) Offset Value in Bytes
Definition at line 1024 of file component/gmac.h.
| #define GMAC_ST2CW18_OFFSVAL_Pos 0 |
Definition at line 1023 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSSTRT | ( | value | ) | ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos))) |
Definition at line 1046 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) |
(GMAC_ST2CW19) Offset from the byte after the EtherType field
Definition at line 1048 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) |
(GMAC_ST2CW19) Offset from the start of the frame
Definition at line 1047 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) |
(GMAC_ST2CW19) Offset from the byte after the IP header field
Definition at line 1049 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) |
(GMAC_ST2CW19) Ethernet Frame Offset Start
Definition at line 1045 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSSTRT_Pos 7 |
Definition at line 1044 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) |
(GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field
Definition at line 1050 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSVAL | ( | value | ) | ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos))) |
Definition at line 1043 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) |
(GMAC_ST2CW19) Offset Value in Bytes
Definition at line 1042 of file component/gmac.h.
| #define GMAC_ST2CW19_OFFSVAL_Pos 0 |
Definition at line 1041 of file component/gmac.h.
| #define GMAC_ST2ER_COMPVAL | ( | value | ) | ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) |
Definition at line 870 of file component/gmac.h.
| #define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) |
(GMAC_ST2ER[4]) Ethertype Compare Value
Definition at line 869 of file component/gmac.h.
| #define GMAC_ST2ER_COMPVAL_Pos 0 |
Definition at line 868 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPA | ( | value | ) | ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) |
Definition at line 833 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) |
(GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x
Definition at line 832 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPA_Pos 13 |
Definition at line 831 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPAE (0x1u << 18) |
(GMAC_ST2RPQ[8]) Compare A Enable
Definition at line 834 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPB | ( | value | ) | ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) |
Definition at line 837 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) |
(GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x
Definition at line 836 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPB_Pos 19 |
Definition at line 835 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPBE (0x1u << 24) |
(GMAC_ST2RPQ[8]) Compare B Enable
Definition at line 838 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPC | ( | value | ) | ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) |
Definition at line 841 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) |
(GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x
Definition at line 840 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPC_Pos 25 |
Definition at line 839 of file component/gmac.h.
| #define GMAC_ST2RPQ_COMPCE (0x1u << 30) |
(GMAC_ST2RPQ[8]) Compare C Enable
Definition at line 842 of file component/gmac.h.
| #define GMAC_ST2RPQ_ETHE (0x1u << 12) |
(GMAC_ST2RPQ[8]) EtherType Enable
Definition at line 830 of file component/gmac.h.
| #define GMAC_ST2RPQ_I2ETH | ( | value | ) | ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) |
Definition at line 829 of file component/gmac.h.
| #define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) |
(GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x
Definition at line 828 of file component/gmac.h.
| #define GMAC_ST2RPQ_I2ETH_Pos 9 |
Definition at line 827 of file component/gmac.h.
| #define GMAC_ST2RPQ_QNB | ( | value | ) | ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) |
Definition at line 822 of file component/gmac.h.
| #define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) |
(GMAC_ST2RPQ[8]) Queue Number (0-5)
Definition at line 821 of file component/gmac.h.
| #define GMAC_ST2RPQ_QNB_Pos 0 |
Definition at line 820 of file component/gmac.h.
| #define GMAC_ST2RPQ_VLANE (0x1u << 8) |
(GMAC_ST2RPQ[8]) VLAN Enable
Definition at line 826 of file component/gmac.h.
| #define GMAC_ST2RPQ_VLANP | ( | value | ) | ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) |
Definition at line 825 of file component/gmac.h.
| #define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) |
(GMAC_ST2RPQ[8]) VLAN Priority
Definition at line 824 of file component/gmac.h.
| #define GMAC_ST2RPQ_VLANP_Pos 4 |
Definition at line 823 of file component/gmac.h.
| #define GMAC_SVLAN_ESVLAN (0x1u << 31) |
(GMAC_SVLAN) Enable Stacked VLAN Processing Mode
Definition at line 529 of file component/gmac.h.
| #define GMAC_SVLAN_VLAN_TYPE | ( | value | ) | ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) |
Definition at line 528 of file component/gmac.h.
| #define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) |
(GMAC_SVLAN) User Defined VLAN_TYPE Field
Definition at line 527 of file component/gmac.h.
| #define GMAC_SVLAN_VLAN_TYPE_Pos 0 |
Definition at line 526 of file component/gmac.h.
| #define GMAC_TA_ADJ (0x1u << 31) |
(GMAC_TA) Adjust 1588 Timer
Definition at line 729 of file component/gmac.h.
| #define GMAC_TA_ITDT | ( | value | ) | ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) |
Definition at line 728 of file component/gmac.h.
| #define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) |
(GMAC_TA) Increment/Decrement
Definition at line 727 of file component/gmac.h.
| #define GMAC_TA_ITDT_Pos 0 |
Definition at line 726 of file component/gmac.h.
| #define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) |
(GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error
Definition at line 666 of file component/gmac.h.
| #define GMAC_TBFR1023_NFRX_Pos 0 |
Definition at line 665 of file component/gmac.h.
| #define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) |
(GMAC_TBFR127) 65 to 127 Byte Frames Received without Error
Definition at line 657 of file component/gmac.h.
| #define GMAC_TBFR127_NFRX_Pos 0 |
Definition at line 656 of file component/gmac.h.
| #define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) |
(GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error
Definition at line 669 of file component/gmac.h.
| #define GMAC_TBFR1518_NFRX_Pos 0 |
Definition at line 668 of file component/gmac.h.
| #define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) |
(GMAC_TBFR255) 128 to 255 Byte Frames Received without Error
Definition at line 660 of file component/gmac.h.
| #define GMAC_TBFR255_NFRX_Pos 0 |
Definition at line 659 of file component/gmac.h.
| #define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) |
(GMAC_TBFR511) 256 to 511 Byte Frames Received without Error
Definition at line 663 of file component/gmac.h.
| #define GMAC_TBFR511_NFRX_Pos 0 |
Definition at line 662 of file component/gmac.h.
| #define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) |
(GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error
Definition at line 606 of file component/gmac.h.
| #define GMAC_TBFT1023_NFTX_Pos 0 |
Definition at line 605 of file component/gmac.h.
| #define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) |
(GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error
Definition at line 597 of file component/gmac.h.
| #define GMAC_TBFT127_NFTX_Pos 0 |
Definition at line 596 of file component/gmac.h.
| #define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) |
(GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error
Definition at line 609 of file component/gmac.h.
| #define GMAC_TBFT1518_NFTX_Pos 0 |
Definition at line 608 of file component/gmac.h.
| #define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) |
(GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error
Definition at line 600 of file component/gmac.h.
| #define GMAC_TBFT255_NFTX_Pos 0 |
Definition at line 599 of file component/gmac.h.
| #define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) |
(GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error
Definition at line 603 of file component/gmac.h.
| #define GMAC_TBFT511_NFTX_Pos 0 |
Definition at line 602 of file component/gmac.h.
| #define GMAC_TBQB_ADDR | ( | value | ) | ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) |
Definition at line 333 of file component/gmac.h.
| #define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) |
(GMAC_TBQB) Transmit Buffer Queue Base Address
Definition at line 332 of file component/gmac.h.
| #define GMAC_TBQB_ADDR_Pos 2 |
Definition at line 331 of file component/gmac.h.
| #define GMAC_TBQBAPQ_TXBQBA | ( | value | ) | ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) |
Definition at line 787 of file component/gmac.h.
| #define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) |
(GMAC_TBQBAPQ[5]) Transmit Buffer Queue Base Address
Definition at line 786 of file component/gmac.h.
| #define GMAC_TBQBAPQ_TXBQBA_Pos 2 |
Definition at line 785 of file component/gmac.h.
| #define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) |
(GMAC_TCE) TCP Checksum Errors
Definition at line 705 of file component/gmac.h.
| #define GMAC_TCE_TCKER_Pos 0 |
Definition at line 704 of file component/gmac.h.
| #define GMAC_TI_ACNS | ( | value | ) | ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) |
Definition at line 736 of file component/gmac.h.
| #define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) |
(GMAC_TI) Alternative Count Nanoseconds
Definition at line 735 of file component/gmac.h.
| #define GMAC_TI_ACNS_Pos 8 |
Definition at line 734 of file component/gmac.h.
| #define GMAC_TI_CNS | ( | value | ) | ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) |
Definition at line 733 of file component/gmac.h.
| #define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) |
(GMAC_TI) Count Nanoseconds
Definition at line 732 of file component/gmac.h.
| #define GMAC_TI_CNS_Pos 0 |
Definition at line 731 of file component/gmac.h.
| #define GMAC_TI_NIT | ( | value | ) | ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) |
Definition at line 739 of file component/gmac.h.
| #define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) |
(GMAC_TI) Number of Increments
Definition at line 738 of file component/gmac.h.
| #define GMAC_TI_NIT_Pos 16 |
Definition at line 737 of file component/gmac.h.
| #define GMAC_TIDM1_ENID1 (0x1u << 31) |
(GMAC_TIDM1) Enable Copying of TID Matched Frames
Definition at line 497 of file component/gmac.h.
| #define GMAC_TIDM1_TID | ( | value | ) | ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) |
Definition at line 496 of file component/gmac.h.
| #define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) |
(GMAC_TIDM1) Type ID Match 1
Definition at line 495 of file component/gmac.h.
| #define GMAC_TIDM1_TID_Pos 0 |
Definition at line 494 of file component/gmac.h.
| #define GMAC_TIDM2_ENID2 (0x1u << 31) |
(GMAC_TIDM2) Enable Copying of TID Matched Frames
Definition at line 502 of file component/gmac.h.
| #define GMAC_TIDM2_TID | ( | value | ) | ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) |
Definition at line 501 of file component/gmac.h.
| #define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) |
(GMAC_TIDM2) Type ID Match 2
Definition at line 500 of file component/gmac.h.
| #define GMAC_TIDM2_TID_Pos 0 |
Definition at line 499 of file component/gmac.h.
| #define GMAC_TIDM3_ENID3 (0x1u << 31) |
(GMAC_TIDM3) Enable Copying of TID Matched Frames
Definition at line 507 of file component/gmac.h.
| #define GMAC_TIDM3_TID | ( | value | ) | ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) |
Definition at line 506 of file component/gmac.h.
| #define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) |
(GMAC_TIDM3) Type ID Match 3
Definition at line 505 of file component/gmac.h.
| #define GMAC_TIDM3_TID_Pos 0 |
Definition at line 504 of file component/gmac.h.
| #define GMAC_TIDM4_ENID4 (0x1u << 31) |
(GMAC_TIDM4) Enable Copying of TID Matched Frames
Definition at line 512 of file component/gmac.h.
| #define GMAC_TIDM4_TID | ( | value | ) | ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) |
Definition at line 511 of file component/gmac.h.
| #define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) |
(GMAC_TIDM4) Type ID Match 4
Definition at line 510 of file component/gmac.h.
| #define GMAC_TIDM4_TID_Pos 0 |
Definition at line 509 of file component/gmac.h.
| #define GMAC_TISUBN_LSBTIR | ( | value | ) | ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) |
Definition at line 712 of file component/gmac.h.
| #define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) |
(GMAC_TISUBN) Lower Significant Bits of Timer Increment Register
Definition at line 711 of file component/gmac.h.
| #define GMAC_TISUBN_LSBTIR_Pos 0 |
Definition at line 710 of file component/gmac.h.
| #define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) |
(GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error
Definition at line 672 of file component/gmac.h.
| #define GMAC_TMXBFR_NFRX_Pos 0 |
Definition at line 671 of file component/gmac.h.
| #define GMAC_TN_TNS | ( | value | ) | ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) |
Definition at line 724 of file component/gmac.h.
| #define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) |
(GMAC_TN) Timer Count in Nanoseconds
Definition at line 723 of file component/gmac.h.
| #define GMAC_TN_TNS_Pos 0 |
Definition at line 722 of file component/gmac.h.
| #define GMAC_TPFCP_PEV | ( | value | ) | ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) |
Definition at line 533 of file component/gmac.h.
| #define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) |
(GMAC_TPFCP) Priority Enable Vector
Definition at line 532 of file component/gmac.h.
| #define GMAC_TPFCP_PEV_Pos 0 |
Definition at line 531 of file component/gmac.h.
| #define GMAC_TPFCP_PQ | ( | value | ) | ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) |
Definition at line 536 of file component/gmac.h.
| #define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) |
(GMAC_TPFCP) Pause Quantum
Definition at line 535 of file component/gmac.h.
| #define GMAC_TPFCP_PQ_Pos 8 |
Definition at line 534 of file component/gmac.h.
| #define GMAC_TPQ_TPQ | ( | value | ) | ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) |
Definition at line 462 of file component/gmac.h.
| #define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) |
(GMAC_TPQ) Transmit Pause Quantum
Definition at line 461 of file component/gmac.h.
| #define GMAC_TPQ_TPQ_Pos 0 |
Definition at line 460 of file component/gmac.h.
| #define GMAC_TPSF_ENTXP (0x1u << 31) |
(GMAC_TPSF) Enable TX Partial Store and Forward Operation
Definition at line 467 of file component/gmac.h.
| #define GMAC_TPSF_TPB1ADR | ( | value | ) | ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) |
Definition at line 466 of file component/gmac.h.
| #define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) |
(GMAC_TPSF) Transmit Partial Store and Forward Address
Definition at line 465 of file component/gmac.h.
| #define GMAC_TPSF_TPB1ADR_Pos 0 |
Definition at line 464 of file component/gmac.h.
| #define GMAC_TSH_TCS | ( | value | ) | ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) |
Definition at line 716 of file component/gmac.h.
| #define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) |
(GMAC_TSH) Timer Count in Seconds
Definition at line 715 of file component/gmac.h.
| #define GMAC_TSH_TCS_Pos 0 |
Definition at line 714 of file component/gmac.h.
| #define GMAC_TSL_TCS | ( | value | ) | ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) |
Definition at line 720 of file component/gmac.h.
| #define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) |
(GMAC_TSL) Timer Count in Seconds
Definition at line 719 of file component/gmac.h.
| #define GMAC_TSL_TCS_Pos 0 |
Definition at line 718 of file component/gmac.h.
| #define GMAC_TSR_COL (0x1u << 1) |
(GMAC_TSR) Collision Occurred
Definition at line 320 of file component/gmac.h.
| #define GMAC_TSR_HRESP (0x1u << 8) |
(GMAC_TSR) HRESP Not OK
Definition at line 325 of file component/gmac.h.
| #define GMAC_TSR_RLE (0x1u << 2) |
(GMAC_TSR) Retry Limit Exceeded
Definition at line 321 of file component/gmac.h.
| #define GMAC_TSR_TFC (0x1u << 4) |
(GMAC_TSR) Transmit Frame Corruption Due to AHB Error
Definition at line 323 of file component/gmac.h.
| #define GMAC_TSR_TXCOMP (0x1u << 5) |
(GMAC_TSR) Transmit Complete
Definition at line 324 of file component/gmac.h.
| #define GMAC_TSR_TXGO (0x1u << 3) |
(GMAC_TSR) Transmit Go
Definition at line 322 of file component/gmac.h.
| #define GMAC_TSR_UBR (0x1u << 0) |
(GMAC_TSR) Used Bit Read
Definition at line 319 of file component/gmac.h.
| #define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) |
(GMAC_TUR) Transmit Underruns
Definition at line 615 of file component/gmac.h.
| #define GMAC_TUR_TXUNR_Pos 0 |
Definition at line 614 of file component/gmac.h.
| #define GMAC_TXLPI_COUNT_Msk (0xffffu << GMAC_TXLPI_COUNT_Pos) |
(GMAC_TXLPI) Count of LPI transitions (cleared on read)
Definition at line 772 of file component/gmac.h.
| #define GMAC_TXLPI_COUNT_Pos 0 |
Definition at line 771 of file component/gmac.h.
| #define GMAC_TXLPITIME_LPITIME_Msk (0xffffffu << GMAC_TXLPITIME_LPITIME_Pos) |
(GMAC_TXLPITIME) Time in LPI (cleared on read)
Definition at line 775 of file component/gmac.h.
| #define GMAC_TXLPITIME_LPITIME_Pos 0 |
Definition at line 774 of file component/gmac.h.
| #define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) |
(GMAC_UCE) UDP Checksum Errors
Definition at line 708 of file component/gmac.h.
| #define GMAC_UCE_UCKER_Pos 0 |
Definition at line 707 of file component/gmac.h.
| #define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) |
(GMAC_UFR) Undersize Frames Received
Definition at line 675 of file component/gmac.h.
| #define GMAC_UFR_UFRX_Pos 0 |
Definition at line 674 of file component/gmac.h.
| #define GMAC_UR_RMII (0x1u << 0) |
(GMAC_UR) Reduced MII Mode
Definition at line 294 of file component/gmac.h.
| #define GMAC_WOL_ARP (0x1u << 17) |
(GMAC_WOL) ARP Request IP Address
Definition at line 518 of file component/gmac.h.
| #define GMAC_WOL_IP | ( | value | ) | ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) |
Definition at line 516 of file component/gmac.h.
| #define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) |
(GMAC_WOL) ARP Request IP Address
Definition at line 515 of file component/gmac.h.
| #define GMAC_WOL_IP_Pos 0 |
Definition at line 514 of file component/gmac.h.
| #define GMAC_WOL_MAG (0x1u << 16) |
(GMAC_WOL) Magic Packet Event Enable
Definition at line 517 of file component/gmac.h.
| #define GMAC_WOL_MTI (0x1u << 19) |
(GMAC_WOL) Multicast Hash Event Enable
Definition at line 520 of file component/gmac.h.
| #define GMAC_WOL_SA1 (0x1u << 18) |
(GMAC_WOL) Specific Address Register 1 Event Enable
Definition at line 519 of file component/gmac.h.
| #define GMACSA_NUMBER 4 |
Gmac hardware registers.
Definition at line 51 of file component/gmac.h.