Modules | Macros
SAME70N19 definitions
Collaboration diagram for SAME70N19 definitions:

Modules

 CMSIS Definitions
 
 Peripheral Software API
 
 Registers Access Definitions
 
 Peripheral Ids Definitions
 
 Peripheral Base Address Definitions
 
 Peripheral Pio Definitions
 

Macros

#define AXIMX_ADDR   (0xA0000000u)
 
#define CHIP_CIDR   (0xA10D0A00UL)
 
#define CHIP_EXID   (0x00000001UL)
 
#define CHIP_FREQ_CPU_MAX   (300000000UL)
 
#define CHIP_FREQ_FWS_0   (23000000UL)
 Maximum operating frequency when FWS is 0. More...
 
#define CHIP_FREQ_FWS_1   (46000000UL)
 Maximum operating frequency when FWS is 1. More...
 
#define CHIP_FREQ_FWS_2   (69000000UL)
 Maximum operating frequency when FWS is 2. More...
 
#define CHIP_FREQ_FWS_3   (92000000UL)
 Maximum operating frequency when FWS is 3. More...
 
#define CHIP_FREQ_FWS_4   (115000000UL)
 Maximum operating frequency when FWS is 4. More...
 
#define CHIP_FREQ_FWS_5   (138000000UL)
 Maximum operating frequency when FWS is 5. More...
 
#define CHIP_FREQ_FWS_6   (150000000UL)
 Maximum operating frequency when FWS is 6. More...
 
#define CHIP_FREQ_MAINCK_RC_12MHZ   (12000000UL)
 
#define CHIP_FREQ_MAINCK_RC_4MHZ   (4000000UL)
 
#define CHIP_FREQ_MAINCK_RC_8MHZ   (8000000UL)
 
#define CHIP_FREQ_SLCK_RC   (32000UL)
 
#define CHIP_FREQ_SLCK_RC_MAX   (44000UL)
 
#define CHIP_FREQ_SLCK_RC_MIN   (20000UL)
 
#define CHIP_FREQ_XTAL_12M   (12000000UL)
 
#define CHIP_FREQ_XTAL_32K   (32768UL)
 
#define CHIP_JTAGID   (0x05B3D03FUL)
 
#define DTCM_ADDR   (0x20000000u)
 
#define IFLASH_ADDR   (0x00400000u)
 
#define IFLASH_LOCK_REGION_SIZE   (8192u)
 
#define IFLASH_NB_OF_LOCK_BITS   (32u)
 
#define IFLASH_NB_OF_PAGES   (1024u)
 
#define IFLASH_PAGE_SIZE   (512u)
 
#define IFLASH_SIZE   (0x80000u)
 
#define IRAM_ADDR   (0x20400000u)
 
#define IRAM_SIZE   (0x40000u)
 
#define IROM_ADDR   (0x00800000u)
 
#define ITCM_ADDR   (0x00000000u)
 
#define QSPIMEM_ADDR   (0x80000000u)
 

Detailed Description

This file defines all structures and symbols for SAME70N19:

Macro Definition Documentation

◆ AXIMX_ADDR

#define AXIMX_ADDR   (0xA0000000u)

AXI Bus Matrix base address

Definition at line 610 of file same70n19.h.

◆ CHIP_CIDR

#define CHIP_CIDR   (0xA10D0A00UL)

Definition at line 622 of file same70n19.h.

◆ CHIP_EXID

#define CHIP_EXID   (0x00000001UL)

Definition at line 623 of file same70n19.h.

◆ CHIP_FREQ_CPU_MAX

#define CHIP_FREQ_CPU_MAX   (300000000UL)

Definition at line 638 of file same70n19.h.

◆ CHIP_FREQ_FWS_0

#define CHIP_FREQ_FWS_0   (23000000UL)

Maximum operating frequency when FWS is 0.

Definition at line 643 of file same70n19.h.

◆ CHIP_FREQ_FWS_1

#define CHIP_FREQ_FWS_1   (46000000UL)

Maximum operating frequency when FWS is 1.

Definition at line 644 of file same70n19.h.

◆ CHIP_FREQ_FWS_2

#define CHIP_FREQ_FWS_2   (69000000UL)

Maximum operating frequency when FWS is 2.

Definition at line 645 of file same70n19.h.

◆ CHIP_FREQ_FWS_3

#define CHIP_FREQ_FWS_3   (92000000UL)

Maximum operating frequency when FWS is 3.

Definition at line 646 of file same70n19.h.

◆ CHIP_FREQ_FWS_4

#define CHIP_FREQ_FWS_4   (115000000UL)

Maximum operating frequency when FWS is 4.

Definition at line 647 of file same70n19.h.

◆ CHIP_FREQ_FWS_5

#define CHIP_FREQ_FWS_5   (138000000UL)

Maximum operating frequency when FWS is 5.

Definition at line 648 of file same70n19.h.

◆ CHIP_FREQ_FWS_6

#define CHIP_FREQ_FWS_6   (150000000UL)

Maximum operating frequency when FWS is 6.

Definition at line 649 of file same70n19.h.

◆ CHIP_FREQ_MAINCK_RC_12MHZ

#define CHIP_FREQ_MAINCK_RC_12MHZ   (12000000UL)

Definition at line 637 of file same70n19.h.

◆ CHIP_FREQ_MAINCK_RC_4MHZ

#define CHIP_FREQ_MAINCK_RC_4MHZ   (4000000UL)

Definition at line 635 of file same70n19.h.

◆ CHIP_FREQ_MAINCK_RC_8MHZ

#define CHIP_FREQ_MAINCK_RC_8MHZ   (8000000UL)

Definition at line 636 of file same70n19.h.

◆ CHIP_FREQ_SLCK_RC

#define CHIP_FREQ_SLCK_RC   (32000UL)

Definition at line 633 of file same70n19.h.

◆ CHIP_FREQ_SLCK_RC_MAX

#define CHIP_FREQ_SLCK_RC_MAX   (44000UL)

Definition at line 634 of file same70n19.h.

◆ CHIP_FREQ_SLCK_RC_MIN

#define CHIP_FREQ_SLCK_RC_MIN   (20000UL)

Definition at line 632 of file same70n19.h.

◆ CHIP_FREQ_XTAL_12M

#define CHIP_FREQ_XTAL_12M   (12000000UL)

Definition at line 640 of file same70n19.h.

◆ CHIP_FREQ_XTAL_32K

#define CHIP_FREQ_XTAL_32K   (32768UL)

Definition at line 639 of file same70n19.h.

◆ CHIP_JTAGID

#define CHIP_JTAGID   (0x05B3D03FUL)

Definition at line 621 of file same70n19.h.

◆ DTCM_ADDR

#define DTCM_ADDR   (0x20000000u)

Data Tightly Coupled Memory base address

Definition at line 614 of file same70n19.h.

◆ IFLASH_ADDR

#define IFLASH_ADDR   (0x00400000u)

Internal Flash base address

Definition at line 612 of file same70n19.h.

◆ IFLASH_LOCK_REGION_SIZE

#define IFLASH_LOCK_REGION_SIZE   (8192u)

Definition at line 604 of file same70n19.h.

◆ IFLASH_NB_OF_LOCK_BITS

#define IFLASH_NB_OF_LOCK_BITS   (32u)

Definition at line 606 of file same70n19.h.

◆ IFLASH_NB_OF_PAGES

#define IFLASH_NB_OF_PAGES   (1024u)

Definition at line 605 of file same70n19.h.

◆ IFLASH_PAGE_SIZE

#define IFLASH_PAGE_SIZE   (512u)

Definition at line 603 of file same70n19.h.

◆ IFLASH_SIZE

#define IFLASH_SIZE   (0x80000u)

Definition at line 602 of file same70n19.h.

◆ IRAM_ADDR

#define IRAM_ADDR   (0x20400000u)

Internal RAM base address

Definition at line 615 of file same70n19.h.

◆ IRAM_SIZE

#define IRAM_SIZE   (0x40000u)

Definition at line 607 of file same70n19.h.

◆ IROM_ADDR

#define IROM_ADDR   (0x00800000u)

Internal ROM base address

Definition at line 613 of file same70n19.h.

◆ ITCM_ADDR

#define ITCM_ADDR   (0x00000000u)

Instruction Tightly Coupled Memory base address

Definition at line 611 of file same70n19.h.

◆ QSPIMEM_ADDR

#define QSPIMEM_ADDR   (0x80000000u)

QSPI Memory base address

Definition at line 609 of file same70n19.h.



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autogenerated on Sat Sep 19 2020 03:19:09