|
Modules | |
| CMSIS Definitions | |
| Peripheral Software API | |
| Registers Access Definitions | |
| Peripheral Ids Definitions | |
| Peripheral Base Address Definitions | |
| Peripheral Pio Definitions | |
Macros | |
| #define | AXIMX_ADDR (0xA0000000u) |
| #define | CHIP_CIDR (0xA1020E01UL) |
| #define | CHIP_EXID (0x00000000UL) |
| #define | CHIP_FREQ_CPU_MAX (300000000UL) |
| #define | CHIP_FREQ_FWS_0 (23000000UL) |
| Maximum operating frequency when FWS is 0. More... | |
| #define | CHIP_FREQ_FWS_1 (46000000UL) |
| Maximum operating frequency when FWS is 1. More... | |
| #define | CHIP_FREQ_FWS_2 (69000000UL) |
| Maximum operating frequency when FWS is 2. More... | |
| #define | CHIP_FREQ_FWS_3 (92000000UL) |
| Maximum operating frequency when FWS is 3. More... | |
| #define | CHIP_FREQ_FWS_4 (115000000UL) |
| Maximum operating frequency when FWS is 4. More... | |
| #define | CHIP_FREQ_FWS_5 (138000000UL) |
| Maximum operating frequency when FWS is 5. More... | |
| #define | CHIP_FREQ_FWS_6 (150000000UL) |
| Maximum operating frequency when FWS is 6. More... | |
| #define | CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) |
| #define | CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) |
| #define | CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) |
| #define | CHIP_FREQ_SLCK_RC (32000UL) |
| #define | CHIP_FREQ_SLCK_RC_MAX (44000UL) |
| #define | CHIP_FREQ_SLCK_RC_MIN (20000UL) |
| #define | CHIP_FREQ_XTAL_12M (12000000UL) |
| #define | CHIP_FREQ_XTAL_32K (32768UL) |
| #define | CHIP_JTAGID (0x05B3D03FUL) |
| #define | DTCM_ADDR (0x20000000u) |
| #define | EBI_CS0_ADDR (0x60000000u) |
| #define | EBI_CS1_ADDR (0x61000000u) |
| #define | EBI_CS2_ADDR (0x62000000u) |
| #define | EBI_CS3_ADDR (0x63000000u) |
| #define | IFLASH_ADDR (0x00400000u) |
| #define | IFLASH_LOCK_REGION_SIZE (8192u) |
| #define | IFLASH_NB_OF_LOCK_BITS (128u) |
| #define | IFLASH_NB_OF_PAGES (4096u) |
| #define | IFLASH_PAGE_SIZE (512u) |
| #define | IFLASH_SIZE (0x200000u) |
| #define | IRAM_ADDR (0x20400000u) |
| #define | IRAM_SIZE (0x60000u) |
| #define | IROM_ADDR (0x00800000u) |
| #define | ITCM_ADDR (0x00000000u) |
| #define | QSPIMEM_ADDR (0x80000000u) |
| #define | SDRAM_CS_ADDR (0x70000000u) |
Detailed Description
This file defines all structures and symbols for SAME70J21B:
- registers and bitfields
- peripheral base address
- peripheral ID
- PIO definitions
Macro Definition Documentation
◆ AXIMX_ADDR
| #define AXIMX_ADDR (0xA0000000u) |
AXI Bus Matrix base address
Definition at line 573 of file same70j21b.h.
◆ CHIP_CIDR
| #define CHIP_CIDR (0xA1020E01UL) |
Definition at line 590 of file same70j21b.h.
◆ CHIP_EXID
| #define CHIP_EXID (0x00000000UL) |
Definition at line 591 of file same70j21b.h.
◆ CHIP_FREQ_CPU_MAX
| #define CHIP_FREQ_CPU_MAX (300000000UL) |
Definition at line 606 of file same70j21b.h.
◆ CHIP_FREQ_FWS_0
| #define CHIP_FREQ_FWS_0 (23000000UL) |
Maximum operating frequency when FWS is 0.
Definition at line 611 of file same70j21b.h.
◆ CHIP_FREQ_FWS_1
| #define CHIP_FREQ_FWS_1 (46000000UL) |
Maximum operating frequency when FWS is 1.
Definition at line 612 of file same70j21b.h.
◆ CHIP_FREQ_FWS_2
| #define CHIP_FREQ_FWS_2 (69000000UL) |
Maximum operating frequency when FWS is 2.
Definition at line 613 of file same70j21b.h.
◆ CHIP_FREQ_FWS_3
| #define CHIP_FREQ_FWS_3 (92000000UL) |
Maximum operating frequency when FWS is 3.
Definition at line 614 of file same70j21b.h.
◆ CHIP_FREQ_FWS_4
| #define CHIP_FREQ_FWS_4 (115000000UL) |
Maximum operating frequency when FWS is 4.
Definition at line 615 of file same70j21b.h.
◆ CHIP_FREQ_FWS_5
| #define CHIP_FREQ_FWS_5 (138000000UL) |
Maximum operating frequency when FWS is 5.
Definition at line 616 of file same70j21b.h.
◆ CHIP_FREQ_FWS_6
| #define CHIP_FREQ_FWS_6 (150000000UL) |
Maximum operating frequency when FWS is 6.
Definition at line 617 of file same70j21b.h.
◆ CHIP_FREQ_MAINCK_RC_12MHZ
| #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) |
Definition at line 605 of file same70j21b.h.
◆ CHIP_FREQ_MAINCK_RC_4MHZ
| #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) |
Definition at line 603 of file same70j21b.h.
◆ CHIP_FREQ_MAINCK_RC_8MHZ
| #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) |
Definition at line 604 of file same70j21b.h.
◆ CHIP_FREQ_SLCK_RC
| #define CHIP_FREQ_SLCK_RC (32000UL) |
Definition at line 601 of file same70j21b.h.
◆ CHIP_FREQ_SLCK_RC_MAX
| #define CHIP_FREQ_SLCK_RC_MAX (44000UL) |
Definition at line 602 of file same70j21b.h.
◆ CHIP_FREQ_SLCK_RC_MIN
| #define CHIP_FREQ_SLCK_RC_MIN (20000UL) |
Definition at line 600 of file same70j21b.h.
◆ CHIP_FREQ_XTAL_12M
| #define CHIP_FREQ_XTAL_12M (12000000UL) |
Definition at line 608 of file same70j21b.h.
◆ CHIP_FREQ_XTAL_32K
| #define CHIP_FREQ_XTAL_32K (32768UL) |
Definition at line 607 of file same70j21b.h.
◆ CHIP_JTAGID
| #define CHIP_JTAGID (0x05B3D03FUL) |
Definition at line 589 of file same70j21b.h.
◆ DTCM_ADDR
| #define DTCM_ADDR (0x20000000u) |
Data Tightly Coupled Memory base address
Definition at line 577 of file same70j21b.h.
◆ EBI_CS0_ADDR
| #define EBI_CS0_ADDR (0x60000000u) |
EBI Chip Select 0 base address
Definition at line 579 of file same70j21b.h.
◆ EBI_CS1_ADDR
| #define EBI_CS1_ADDR (0x61000000u) |
EBI Chip Select 1 base address
Definition at line 580 of file same70j21b.h.
◆ EBI_CS2_ADDR
| #define EBI_CS2_ADDR (0x62000000u) |
EBI Chip Select 2 base address
Definition at line 581 of file same70j21b.h.
◆ EBI_CS3_ADDR
| #define EBI_CS3_ADDR (0x63000000u) |
EBI Chip Select 3 base address
Definition at line 582 of file same70j21b.h.
◆ IFLASH_ADDR
| #define IFLASH_ADDR (0x00400000u) |
Internal Flash base address
Definition at line 575 of file same70j21b.h.
◆ IFLASH_LOCK_REGION_SIZE
| #define IFLASH_LOCK_REGION_SIZE (8192u) |
Definition at line 567 of file same70j21b.h.
◆ IFLASH_NB_OF_LOCK_BITS
| #define IFLASH_NB_OF_LOCK_BITS (128u) |
Definition at line 569 of file same70j21b.h.
◆ IFLASH_NB_OF_PAGES
| #define IFLASH_NB_OF_PAGES (4096u) |
Definition at line 568 of file same70j21b.h.
◆ IFLASH_PAGE_SIZE
| #define IFLASH_PAGE_SIZE (512u) |
Definition at line 566 of file same70j21b.h.
◆ IFLASH_SIZE
| #define IFLASH_SIZE (0x200000u) |
Definition at line 565 of file same70j21b.h.
◆ IRAM_ADDR
| #define IRAM_ADDR (0x20400000u) |
Internal RAM base address
Definition at line 578 of file same70j21b.h.
◆ IRAM_SIZE
| #define IRAM_SIZE (0x60000u) |
Definition at line 570 of file same70j21b.h.
◆ IROM_ADDR
| #define IROM_ADDR (0x00800000u) |
Internal ROM base address
Definition at line 576 of file same70j21b.h.
◆ ITCM_ADDR
| #define ITCM_ADDR (0x00000000u) |
Instruction Tightly Coupled Memory base address
Definition at line 574 of file same70j21b.h.
◆ QSPIMEM_ADDR
| #define QSPIMEM_ADDR (0x80000000u) |
QSPI Memory base address
Definition at line 572 of file same70j21b.h.
◆ SDRAM_CS_ADDR
| #define SDRAM_CS_ADDR (0x70000000u) |
SDRAM Chip Select base address
Definition at line 583 of file same70j21b.h.