drivers/tc/tc.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef TC_H_INCLUDED
38 #define TC_H_INCLUDED
39 
126 #include <compiler.h>
127 
129 
130 #ifdef __cplusplus
131 extern "C" {
132 #endif
133 
134 
136 void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode);
137 void tc_sync_trigger(Tc *p_tc);
138 void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode);
139 
140 #if (!SAM3U) || defined(__DOXYGEN__)
141 uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel,
142  uint32_t ul_steppermode);
143 #endif /* (!SAM3U) || defined(__DOXYGEN__) */
144 
145 void tc_start(Tc *p_tc, uint32_t ul_channel);
146 void tc_stop(Tc *p_tc, uint32_t ul_channel);
147 
148 uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel);
149 uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel);
150 uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel);
151 uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel);
152 
153 void tc_write_ra(Tc *p_tc, uint32_t ul_channel,
154  uint32_t ul_value);
155 void tc_write_rb(Tc *p_tc, uint32_t ul_channel,
156  uint32_t ul_value);
157 void tc_write_rc(Tc *p_tc, uint32_t ul_channel,
158  uint32_t ul_value);
159 
160 uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck,
161  uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck);
162 void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel,
163  uint32_t ul_sources);
164 void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel,
165  uint32_t ul_sources);
166 uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel);
167 uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel);
168 #if (!SAM4L && !SAMG) || defined(__DOXYGEN__)
169 void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources);
170 void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources);
171 uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc);
172 uint32_t tc_get_qdec_interrupt_status(Tc *p_tc);
173 #endif /* (!SAM4L && !SAMG) || defined(__DOXYGEN__) */
174 
175 #if (!SAM3U)
176 void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable);
177 #endif /* (!SAM3U) */
178 
179 #if SAM4L || defined(__DOXYGEN__)
180 uint32_t tc_get_feature(Tc *p_tc);
181 uint32_t tc_get_version(Tc *p_tc);
182 #endif /* SAM4L || defined(__DOXYGEN__) */
183 
185 
186 #ifdef __cplusplus
187 }
188 #endif
189 
190 
445 #endif /* TC_H_INCLUDED */
void tc_write_rc(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register C (RC) on the selected channel.
Definition: tc.c:326
uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel)
Read TC Register B (RB) on the specified channel.
Definition: tc.c:247
uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc)
Read TC QDEC interrupt mask.
Definition: tc.c:665
void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
Disable TC QDEC interrupts.
Definition: tc.c:646
void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable)
Enable or disable write protection of TC registers.
Definition: tc.c:704
void tc_stop(Tc *p_tc, uint32_t ul_channel)
Stop the TC clock on the specified channel.
Definition: tc.c:187
void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, uint32_t ul_sources)
Disable TC interrupts on the specified channel.
Definition: tc.c:400
uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel)
Read the counter value on the specified channel.
Definition: tc.c:207
void tc_write_rb(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register B (RB) on the specified channel.
Definition: tc.c:306
void tc_start(Tc *p_tc, uint32_t ul_channel)
Start the TC clock on the specified channel.
Definition: tc.c:169
Commonly used includes, types and macros.
void tc_sync_trigger(Tc *p_tc)
Asserts a SYNC signal to generate a software trigger on all channels.
Definition: tc.c:103
void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode)
Configure TC for timer, waveform generation, or capture.
Definition: tc.c:70
uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel)
Read TC Register A (RA) on the specified channel.
Definition: tc.c:227
uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel)
Read the TC interrupt mask for the specified channel.
Definition: tc.c:423
uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel)
Get the current status for the specified TC channel.
Definition: tc.c:445
void tc_write_ra(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register A (RA) on the specified channel.
Definition: tc.c:286
uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck)
Find the best MCK divisor.
Definition: tc.c:487
uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel)
Read TC Register C (RC) on the specified channel.
Definition: tc.c:267
void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, uint32_t ul_sources)
Enable the TC interrupts on the specified channel.
Definition: tc.c:362
void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
Enable TC QDEC interrupts.
Definition: tc.c:617
uint32_t tc_get_qdec_interrupt_status(Tc *p_tc)
Get current TC QDEC interrupt status.
Definition: tc.c:683
void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode)
Configure the TC Block mode.
Definition: tc.c:123
uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, uint32_t ul_steppermode)
Configure TC for 2-bit Gray Counter for Stepper Motor.
Definition: tc.c:147


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05