core_cm7_4p30.h
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1 #ifndef __CORE_CM7_4_30_H
2 #define __CORE_CM7_4_30_H
3 
4 #ifdef __cplusplus
5 extern "C" {
6 #endif
7 
8 #include "board_opt.h"
9 
16 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
17 {
18  #if (__DCACHE_PRESENT == 1U) && (CONF_BOARD_ENABLE_DCACHE==1)
19  int32_t op_size = dsize;
20  uint32_t op_addr = (uint32_t)addr;
21  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
22 
23  __DSB();
24 
25  while (op_size > 0) {
26 #if (__CM7_CMSIS_VERSION_SUB == 0x00)
27  SCB->DCIMVAU = op_addr; // 4.00 typo
28 #else
29  SCB->DCIMVAC = op_addr;
30 #endif // (__CM7_CMSIS_VERSION_SUB == 0x00)
31  op_addr += linesize;
32  op_size -= linesize;
33  }
34 
35  __DSB();
36  __ISB();
37  #endif
38 }
39 
40 
47 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
48 {
49  #if (__DCACHE_PRESENT == 1) && (CONF_BOARD_ENABLE_DCACHE==1)
50  int32_t op_size = dsize;
51  uint32_t op_addr = (uint32_t) addr;
52  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
53 
54  __DSB();
55 
56  while (op_size > 0) {
57  SCB->DCCMVAC = op_addr;
58  op_addr += linesize;
59  op_size -= linesize;
60  }
61 
62  __DSB();
63  __ISB();
64  #endif
65 }
66 
67 
74 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
75 {
76  #if (__DCACHE_PRESENT == 1U) && (CONF_BOARD_ENABLE_DCACHE==1)
77  int32_t op_size = dsize;
78  uint32_t op_addr = (uint32_t) addr;
79  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
80 
81  __DSB();
82 
83  while (op_size > 0) {
84  SCB->DCCIMVAC = op_addr;
85  op_addr += linesize;
86  op_size -= linesize;
87  }
88 
89  __DSB();
90  __ISB();
91  #endif
92 }
93 
94 #if CONF_BOARD_ENABLE_DCACHE == 1
95  // move address back until it is 32 byte aligned, add to size the amount that address was moved back
96  #define SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) SCB_CleanInvalidateDCache_by_Addr((uint32_t*)(((uint32_t)(addr))&0xFFFFFFE0), (size) + (((uint32_t)(addr))&0x0000001F))
97  //This one can be unsafe
98  //#define SCB_INVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)(addr))&0xFFFFFFE0), (size) + (((uint32_t)(addr))&0x0000001F))
99  #define SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size) SCB_CleanDCache_by_Addr((uint32_t*)(((uint32_t)(addr))&0xFFFFFFE0), (size) + (((uint32_t)(addr))&0x0000001F))
100 #else
101  #define SCB_CLEANINVALIDATE_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size)
102  #define SCB_CLEAN_DCACHE_BY_ADDR_32BYTE_ALIGNED(addr,size)
103 #endif
104 
105 #ifdef __cplusplus
106 }
107 #endif
108 #endif // __CORE_CM7_4_30_H
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: core_cm7_4p30.h:16
__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean by address.
Definition: core_cm7_4p30.h:47
#define SCB
Definition: core_cm7.h:1599
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: core_cm7_4p30.h:74


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04