component/smc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_SMC_COMPONENT_
36 #define _SAME70_SMC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __IO uint32_t SMC_SETUP;
48  __IO uint32_t SMC_PULSE;
49  __IO uint32_t SMC_CYCLE;
50  __IO uint32_t SMC_MODE;
51 } SmcCs_number;
53 #define SMCCS_NUMBER_NUMBER 4
54 typedef struct {
56  __I uint32_t Reserved1[16];
57  __IO uint32_t SMC_OCMS;
58  __O uint32_t SMC_KEY1;
59  __O uint32_t SMC_KEY2;
60  __I uint32_t Reserved2[22];
61  __IO uint32_t SMC_WPMR;
62  __I uint32_t SMC_WPSR;
63  __I uint32_t Reserved3[4];
64  __I uint32_t SMC_VERSION;
65 } Smc;
66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
67 /* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
68 #define SMC_SETUP_NWE_SETUP_Pos 0
69 #define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos)
70 #define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
71 #define SMC_SETUP_NCS_WR_SETUP_Pos 8
72 #define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos)
73 #define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
74 #define SMC_SETUP_NRD_SETUP_Pos 16
75 #define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos)
76 #define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
77 #define SMC_SETUP_NCS_RD_SETUP_Pos 24
78 #define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos)
79 #define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
80 /* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
81 #define SMC_PULSE_NWE_PULSE_Pos 0
82 #define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos)
83 #define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
84 #define SMC_PULSE_NCS_WR_PULSE_Pos 8
85 #define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos)
86 #define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
87 #define SMC_PULSE_NRD_PULSE_Pos 16
88 #define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos)
89 #define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
90 #define SMC_PULSE_NCS_RD_PULSE_Pos 24
91 #define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos)
92 #define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
93 /* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
94 #define SMC_CYCLE_NWE_CYCLE_Pos 0
95 #define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos)
96 #define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
97 #define SMC_CYCLE_NRD_CYCLE_Pos 16
98 #define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos)
99 #define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
100 /* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */
101 #define SMC_MODE_READ_MODE (0x1u << 0)
102 #define SMC_MODE_WRITE_MODE (0x1u << 1)
103 #define SMC_MODE_EXNW_MODE_Pos 4
104 #define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos)
105 #define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)))
106 #define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4)
107 #define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4)
108 #define SMC_MODE_EXNW_MODE_READY (0x3u << 4)
109 #define SMC_MODE_BAT (0x1u << 8)
110 #define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8)
111 #define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8)
112 #define SMC_MODE_DBW (0x1u << 12)
113 #define SMC_MODE_DBW_8_BIT (0x0u << 12)
114 #define SMC_MODE_DBW_16_BIT (0x1u << 12)
115 #define SMC_MODE_TDF_CYCLES_Pos 16
116 #define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos)
117 #define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
118 #define SMC_MODE_TDF_MODE (0x1u << 20)
119 #define SMC_MODE_PMEN (0x1u << 24)
120 #define SMC_MODE_PS_Pos 28
121 #define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos)
122 #define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)))
123 #define SMC_MODE_PS_4_BYTE (0x0u << 28)
124 #define SMC_MODE_PS_8_BYTE (0x1u << 28)
125 #define SMC_MODE_PS_16_BYTE (0x2u << 28)
126 #define SMC_MODE_PS_32_BYTE (0x3u << 28)
127 /* -------- SMC_OCMS : (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register -------- */
128 #define SMC_OCMS_SMSE (0x1u << 0)
129 #define SMC_OCMS_CS0SE (0x1u << 8)
130 #define SMC_OCMS_CS1SE (0x1u << 9)
131 #define SMC_OCMS_CS2SE (0x1u << 10)
132 #define SMC_OCMS_CS3SE (0x1u << 11)
133 /* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register -------- */
134 #define SMC_KEY1_KEY1_Pos 0
135 #define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos)
136 #define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
137 /* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register -------- */
138 #define SMC_KEY2_KEY2_Pos 0
139 #define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos)
140 #define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
141 /* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */
142 #define SMC_WPMR_WPEN (0x1u << 0)
143 #define SMC_WPMR_WPKEY_Pos 8
144 #define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos)
145 #define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
146 #define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8)
147 /* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */
148 #define SMC_WPSR_WPVS (0x1u << 0)
149 #define SMC_WPSR_WPVSRC_Pos 8
150 #define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos)
151 /* -------- SMC_VERSION : (SMC Offset: 0xFC) SMC Version Register -------- */
152 #define SMC_VERSION_VERSION_Pos 0
153 #define SMC_VERSION_VERSION_Msk (0xfffu << SMC_VERSION_VERSION_Pos)
154 #define SMC_VERSION_MFN_Pos 16
155 #define SMC_VERSION_MFN_Msk (0x7u << SMC_VERSION_MFN_Pos)
158 
159 
160 #endif /* _SAME70_SMC_COMPONENT_ */
__O uint32_t SMC_KEY2
(Smc Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register
Definition: component/smc.h:59
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__IO uint32_t SMC_CYCLE
(SmcCs_number Offset: 0x8) SMC Cycle Register
Definition: component/smc.h:49
__I uint32_t SMC_VERSION
(Smc Offset: 0xFC) SMC Version Register
Definition: component/smc.h:64
__IO uint32_t SMC_SETUP
(SmcCs_number Offset: 0x0) SMC Setup Register
Definition: component/smc.h:47
__IO uint32_t SMC_OCMS
(Smc Offset: 0x80) SMC Off-Chip Memory Scrambling Register
Definition: component/smc.h:57
__I uint32_t SMC_WPSR
(Smc Offset: 0xE8) SMC Write Protection Status Register
Definition: component/smc.h:62
__IO uint32_t SMC_PULSE
(SmcCs_number Offset: 0x4) SMC Pulse Register
Definition: component/smc.h:48
#define SMCCS_NUMBER_NUMBER
Smc hardware registers.
Definition: component/smc.h:53
SmcCs_number hardware registers.
Definition: component/smc.h:46
__IO uint32_t SMC_WPMR
(Smc Offset: 0xE4) SMC Write Protection Mode Register
Definition: component/smc.h:61
__IO uint32_t SMC_MODE
(SmcCs_number Offset: 0xC) SMC MODE Register
Definition: component/smc.h:50
__O uint32_t SMC_KEY1
(Smc Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register
Definition: component/smc.h:58
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05