component/sdramc.h
Go to the documentation of this file.
1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_SDRAMC_COMPONENT_
36 #define _SAME70_SDRAMC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __IO uint32_t SDRAMC_MR;
48  __IO uint32_t SDRAMC_TR;
49  __IO uint32_t SDRAMC_CR;
50  __I uint32_t Reserved1[1];
51  __IO uint32_t SDRAMC_LPR;
52  __O uint32_t SDRAMC_IER;
53  __O uint32_t SDRAMC_IDR;
54  __I uint32_t SDRAMC_IMR;
55  __I uint32_t SDRAMC_ISR;
56  __IO uint32_t SDRAMC_MDR;
57  __IO uint32_t SDRAMC_CFR1;
58  __IO uint32_t SDRAMC_OCMS;
59  __O uint32_t SDRAMC_OCMS_KEY1;
60  __O uint32_t SDRAMC_OCMS_KEY2;
61  __I uint32_t Reserved2[49];
62  __I uint32_t SDRAMC_VERSION;
63 } Sdramc;
64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
65 /* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
66 #define SDRAMC_MR_MODE_Pos 0
67 #define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos)
68 #define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)))
69 #define SDRAMC_MR_MODE_NORMAL (0x0u << 0)
70 #define SDRAMC_MR_MODE_NOP (0x1u << 0)
71 #define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0)
72 #define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0)
73 #define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0)
74 #define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0)
75 #define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0)
76 /* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
77 #define SDRAMC_TR_COUNT_Pos 0
78 #define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos)
79 #define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
80 /* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
81 #define SDRAMC_CR_NC_Pos 0
82 #define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos)
83 #define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)))
84 #define SDRAMC_CR_NC_COL8 (0x0u << 0)
85 #define SDRAMC_CR_NC_COL9 (0x1u << 0)
86 #define SDRAMC_CR_NC_COL10 (0x2u << 0)
87 #define SDRAMC_CR_NC_COL11 (0x3u << 0)
88 #define SDRAMC_CR_NR_Pos 2
89 #define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos)
90 #define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)))
91 #define SDRAMC_CR_NR_ROW11 (0x0u << 2)
92 #define SDRAMC_CR_NR_ROW12 (0x1u << 2)
93 #define SDRAMC_CR_NR_ROW13 (0x2u << 2)
94 #define SDRAMC_CR_NB (0x1u << 4)
95 #define SDRAMC_CR_NB_BANK2 (0x0u << 4)
96 #define SDRAMC_CR_NB_BANK4 (0x1u << 4)
97 #define SDRAMC_CR_CAS_Pos 5
98 #define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos)
99 #define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)))
100 #define SDRAMC_CR_CAS_LATENCY1 (0x1u << 5)
101 #define SDRAMC_CR_CAS_LATENCY2 (0x2u << 5)
102 #define SDRAMC_CR_CAS_LATENCY3 (0x3u << 5)
103 #define SDRAMC_CR_DBW (0x1u << 7)
104 #define SDRAMC_CR_TWR_Pos 8
105 #define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos)
106 #define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
107 #define SDRAMC_CR_TRC_TRFC_Pos 12
108 #define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos)
109 #define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
110 #define SDRAMC_CR_TRP_Pos 16
111 #define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos)
112 #define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
113 #define SDRAMC_CR_TRCD_Pos 20
114 #define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos)
115 #define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
116 #define SDRAMC_CR_TRAS_Pos 24
117 #define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos)
118 #define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
119 #define SDRAMC_CR_TXSR_Pos 28
120 #define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos)
121 #define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
122 /* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
123 #define SDRAMC_LPR_LPCB_Pos 0
124 #define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos)
125 #define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)))
126 #define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0)
127 #define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0)
128 #define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0)
129 #define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0)
130 #define SDRAMC_LPR_PASR_Pos 4
131 #define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos)
132 #define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
133 #define SDRAMC_LPR_TCSR_Pos 8
134 #define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos)
135 #define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
136 #define SDRAMC_LPR_DS_Pos 10
137 #define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos)
138 #define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
139 #define SDRAMC_LPR_TIMEOUT_Pos 12
140 #define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos)
141 #define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)))
142 #define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12)
143 #define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12)
144 #define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12)
145 /* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
146 #define SDRAMC_IER_RES (0x1u << 0)
147 /* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
148 #define SDRAMC_IDR_RES (0x1u << 0)
149 /* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
150 #define SDRAMC_IMR_RES (0x1u << 0)
151 /* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
152 #define SDRAMC_ISR_RES (0x1u << 0)
153 /* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
154 #define SDRAMC_MDR_MD_Pos 0
155 #define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos)
156 #define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)))
157 #define SDRAMC_MDR_MD_SDRAM (0x0u << 0)
158 #define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0)
159 /* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
160 #define SDRAMC_CFR1_TMRD_Pos 0
161 #define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos)
162 #define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)))
163 #define SDRAMC_CFR1_UNAL (0x1u << 8)
164 #define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8)
165 #define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8)
166 /* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */
167 #define SDRAMC_OCMS_SDR_SE (0x1u << 0)
168 /* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */
169 #define SDRAMC_OCMS_KEY1_KEY1_Pos 0
170 #define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos)
171 #define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)))
172 /* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */
173 #define SDRAMC_OCMS_KEY2_KEY2_Pos 0
174 #define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos)
175 #define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)))
176 /* -------- SDRAMC_VERSION : (SDRAMC Offset: 0xFC) SDRAMC Version Register -------- */
177 #define SDRAMC_VERSION_VERSION_Pos 0
178 #define SDRAMC_VERSION_VERSION_Msk (0xfffu << SDRAMC_VERSION_VERSION_Pos)
179 #define SDRAMC_VERSION_MFN_Pos 16
180 #define SDRAMC_VERSION_MFN_Msk (0x7u << SDRAMC_VERSION_MFN_Pos)
183 
184 
185 #endif /* _SAME70_SDRAMC_COMPONENT_ */
Sdramc
Sdramc hardware registers.
Definition: component/sdramc.h:46
__IO
#define __IO
Definition: core_cm7.h:266
__O
#define __O
Definition: core_cm7.h:265
Sdramc::SDRAMC_OCMS
__IO uint32_t SDRAMC_OCMS
(Sdramc Offset: 0x2C) SDRAMC OCMS Register
Definition: component/sdramc.h:58
Sdramc::SDRAMC_CFR1
__IO uint32_t SDRAMC_CFR1
(Sdramc Offset: 0x28) SDRAMC Configuration Register 1
Definition: component/sdramc.h:57
Sdramc::SDRAMC_CR
__IO uint32_t SDRAMC_CR
(Sdramc Offset: 0x08) SDRAMC Configuration Register
Definition: component/sdramc.h:49
Sdramc::SDRAMC_IMR
__I uint32_t SDRAMC_IMR
(Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register
Definition: component/sdramc.h:54
Sdramc::SDRAMC_IDR
__O uint32_t SDRAMC_IDR
(Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register
Definition: component/sdramc.h:53
Sdramc::SDRAMC_MDR
__IO uint32_t SDRAMC_MDR
(Sdramc Offset: 0x24) SDRAMC Memory Device Register
Definition: component/sdramc.h:56
Sdramc::SDRAMC_MR
__IO uint32_t SDRAMC_MR
(Sdramc Offset: 0x00) SDRAMC Mode Register
Definition: component/sdramc.h:47
Sdramc::SDRAMC_OCMS_KEY2
__O uint32_t SDRAMC_OCMS_KEY2
(Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register
Definition: component/sdramc.h:60
Sdramc::SDRAMC_VERSION
__I uint32_t SDRAMC_VERSION
(Sdramc Offset: 0xFC) SDRAMC Version Register
Definition: component/sdramc.h:62
Sdramc::SDRAMC_OCMS_KEY1
__O uint32_t SDRAMC_OCMS_KEY1
(Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register
Definition: component/sdramc.h:59
Sdramc::SDRAMC_IER
__O uint32_t SDRAMC_IER
(Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register
Definition: component/sdramc.h:52
Sdramc::SDRAMC_LPR
__IO uint32_t SDRAMC_LPR
(Sdramc Offset: 0x10) SDRAMC Low Power Register
Definition: component/sdramc.h:51
Sdramc::SDRAMC_ISR
__I uint32_t SDRAMC_ISR
(Sdramc Offset: 0x20) SDRAMC Interrupt Status Register
Definition: component/sdramc.h:55
__I
#define __I
Definition: core_cm7.h:263
Sdramc::SDRAMC_TR
__IO uint32_t SDRAMC_TR
(Sdramc Offset: 0x04) SDRAMC Refresh Timer Register
Definition: component/sdramc.h:48

inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:05