component/acc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_ACC_COMPONENT_
36 #define _SAME70_ACC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t ACC_CR;
48  __IO uint32_t ACC_MR;
49  __I uint32_t Reserved1[7];
50  __O uint32_t ACC_IER;
51  __O uint32_t ACC_IDR;
52  __I uint32_t ACC_IMR;
53  __I uint32_t ACC_ISR;
54  __I uint32_t Reserved2[24];
55  __IO uint32_t ACC_ACR;
56  __I uint32_t Reserved3[19];
57  __IO uint32_t ACC_WPMR;
58  __I uint32_t ACC_WPSR;
59  __I uint32_t Reserved4[4];
60  __I uint32_t ACC_VER;
61 } Acc;
62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
63 /* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
64 #define ACC_CR_SWRST (0x1u << 0)
65 /* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
66 #define ACC_MR_SELMINUS_Pos 0
67 #define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos)
68 #define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
69 #define ACC_MR_SELMINUS_TS (0x0u << 0)
70 #define ACC_MR_SELMINUS_ADVREFP (0x1u << 0)
71 #define ACC_MR_SELMINUS_VREFP (0x1u << 0)
72 #define ACC_MR_SELMINUS_DAC0 (0x2u << 0)
73 #define ACC_MR_SELMINUS_DAC1 (0x3u << 0)
74 #define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0)
75 #define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0)
76 #define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0)
77 #define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0)
78 #define ACC_MR_SELPLUS_Pos 4
79 #define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos)
80 #define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
81 #define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4)
82 #define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4)
83 #define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4)
84 #define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4)
85 #define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4)
86 #define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4)
87 #define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4)
88 #define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4)
89 #define ACC_MR_ACEN (0x1u << 8)
90 #define ACC_MR_ACEN_DIS (0x0u << 8)
91 #define ACC_MR_ACEN_EN (0x1u << 8)
92 #define ACC_MR_EDGETYP_Pos 9
93 #define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos)
94 #define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
95 #define ACC_MR_EDGETYP_RISING (0x0u << 9)
96 #define ACC_MR_EDGETYP_FALLING (0x1u << 9)
97 #define ACC_MR_EDGETYP_ANY (0x2u << 9)
98 #define ACC_MR_INV (0x1u << 12)
99 #define ACC_MR_INV_DIS (0x0u << 12)
100 #define ACC_MR_INV_EN (0x1u << 12)
101 #define ACC_MR_SELFS (0x1u << 13)
102 #define ACC_MR_SELFS_CE (0x0u << 13)
103 #define ACC_MR_SELFS_OUTPUT (0x1u << 13)
104 #define ACC_MR_FE (0x1u << 14)
105 #define ACC_MR_FE_DIS (0x0u << 14)
106 #define ACC_MR_FE_EN (0x1u << 14)
107 /* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
108 #define ACC_IER_CE (0x1u << 0)
109 /* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
110 #define ACC_IDR_CE (0x1u << 0)
111 /* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
112 #define ACC_IMR_CE (0x1u << 0)
113 /* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
114 #define ACC_ISR_CE (0x1u << 0)
115 #define ACC_ISR_SCO (0x1u << 1)
116 #define ACC_ISR_MASK (0x1u << 31)
117 /* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
118 #define ACC_ACR_ISEL (0x1u << 0)
119 #define ACC_ACR_ISEL_LOPW (0x0u << 0)
120 #define ACC_ACR_ISEL_HISP (0x1u << 0)
121 #define ACC_ACR_HYST_Pos 1
122 #define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos)
123 #define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
124 /* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
125 #define ACC_WPMR_WPEN (0x1u << 0)
126 #define ACC_WPMR_WPKEY_Pos 8
127 #define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos)
128 #define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
129 #define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8)
130 /* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
131 #define ACC_WPSR_WPVS (0x1u << 0)
132 /* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */
133 #define ACC_VER_VERSION_Pos 0
134 #define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos)
135 #define ACC_VER_MFN_Pos 16
136 #define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos)
139 
140 
141 #endif /* _SAME70_ACC_COMPONENT_ */
__O uint32_t ACC_IER
(Acc Offset: 0x24) Interrupt Enable Register
Definition: component/acc.h:50
__I uint32_t ACC_IMR
(Acc Offset: 0x2C) Interrupt Mask Register
Definition: component/acc.h:52
#define __IO
Definition: core_cm7.h:266
__I uint32_t ACC_WPSR
(Acc Offset: 0xE8) Write Protection Status Register
Definition: component/acc.h:58
#define __O
Definition: core_cm7.h:265
__I uint32_t ACC_VER
(Acc Offset: 0xFC) Version Register
Definition: component/acc.h:60
__IO uint32_t ACC_ACR
(Acc Offset: 0x94) Analog Control Register
Definition: component/acc.h:55
__IO uint32_t ACC_MR
(Acc Offset: 0x04) Mode Register
Definition: component/acc.h:48
__I uint32_t ACC_ISR
(Acc Offset: 0x30) Interrupt Status Register
Definition: component/acc.h:53
Acc hardware registers.
Definition: component/acc.h:46
__O uint32_t ACC_CR
(Acc Offset: 0x00) Control Register
Definition: component/acc.h:47
#define __I
Definition: core_cm7.h:263
__O uint32_t ACC_IDR
(Acc Offset: 0x28) Interrupt Disable Register
Definition: component/acc.h:51
__IO uint32_t ACC_WPMR
(Acc Offset: 0xE4) Write Protection Mode Register
Definition: component/acc.h:57


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:18:13