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21 #ifndef STM32H7xx_HAL_DMA_H
22 #define STM32H7xx_HAL_DMA_H
64 uint32_t PeriphDataAlignment;
67 uint32_t MemDataAlignment;
83 uint32_t FIFOThreshold;
198 #define HAL_DMA_ERROR_NONE (0x00000000U)
199 #define HAL_DMA_ERROR_TE (0x00000001U)
200 #define HAL_DMA_ERROR_FE (0x00000002U)
201 #define HAL_DMA_ERROR_DME (0x00000004U)
202 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U)
203 #define HAL_DMA_ERROR_PARAM (0x00000040U)
204 #define HAL_DMA_ERROR_NO_XFER (0x00000080U)
205 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)
206 #define HAL_DMA_ERROR_SYNC (0x00000200U)
207 #define HAL_DMA_ERROR_REQGEN (0x00000400U)
208 #define HAL_DMA_ERROR_BUSY (0x00000800U)
219 #define DMA_REQUEST_MEM2MEM 0U
221 #define DMA_REQUEST_GENERATOR0 1U
222 #define DMA_REQUEST_GENERATOR1 2U
223 #define DMA_REQUEST_GENERATOR2 3U
224 #define DMA_REQUEST_GENERATOR3 4U
225 #define DMA_REQUEST_GENERATOR4 5U
226 #define DMA_REQUEST_GENERATOR5 6U
227 #define DMA_REQUEST_GENERATOR6 7U
228 #define DMA_REQUEST_GENERATOR7 8U
230 #define DMA_REQUEST_ADC1 9U
231 #define DMA_REQUEST_ADC2 10U
233 #define DMA_REQUEST_TIM1_CH1 11U
234 #define DMA_REQUEST_TIM1_CH2 12U
235 #define DMA_REQUEST_TIM1_CH3 13U
236 #define DMA_REQUEST_TIM1_CH4 14U
237 #define DMA_REQUEST_TIM1_UP 15U
238 #define DMA_REQUEST_TIM1_TRIG 16U
239 #define DMA_REQUEST_TIM1_COM 17U
241 #define DMA_REQUEST_TIM2_CH1 18U
242 #define DMA_REQUEST_TIM2_CH2 19U
243 #define DMA_REQUEST_TIM2_CH3 20U
244 #define DMA_REQUEST_TIM2_CH4 21U
245 #define DMA_REQUEST_TIM2_UP 22U
247 #define DMA_REQUEST_TIM3_CH1 23U
248 #define DMA_REQUEST_TIM3_CH2 24U
249 #define DMA_REQUEST_TIM3_CH3 25U
250 #define DMA_REQUEST_TIM3_CH4 26U
251 #define DMA_REQUEST_TIM3_UP 27U
252 #define DMA_REQUEST_TIM3_TRIG 28U
254 #define DMA_REQUEST_TIM4_CH1 29U
255 #define DMA_REQUEST_TIM4_CH2 30U
256 #define DMA_REQUEST_TIM4_CH3 31U
257 #define DMA_REQUEST_TIM4_UP 32U
259 #define DMA_REQUEST_I2C1_RX 33U
260 #define DMA_REQUEST_I2C1_TX 34U
261 #define DMA_REQUEST_I2C2_RX 35U
262 #define DMA_REQUEST_I2C2_TX 36U
264 #define DMA_REQUEST_SPI1_RX 37U
265 #define DMA_REQUEST_SPI1_TX 38U
266 #define DMA_REQUEST_SPI2_RX 39U
267 #define DMA_REQUEST_SPI2_TX 40U
269 #define DMA_REQUEST_USART1_RX 41U
270 #define DMA_REQUEST_USART1_TX 42U
271 #define DMA_REQUEST_USART2_RX 43U
272 #define DMA_REQUEST_USART2_TX 44U
273 #define DMA_REQUEST_USART3_RX 45U
274 #define DMA_REQUEST_USART3_TX 46U
276 #define DMA_REQUEST_TIM8_CH1 47U
277 #define DMA_REQUEST_TIM8_CH2 48U
278 #define DMA_REQUEST_TIM8_CH3 49U
279 #define DMA_REQUEST_TIM8_CH4 50U
280 #define DMA_REQUEST_TIM8_UP 51U
281 #define DMA_REQUEST_TIM8_TRIG 52U
282 #define DMA_REQUEST_TIM8_COM 53U
284 #define DMA_REQUEST_TIM5_CH1 55U
285 #define DMA_REQUEST_TIM5_CH2 56U
286 #define DMA_REQUEST_TIM5_CH3 57U
287 #define DMA_REQUEST_TIM5_CH4 58U
288 #define DMA_REQUEST_TIM5_UP 59U
289 #define DMA_REQUEST_TIM5_TRIG 60U
291 #define DMA_REQUEST_SPI3_RX 61U
292 #define DMA_REQUEST_SPI3_TX 62U
294 #define DMA_REQUEST_UART4_RX 63U
295 #define DMA_REQUEST_UART4_TX 64U
296 #define DMA_REQUEST_UART5_RX 65U
297 #define DMA_REQUEST_UART5_TX 66U
299 #define DMA_REQUEST_DAC1_CH1 67U
300 #define DMA_REQUEST_DAC1_CH2 68U
302 #define DMA_REQUEST_TIM6_UP 69U
303 #define DMA_REQUEST_TIM7_UP 70U
305 #define DMA_REQUEST_USART6_RX 71U
306 #define DMA_REQUEST_USART6_TX 72U
308 #define DMA_REQUEST_I2C3_RX 73U
309 #define DMA_REQUEST_I2C3_TX 74U
312 #define DMA_REQUEST_DCMI_PSSI 75U
313 #define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI
315 #define DMA_REQUEST_DCMI 75U
318 #define DMA_REQUEST_CRYP_IN 76U
319 #define DMA_REQUEST_CRYP_OUT 77U
321 #define DMA_REQUEST_HASH_IN 78U
323 #define DMA_REQUEST_UART7_RX 79U
324 #define DMA_REQUEST_UART7_TX 80U
325 #define DMA_REQUEST_UART8_RX 81U
326 #define DMA_REQUEST_UART8_TX 82U
328 #define DMA_REQUEST_SPI4_RX 83U
329 #define DMA_REQUEST_SPI4_TX 84U
330 #define DMA_REQUEST_SPI5_RX 85U
331 #define DMA_REQUEST_SPI5_TX 86U
333 #define DMA_REQUEST_SAI1_A 87U
334 #define DMA_REQUEST_SAI1_B 88U
337 #define DMA_REQUEST_SAI2_A 89U
338 #define DMA_REQUEST_SAI2_B 90U
341 #define DMA_REQUEST_SWPMI_RX 91U
342 #define DMA_REQUEST_SWPMI_TX 92U
344 #define DMA_REQUEST_SPDIF_RX_DT 93U
345 #define DMA_REQUEST_SPDIF_RX_CS 94U
348 #define DMA_REQUEST_HRTIM_MASTER 95U
349 #define DMA_REQUEST_HRTIM_TIMER_A 96U
350 #define DMA_REQUEST_HRTIM_TIMER_B 97U
351 #define DMA_REQUEST_HRTIM_TIMER_C 98U
352 #define DMA_REQUEST_HRTIM_TIMER_D 99U
353 #define DMA_REQUEST_HRTIM_TIMER_E 100U
356 #define DMA_REQUEST_DFSDM1_FLT0 101U
357 #define DMA_REQUEST_DFSDM1_FLT1 102U
358 #define DMA_REQUEST_DFSDM1_FLT2 103U
359 #define DMA_REQUEST_DFSDM1_FLT3 104U
361 #define DMA_REQUEST_TIM15_CH1 105U
362 #define DMA_REQUEST_TIM15_UP 106U
363 #define DMA_REQUEST_TIM15_TRIG 107U
364 #define DMA_REQUEST_TIM15_COM 108U
366 #define DMA_REQUEST_TIM16_CH1 109U
367 #define DMA_REQUEST_TIM16_UP 110U
369 #define DMA_REQUEST_TIM17_CH1 111U
370 #define DMA_REQUEST_TIM17_UP 112U
373 #define DMA_REQUEST_SAI3_A 113U
374 #define DMA_REQUEST_SAI3_B 114U
378 #define DMA_REQUEST_ADC3 115U
382 #define DMA_REQUEST_UART9_RX 116U
383 #define DMA_REQUEST_UART9_TX 117U
387 #define DMA_REQUEST_USART10_RX 118U
388 #define DMA_REQUEST_USART10_TX 119U
392 #define DMA_REQUEST_FMAC_READ 120U
393 #define DMA_REQUEST_FMAC_WRITE 121U
397 #define DMA_REQUEST_CORDIC_READ 122U
398 #define DMA_REQUEST_CORDIC_WRITE 123U
402 #define DMA_REQUEST_I2C5_RX 124U
403 #define DMA_REQUEST_I2C5_TX 125U
407 #define DMA_REQUEST_TIM23_CH1 126U
408 #define DMA_REQUEST_TIM23_CH2 127U
409 #define DMA_REQUEST_TIM23_CH3 128U
410 #define DMA_REQUEST_TIM23_CH4 129U
411 #define DMA_REQUEST_TIM23_UP 130U
412 #define DMA_REQUEST_TIM23_TRIG 131U
416 #define DMA_REQUEST_TIM24_CH1 132U
417 #define DMA_REQUEST_TIM24_CH2 133U
418 #define DMA_REQUEST_TIM24_CH3 134U
419 #define DMA_REQUEST_TIM24_CH4 135U
420 #define DMA_REQUEST_TIM24_UP 136U
421 #define DMA_REQUEST_TIM24_TRIG 137U
425 #define BDMA_REQUEST_MEM2MEM 0U
426 #define BDMA_REQUEST_GENERATOR0 1U
427 #define BDMA_REQUEST_GENERATOR1 2U
428 #define BDMA_REQUEST_GENERATOR2 3U
429 #define BDMA_REQUEST_GENERATOR3 4U
430 #define BDMA_REQUEST_GENERATOR4 5U
431 #define BDMA_REQUEST_GENERATOR5 6U
432 #define BDMA_REQUEST_GENERATOR6 7U
433 #define BDMA_REQUEST_GENERATOR7 8U
434 #define BDMA_REQUEST_LPUART1_RX 9U
435 #define BDMA_REQUEST_LPUART1_TX 10U
436 #define BDMA_REQUEST_SPI6_RX 11U
437 #define BDMA_REQUEST_SPI6_TX 12U
438 #define BDMA_REQUEST_I2C4_RX 13U
439 #define BDMA_REQUEST_I2C4_TX 14U
441 #define BDMA_REQUEST_SAI4_A 15U
442 #define BDMA_REQUEST_SAI4_B 16U
445 #define BDMA_REQUEST_ADC3 17U
448 #define BDMA_REQUEST_DAC2_CH1 17U
450 #if defined(DFSDM2_Channel0)
451 #define BDMA_REQUEST_DFSDM2_FLT0 18U
462 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
463 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
464 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
473 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
474 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U)
483 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
484 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U)
493 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
494 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
495 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
504 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
505 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
506 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
515 #define DMA_NORMAL ((uint32_t)0x00000000U)
516 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
517 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
518 #define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM)
519 #define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT))
528 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
529 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
530 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
531 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
540 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
541 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
550 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
551 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
552 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
553 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
562 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
563 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
564 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
565 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
574 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
575 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
576 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
577 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
586 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
587 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
588 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
589 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
590 #define DMA_IT_FE ((uint32_t)0x00000080U)
599 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)
600 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)
601 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
602 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
603 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
604 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
605 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
606 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
607 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
608 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
609 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
610 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
611 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
612 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
613 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
614 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
615 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
616 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
617 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
618 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
627 #define BDMA_FLAG_GL0 ((uint32_t)0x00000001)
628 #define BDMA_FLAG_TC0 ((uint32_t)0x00000002)
629 #define BDMA_FLAG_HT0 ((uint32_t)0x00000004)
630 #define BDMA_FLAG_TE0 ((uint32_t)0x00000008)
631 #define BDMA_FLAG_GL1 ((uint32_t)0x00000010)
632 #define BDMA_FLAG_TC1 ((uint32_t)0x00000020)
633 #define BDMA_FLAG_HT1 ((uint32_t)0x00000040)
634 #define BDMA_FLAG_TE1 ((uint32_t)0x00000080)
635 #define BDMA_FLAG_GL2 ((uint32_t)0x00000100)
636 #define BDMA_FLAG_TC2 ((uint32_t)0x00000200)
637 #define BDMA_FLAG_HT2 ((uint32_t)0x00000400)
638 #define BDMA_FLAG_TE2 ((uint32_t)0x00000800)
639 #define BDMA_FLAG_GL3 ((uint32_t)0x00001000)
640 #define BDMA_FLAG_TC3 ((uint32_t)0x00002000)
641 #define BDMA_FLAG_HT3 ((uint32_t)0x00004000)
642 #define BDMA_FLAG_TE3 ((uint32_t)0x00008000)
643 #define BDMA_FLAG_GL4 ((uint32_t)0x00010000)
644 #define BDMA_FLAG_TC4 ((uint32_t)0x00020000)
645 #define BDMA_FLAG_HT4 ((uint32_t)0x00040000)
646 #define BDMA_FLAG_TE4 ((uint32_t)0x00080000)
647 #define BDMA_FLAG_GL5 ((uint32_t)0x00100000)
648 #define BDMA_FLAG_TC5 ((uint32_t)0x00200000)
649 #define BDMA_FLAG_HT5 ((uint32_t)0x00400000)
650 #define BDMA_FLAG_TE5 ((uint32_t)0x00800000)
651 #define BDMA_FLAG_GL6 ((uint32_t)0x01000000)
652 #define BDMA_FLAG_TC6 ((uint32_t)0x02000000)
653 #define BDMA_FLAG_HT6 ((uint32_t)0x04000000)
654 #define BDMA_FLAG_TE6 ((uint32_t)0x08000000)
655 #define BDMA_FLAG_GL7 ((uint32_t)0x10000000)
656 #define BDMA_FLAG_TC7 ((uint32_t)0x20000000)
657 #define BDMA_FLAG_HT7 ((uint32_t)0x40000000)
658 #define BDMA_FLAG_TE7 ((uint32_t)0x80000000)
677 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
691 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
698 #define __HAL_DMA_ENABLE(__HANDLE__) \
699 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \
700 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))
707 #define __HAL_DMA_DISABLE(__HANDLE__) \
708 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \
709 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))
719 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
720 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
721 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
722 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
723 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
724 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
725 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
726 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
727 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
728 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
729 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
730 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
731 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
732 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
733 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
734 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
735 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
736 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\
737 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\
738 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\
739 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\
740 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\
741 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\
742 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\
743 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\
744 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\
745 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\
746 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\
747 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\
748 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\
749 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\
750 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\
751 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\
752 (uint32_t)0x00000000)
754 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
755 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
756 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
757 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
758 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
759 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
760 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
761 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
762 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
763 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
764 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
765 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
766 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
767 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
768 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
769 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
770 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
771 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\
772 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\
773 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\
774 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\
775 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\
776 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\
777 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\
778 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\
779 (uint32_t)0x00000000)
788 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
789 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
790 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
791 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
792 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
793 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
794 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
795 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
796 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
797 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
798 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
799 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
800 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
801 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
802 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
803 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
804 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
805 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\
806 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\
807 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\
808 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\
809 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\
810 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\
811 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\
812 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\
813 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\
814 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\
815 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\
816 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\
817 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\
818 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\
819 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\
820 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\
821 (uint32_t)0x00000000)
823 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
824 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
825 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
826 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
827 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
828 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
829 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
830 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
831 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
832 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
833 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
834 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
835 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
836 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
837 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
838 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
839 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
840 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\
841 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\
842 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\
843 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\
844 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\
845 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\
846 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\
847 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\
848 (uint32_t)0x00000000)
857 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
858 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
859 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
860 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
861 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
862 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
863 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
864 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
865 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
866 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
867 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
868 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
869 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
870 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
871 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
872 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
873 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
874 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\
875 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\
876 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\
877 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\
878 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\
879 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\
880 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\
881 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\
882 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\
883 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\
884 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\
885 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\
886 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\
887 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\
888 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\
889 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\
890 (uint32_t)0x00000000)
892 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
893 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
894 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
895 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
896 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
897 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
898 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
899 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
900 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
901 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
902 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
903 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
904 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
905 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
906 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
907 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
908 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
909 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\
910 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\
911 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\
912 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\
913 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\
914 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\
915 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\
916 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\
917 (uint32_t)0x00000000)
925 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
926 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
927 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
928 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
929 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
930 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
931 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
932 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
933 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
934 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
935 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
936 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
937 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
938 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
939 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
940 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
941 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
942 (uint32_t)0x00000000)
949 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
950 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
951 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
952 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
953 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
954 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
955 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
956 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
957 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
958 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
959 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
960 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
961 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
962 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
963 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
964 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
965 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
966 (uint32_t)0x00000000)
974 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
975 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
976 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
977 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
978 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
979 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
980 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
981 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
982 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
983 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
984 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
985 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
986 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
987 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
988 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
989 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
990 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
991 (uint32_t)0x00000000)
993 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
994 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
995 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
996 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
997 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
998 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
999 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
1000 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
1001 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
1002 (uint32_t)0x00000000)
1019 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1020 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\
1021 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\
1022 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\
1023 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\
1024 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1026 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1027 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\
1028 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
1029 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
1030 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1047 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1048 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
1049 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\
1050 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
1051 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
1052 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1054 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1055 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\
1056 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
1057 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
1058 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1061 #define DMA_TO_BDMA_IT(__DMA_IT__) \
1062 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
1063 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
1064 (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
1065 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\
1066 ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
1067 ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
1068 ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
1069 (uint32_t)0x00000000)
1072 #define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1073 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
1075 #define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1076 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
1090 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1091 (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1092 (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
1095 #define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
1097 #define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1098 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
1112 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1113 (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1114 (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
1117 #define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
1119 #define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1120 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
1121 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
1135 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1136 (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
1137 (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
1156 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1157 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
1158 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
1166 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1167 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
1168 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
1239 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG))
1241 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
1243 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
1247 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
1249 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
1252 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
1253 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
1254 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
1256 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
1258 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
1259 ((STATE) == DMA_PINC_DISABLE))
1261 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
1262 ((STATE) == DMA_MINC_DISABLE))
1264 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
1265 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
1266 ((SIZE) == DMA_PDATAALIGN_WORD))
1268 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
1269 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
1270 ((SIZE) == DMA_MDATAALIGN_WORD ))
1272 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
1273 ((MODE) == DMA_CIRCULAR) || \
1274 ((MODE) == DMA_PFCTRL) || \
1275 ((MODE) == DMA_DOUBLE_BUFFER_M0) || \
1276 ((MODE) == DMA_DOUBLE_BUFFER_M1))
1278 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
1279 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
1280 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
1281 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
1283 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
1284 ((STATE) == DMA_FIFOMODE_ENABLE))
1286 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
1287 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
1288 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
1289 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
1291 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
1292 ((BURST) == DMA_MBURST_INC4) || \
1293 ((BURST) == DMA_MBURST_INC8) || \
1294 ((BURST) == DMA_MBURST_INC16))
1296 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
1297 ((BURST) == DMA_PBURST_INC4) || \
1298 ((BURST) == DMA_PBURST_INC8) || \
1299 ((BURST) == DMA_PBURST_INC16))
uint32_t DMAmuxChannelStatusMask
DMAMUX_ChannelStatus_TypeDef * DMAmuxChannelStatus
HAL_StatusTypeDef
HAL Status structures definition
@ HAL_DMA_XFER_ERROR_CB_ID
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
DMA handle Structure definition.
uint32_t StreamBaseAddress
DMA Configuration Structure definition.
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
DMAMUX_Channel_TypeDef * DMAmuxChannel
HAL_LockTypeDef
HAL Lock structures definition
__IO HAL_DMA_StateTypeDef State
Header file of DMA HAL extension module.
@ HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
DMA_Stream_TypeDef * Instance
HAL_DMA_CallbackIDTypeDef
HAL DMA Callbacks IDs structure definition.
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ HAL_DMA_XFER_M1CPLT_CB_ID
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
@ HAL_DMA_XFER_CPLT_CB_ID
uint32_t DMAmuxRequestGenStatusMask
DMAMUX_RequestGen_TypeDef * DMAmuxRequestGen
This file contains HAL common defines, enumeration, macros and structures definitions.
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
@ HAL_DMA_XFER_HALFCPLT_CB_ID
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
HAL_DMA_LevelCompleteTypeDef
HAL DMA Transfer complete level structure definition.
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
DMAMUX_RequestGenStatus_TypeDef * DMAmuxRequestGenStatus
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))