stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
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1 
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32h7xx_hal.h"
26 
36 #ifdef HAL_RCC_MODULE_ENABLED
37 
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private defines -----------------------------------------------------------*/
43 #define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
44 #define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
45 
46 #define DIVIDER_P_UPDATE 0U
47 #define DIVIDER_Q_UPDATE 1U
48 #define DIVIDER_R_UPDATE 2U
49 
53 /* Private macros ------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private function prototypes -----------------------------------------------*/
63 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
64 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
65 
66 /* Exported functions --------------------------------------------------------*/
107 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
108 {
109  uint32_t tmpreg;
110  uint32_t tickstart;
111  HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
112  HAL_StatusTypeDef status = HAL_OK; /* Final status */
113 
114  /*---------------------------- SPDIFRX configuration -------------------------------*/
115 
116  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
117  {
118 
119  switch(PeriphClkInit->SpdifrxClockSelection)
120  {
121  case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/
122  /* Enable PLL1Q Clock output generated form System PLL . */
123  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
124 
125  /* SPDIFRX clock source configuration done later after clock selection check */
126  break;
127 
128  case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
129 
130  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
131 
132  /* SPDIFRX clock source configuration done later after clock selection check */
133  break;
134 
135  case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/
136  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
137 
138  /* SPDIFRX clock source configuration done later after clock selection check */
139  break;
140 
141  case RCC_SPDIFRXCLKSOURCE_HSI:
142  /* Internal OSC clock is used as source of SPDIFRX clock*/
143  /* SPDIFRX clock source configuration done later after clock selection check */
144  break;
145 
146  default:
147  ret = HAL_ERROR;
148  break;
149  }
150 
151  if(ret == HAL_OK)
152  {
153  /* Set the source of SPDIFRX clock*/
154  __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
155  }
156  else
157  {
158  /* set overall return value */
159  status = ret;
160  }
161  }
162 
163  /*---------------------------- SAI1 configuration -------------------------------*/
164  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
165  {
166  switch(PeriphClkInit->Sai1ClockSelection)
167  {
168  case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
169  /* Enable SAI Clock output generated form System PLL . */
170  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
171 
172  /* SAI1 clock source configuration done later after clock selection check */
173  break;
174 
175  case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
176 
177  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
178 
179  /* SAI1 clock source configuration done later after clock selection check */
180  break;
181 
182  case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
183  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
184 
185  /* SAI1 clock source configuration done later after clock selection check */
186  break;
187 
188  case RCC_SAI1CLKSOURCE_PIN:
189  /* External clock is used as source of SAI1 clock*/
190  /* SAI1 clock source configuration done later after clock selection check */
191  break;
192 
193  case RCC_SAI1CLKSOURCE_CLKP:
194  /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
195  /* SAI1 clock source configuration done later after clock selection check */
196  break;
197 
198  default:
199  ret = HAL_ERROR;
200  break;
201  }
202 
203  if(ret == HAL_OK)
204  {
205  /* Set the source of SAI1 clock*/
206  __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
207  }
208  else
209  {
210  /* set overall return value */
211  status = ret;
212  }
213  }
214 
215 #if defined(SAI3)
216  /*---------------------------- SAI2/3 configuration -------------------------------*/
217  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
218  {
219  switch(PeriphClkInit->Sai23ClockSelection)
220  {
221  case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */
222  /* Enable SAI Clock output generated form System PLL . */
223  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
224 
225  /* SAI2/3 clock source configuration done later after clock selection check */
226  break;
227 
228  case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
229 
230  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
231 
232  /* SAI2/3 clock source configuration done later after clock selection check */
233  break;
234 
235  case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */
236  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
237 
238  /* SAI2/3 clock source configuration done later after clock selection check */
239  break;
240 
241  case RCC_SAI23CLKSOURCE_PIN:
242  /* External clock is used as source of SAI2/3 clock*/
243  /* SAI2/3 clock source configuration done later after clock selection check */
244  break;
245 
246  case RCC_SAI23CLKSOURCE_CLKP:
247  /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
248  /* SAI2/3 clock source configuration done later after clock selection check */
249  break;
250 
251  default:
252  ret = HAL_ERROR;
253  break;
254  }
255 
256  if(ret == HAL_OK)
257  {
258  /* Set the source of SAI2/3 clock*/
259  __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
260  }
261  else
262  {
263  /* set overall return value */
264  status = ret;
265  }
266  }
267 
268 #endif /* SAI3 */
269 
270 #if defined(RCC_CDCCIP1R_SAI2ASEL)
271  /*---------------------------- SAI2A configuration -------------------------------*/
272  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
273  {
274  switch(PeriphClkInit->Sai2AClockSelection)
275  {
276  case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */
277  /* Enable SAI2A Clock output generated form System PLL . */
278  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
279 
280  /* SAI2A clock source configuration done later after clock selection check */
281  break;
282 
283  case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
284 
285  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
286 
287  /* SAI2A clock source configuration done later after clock selection check */
288  break;
289 
290  case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */
291  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
292 
293  /* SAI2A clock source configuration done later after clock selection check */
294  break;
295 
296  case RCC_SAI2ACLKSOURCE_PIN:
297  /* External clock is used as source of SAI2A clock*/
298  /* SAI2A clock source configuration done later after clock selection check */
299  break;
300 
301  case RCC_SAI2ACLKSOURCE_CLKP:
302  /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
303  /* SAI2A clock source configuration done later after clock selection check */
304  break;
305 
306  case RCC_SAI2ACLKSOURCE_SPDIF:
307  /* SPDIF clock is used as source of SAI2A clock */
308  /* SAI2A clock source configuration done later after clock selection check */
309  break;
310 
311  default:
312  ret = HAL_ERROR;
313  break;
314  }
315 
316  if(ret == HAL_OK)
317  {
318  /* Set the source of SAI2A clock*/
319  __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
320  }
321  else
322  {
323  /* set overall return value */
324  status = ret;
325  }
326  }
327 #endif /*SAI2A*/
328 
329 #if defined(RCC_CDCCIP1R_SAI2BSEL)
330 
331  /*---------------------------- SAI2B configuration -------------------------------*/
332  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
333  {
334  switch(PeriphClkInit->Sai2BClockSelection)
335  {
336  case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */
337  /* Enable SAI Clock output generated form System PLL . */
338  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
339 
340  /* SAI2B clock source configuration done later after clock selection check */
341  break;
342 
343  case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
344 
345  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
346 
347  /* SAI2B clock source configuration done later after clock selection check */
348  break;
349 
350  case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */
351  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
352 
353  /* SAI2B clock source configuration done later after clock selection check */
354  break;
355 
356  case RCC_SAI2BCLKSOURCE_PIN:
357  /* External clock is used as source of SAI2B clock*/
358  /* SAI2B clock source configuration done later after clock selection check */
359  break;
360 
361  case RCC_SAI2BCLKSOURCE_CLKP:
362  /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
363  /* SAI2B clock source configuration done later after clock selection check */
364  break;
365 
366  case RCC_SAI2BCLKSOURCE_SPDIF:
367  /* SPDIF clock is used as source of SAI2B clock */
368  /* SAI2B clock source configuration done later after clock selection check */
369  break;
370 
371  default:
372  ret = HAL_ERROR;
373  break;
374  }
375 
376  if(ret == HAL_OK)
377  {
378  /* Set the source of SAI2B clock*/
379  __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
380  }
381  else
382  {
383  /* set overall return value */
384  status = ret;
385  }
386  }
387 #endif /*SAI2B*/
388 
389 #if defined(SAI4)
390  /*---------------------------- SAI4A configuration -------------------------------*/
391  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
392  {
393  switch(PeriphClkInit->Sai4AClockSelection)
394  {
395  case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
396  /* Enable SAI Clock output generated form System PLL . */
397  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
398 
399  /* SAI1 clock source configuration done later after clock selection check */
400  break;
401 
402  case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
403 
404  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
405 
406  /* SAI2 clock source configuration done later after clock selection check */
407  break;
408 
409  case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
410  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
411 
412  /* SAI1 clock source configuration done later after clock selection check */
413  break;
414 
415  case RCC_SAI4ACLKSOURCE_PIN:
416  /* External clock is used as source of SAI2 clock*/
417  /* SAI2 clock source configuration done later after clock selection check */
418  break;
419 
420  case RCC_SAI4ACLKSOURCE_CLKP:
421  /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
422  /* SAI1 clock source configuration done later after clock selection check */
423  break;
424 
425 #if defined(RCC_VER_3_0)
426  case RCC_SAI4ACLKSOURCE_SPDIF:
427  /* SPDIF clock is used as source of SAI4A clock */
428  /* SAI4A clock source configuration done later after clock selection check */
429  break;
430 #endif /* RCC_VER_3_0 */
431 
432  default:
433  ret = HAL_ERROR;
434  break;
435  }
436 
437  if(ret == HAL_OK)
438  {
439  /* Set the source of SAI4A clock*/
440  __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
441  }
442  else
443  {
444  /* set overall return value */
445  status = ret;
446  }
447  }
448  /*---------------------------- SAI4B configuration -------------------------------*/
449  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
450  {
451  switch(PeriphClkInit->Sai4BClockSelection)
452  {
453  case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
454  /* Enable SAI Clock output generated form System PLL . */
455  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
456 
457  /* SAI1 clock source configuration done later after clock selection check */
458  break;
459 
460  case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
461 
462  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
463 
464  /* SAI2 clock source configuration done later after clock selection check */
465  break;
466 
467  case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
468  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
469 
470  /* SAI1 clock source configuration done later after clock selection check */
471  break;
472 
473  case RCC_SAI4BCLKSOURCE_PIN:
474  /* External clock is used as source of SAI2 clock*/
475  /* SAI2 clock source configuration done later after clock selection check */
476  break;
477 
478  case RCC_SAI4BCLKSOURCE_CLKP:
479  /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
480  /* SAI1 clock source configuration done later after clock selection check */
481  break;
482 
483 #if defined(RCC_VER_3_0)
484  case RCC_SAI4BCLKSOURCE_SPDIF:
485  /* SPDIF clock is used as source of SAI4B clock */
486  /* SAI4B clock source configuration done later after clock selection check */
487  break;
488 #endif /* RCC_VER_3_0 */
489 
490  default:
491  ret = HAL_ERROR;
492  break;
493  }
494 
495  if(ret == HAL_OK)
496  {
497  /* Set the source of SAI4B clock*/
498  __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
499  }
500  else
501  {
502  /* set overall return value */
503  status = ret;
504  }
505  }
506 #endif /*SAI4*/
507 
508 #if defined(QUADSPI)
509  /*---------------------------- QSPI configuration -------------------------------*/
510  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
511  {
512  switch(PeriphClkInit->QspiClockSelection)
513  {
514  case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/
515  /* Enable QSPI Clock output generated form System PLL . */
516  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
517 
518  /* QSPI clock source configuration done later after clock selection check */
519  break;
520 
521  case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
522 
523  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
524 
525  /* QSPI clock source configuration done later after clock selection check */
526  break;
527 
528 
529  case RCC_QSPICLKSOURCE_CLKP:
530  /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
531  /* QSPI clock source configuration done later after clock selection check */
532  break;
533 
534  case RCC_QSPICLKSOURCE_D1HCLK:
535  /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */
536  break;
537 
538  default:
539  ret = HAL_ERROR;
540  break;
541  }
542 
543  if(ret == HAL_OK)
544  {
545  /* Set the source of QSPI clock*/
546  __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
547  }
548  else
549  {
550  /* set overall return value */
551  status = ret;
552  }
553  }
554 #endif /*QUADSPI*/
555 
556 #if defined(OCTOSPI1) || defined(OCTOSPI2)
557  /*---------------------------- OCTOSPI configuration -------------------------------*/
558  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
559  {
560  switch(PeriphClkInit->OspiClockSelection)
561  {
562  case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/
563  /* Enable OSPI Clock output generated form System PLL . */
564  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
565 
566  /* OSPI clock source configuration done later after clock selection check */
567  break;
568 
569  case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
570 
571  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
572 
573  /* OSPI clock source configuration done later after clock selection check */
574  break;
575 
576 
577  case RCC_OSPICLKSOURCE_CLKP:
578  /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
579  /* OSPI clock source configuration done later after clock selection check */
580  break;
581 
582  case RCC_OSPICLKSOURCE_HCLK:
583  /* HCLK clock selected as OSPI kernel peripheral clock */
584  break;
585 
586  default:
587  ret = HAL_ERROR;
588  break;
589  }
590 
591  if(ret == HAL_OK)
592  {
593  /* Set the source of OSPI clock*/
594  __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
595  }
596  else
597  {
598  /* set overall return value */
599  status = ret;
600  }
601  }
602 #endif /*OCTOSPI*/
603 
604  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
605  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
606  {
607  switch(PeriphClkInit->Spi123ClockSelection)
608  {
609  case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */
610  /* Enable SPI Clock output generated form System PLL . */
611  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
612 
613  /* SPI1/2/3 clock source configuration done later after clock selection check */
614  break;
615 
616  case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
617  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
618 
619  /* SPI1/2/3 clock source configuration done later after clock selection check */
620  break;
621 
622  case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */
623  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
624 
625  /* SPI1/2/3 clock source configuration done later after clock selection check */
626  break;
627 
628  case RCC_SPI123CLKSOURCE_PIN:
629  /* External clock is used as source of SPI1/2/3 clock*/
630  /* SPI1/2/3 clock source configuration done later after clock selection check */
631  break;
632 
633  case RCC_SPI123CLKSOURCE_CLKP:
634  /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
635  /* SPI1/2/3 clock source configuration done later after clock selection check */
636  break;
637 
638  default:
639  ret = HAL_ERROR;
640  break;
641  }
642 
643  if(ret == HAL_OK)
644  {
645  /* Set the source of SPI1/2/3 clock*/
646  __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
647  }
648  else
649  {
650  /* set overall return value */
651  status = ret;
652  }
653  }
654 
655  /*---------------------------- SPI4/5 configuration -------------------------------*/
656  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
657  {
658  switch(PeriphClkInit->Spi45ClockSelection)
659  {
660  case RCC_SPI45CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for SPI4/5 */
661  /* SPI4/5 clock source configuration done later after clock selection check */
662  break;
663 
664  case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
665 
666  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
667 
668  /* SPI4/5 clock source configuration done later after clock selection check */
669  break;
670  case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */
671  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
672  /* SPI4/5 clock source configuration done later after clock selection check */
673  break;
674 
675  case RCC_SPI45CLKSOURCE_HSI:
676  /* HSI oscillator clock is used as source of SPI4/5 clock*/
677  /* SPI4/5 clock source configuration done later after clock selection check */
678  break;
679 
680  case RCC_SPI45CLKSOURCE_CSI:
681  /* CSI oscillator clock is used as source of SPI4/5 clock */
682  /* SPI4/5 clock source configuration done later after clock selection check */
683  break;
684 
685  case RCC_SPI45CLKSOURCE_HSE:
686  /* HSE, oscillator is used as source of SPI4/5 clock */
687  /* SPI4/5 clock source configuration done later after clock selection check */
688  break;
689 
690  default:
691  ret = HAL_ERROR;
692  break;
693  }
694 
695  if(ret == HAL_OK)
696  {
697  /* Set the source of SPI4/5 clock*/
698  __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
699  }
700  else
701  {
702  /* set overall return value */
703  status = ret;
704  }
705  }
706 
707  /*---------------------------- SPI6 configuration -------------------------------*/
708  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
709  {
710  switch(PeriphClkInit->Spi6ClockSelection)
711  {
712  case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
713  /* SPI6 clock source configuration done later after clock selection check */
714  break;
715 
716  case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
717 
718  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
719 
720  /* SPI6 clock source configuration done later after clock selection check */
721  break;
722  case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/
723  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
724  /* SPI6 clock source configuration done later after clock selection check */
725  break;
726 
727  case RCC_SPI6CLKSOURCE_HSI:
728  /* HSI oscillator clock is used as source of SPI6 clock*/
729  /* SPI6 clock source configuration done later after clock selection check */
730  break;
731 
732  case RCC_SPI6CLKSOURCE_CSI:
733  /* CSI oscillator clock is used as source of SPI6 clock */
734  /* SPI6 clock source configuration done later after clock selection check */
735  break;
736 
737  case RCC_SPI6CLKSOURCE_HSE:
738  /* HSE, oscillator is used as source of SPI6 clock */
739  /* SPI6 clock source configuration done later after clock selection check */
740  break;
741 #if defined(RCC_SPI6CLKSOURCE_PIN)
742  case RCC_SPI6CLKSOURCE_PIN:
743  /* 2S_CKIN is used as source of SPI6 clock */
744  /* SPI6 clock source configuration done later after clock selection check */
745  break;
746 #endif
747 
748  default:
749  ret = HAL_ERROR;
750  break;
751  }
752 
753  if(ret == HAL_OK)
754  {
755  /* Set the source of SPI6 clock*/
756  __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
757  }
758  else
759  {
760  /* set overall return value */
761  status = ret;
762  }
763  }
764 
765 #if defined(DSI)
766  /*---------------------------- DSI configuration -------------------------------*/
767  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
768  {
769  switch(PeriphClkInit->DsiClockSelection)
770  {
771 
772  case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
773 
774  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
775 
776  /* DSI clock source configuration done later after clock selection check */
777  break;
778 
779  case RCC_DSICLKSOURCE_PHY:
780  /* PHY is used as clock source for DSI*/
781  /* DSI clock source configuration done later after clock selection check */
782  break;
783 
784  default:
785  ret = HAL_ERROR;
786  break;
787  }
788 
789  if(ret == HAL_OK)
790  {
791  /* Set the source of DSI clock*/
792  __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
793  }
794  else
795  {
796  /* set overall return value */
797  status = ret;
798  }
799  }
800 #endif /*DSI*/
801 
802 #if defined(FDCAN1) || defined(FDCAN2)
803  /*---------------------------- FDCAN configuration -------------------------------*/
804  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
805  {
806  switch(PeriphClkInit->FdcanClockSelection)
807  {
808  case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/
809  /* Enable FDCAN Clock output generated form System PLL . */
810  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
811 
812  /* FDCAN clock source configuration done later after clock selection check */
813  break;
814 
815  case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
816 
817  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
818 
819  /* FDCAN clock source configuration done later after clock selection check */
820  break;
821 
822  case RCC_FDCANCLKSOURCE_HSE:
823  /* HSE is used as clock source for FDCAN*/
824  /* FDCAN clock source configuration done later after clock selection check */
825  break;
826 
827  default:
828  ret = HAL_ERROR;
829  break;
830  }
831 
832  if(ret == HAL_OK)
833  {
834  /* Set the source of FDCAN clock*/
835  __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
836  }
837  else
838  {
839  /* set overall return value */
840  status = ret;
841  }
842  }
843 #endif /*FDCAN1 || FDCAN2*/
844 
845  /*---------------------------- FMC configuration -------------------------------*/
846  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
847  {
848  switch(PeriphClkInit->FmcClockSelection)
849  {
850  case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/
851  /* Enable FMC Clock output generated form System PLL . */
852  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
853 
854  /* FMC clock source configuration done later after clock selection check */
855  break;
856 
857  case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
858 
859  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
860 
861  /* FMC clock source configuration done later after clock selection check */
862  break;
863 
864 
865  case RCC_FMCCLKSOURCE_CLKP:
866  /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
867  /* FMC clock source configuration done later after clock selection check */
868  break;
869 
870  case RCC_FMCCLKSOURCE_HCLK:
871  /* D1/CD HCLK clock selected as FMC kernel peripheral clock */
872  break;
873 
874  default:
875  ret = HAL_ERROR;
876  break;
877  }
878 
879  if(ret == HAL_OK)
880  {
881  /* Set the source of FMC clock*/
882  __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
883  }
884  else
885  {
886  /* set overall return value */
887  status = ret;
888  }
889  }
890 
891  /*---------------------------- RTC configuration -------------------------------*/
892  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
893  {
894  /* check for RTC Parameters used to output RTCCLK */
895  assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
896 
897  /* Enable write access to Backup domain */
898  SET_BIT(PWR->CR1, PWR_CR1_DBP);
899 
900  /* Wait for Backup domain Write protection disable */
901  tickstart = HAL_GetTick();
902 
903  while((PWR->CR1 & PWR_CR1_DBP) == 0U)
904  {
905  if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
906  {
907  ret = HAL_TIMEOUT;
908  break;
909  }
910  }
911 
912  if(ret == HAL_OK)
913  {
914  /* Reset the Backup domain only if the RTC Clock source selection is modified */
915  if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
916  {
917  /* Store the content of BDCR register before the reset of Backup Domain */
918  tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
919  /* RTC Clock selection can be changed only if the Backup Domain is reset */
920  __HAL_RCC_BACKUPRESET_FORCE();
921  __HAL_RCC_BACKUPRESET_RELEASE();
922  /* Restore the Content of BDCR register */
923  RCC->BDCR = tmpreg;
924  }
925 
926  /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
927  if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
928  {
929  /* Get Start Tick*/
930  tickstart = HAL_GetTick();
931 
932  /* Wait till LSE is ready */
933  while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
934  {
935  if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
936  {
937  ret = HAL_TIMEOUT;
938  break;
939  }
940  }
941  }
942 
943  if(ret == HAL_OK)
944  {
945  __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
946  }
947  else
948  {
949  /* set overall return value */
950  status = ret;
951  }
952  }
953  else
954  {
955  /* set overall return value */
956  status = ret;
957  }
958  }
959 
960 
961  /*-------------------------- USART1/6 configuration --------------------------*/
962  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
963  {
964  switch(PeriphClkInit->Usart16ClockSelection)
965  {
966  case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
967  /* USART1/6 clock source configuration done later after clock selection check */
968  break;
969 
970  case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
971  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
972  /* USART1/6 clock source configuration done later after clock selection check */
973  break;
974 
975  case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
976  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
977  /* USART1/6 clock source configuration done later after clock selection check */
978  break;
979 
980  case RCC_USART16CLKSOURCE_HSI:
981  /* HSI oscillator clock is used as source of USART1/6 clock */
982  /* USART1/6 clock source configuration done later after clock selection check */
983  break;
984 
985  case RCC_USART16CLKSOURCE_CSI:
986  /* CSI oscillator clock is used as source of USART1/6 clock */
987  /* USART1/6 clock source configuration done later after clock selection check */
988  break;
989 
990  case RCC_USART16CLKSOURCE_LSE:
991  /* LSE, oscillator is used as source of USART1/6 clock */
992  /* USART1/6 clock source configuration done later after clock selection check */
993  break;
994 
995  default:
996  ret = HAL_ERROR;
997  break;
998  }
999 
1000  if(ret == HAL_OK)
1001  {
1002  /* Set the source of USART1/6 clock */
1003  __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
1004  }
1005  else
1006  {
1007  /* set overall return value */
1008  status = ret;
1009  }
1010  }
1011 
1012  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
1013  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
1014  {
1015  switch(PeriphClkInit->Usart234578ClockSelection)
1016  {
1017  case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
1018  /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1019  break;
1020 
1021  case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
1022  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
1023  /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1024  break;
1025 
1026  case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
1027  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
1028  /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1029  break;
1030 
1031  case RCC_USART234578CLKSOURCE_HSI:
1032  /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
1033  /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1034  break;
1035 
1036  case RCC_USART234578CLKSOURCE_CSI:
1037  /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
1038  /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1039  break;
1040 
1041  case RCC_USART234578CLKSOURCE_LSE:
1042  /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */
1043  /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1044  break;
1045 
1046  default:
1047  ret = HAL_ERROR;
1048  break;
1049  }
1050 
1051  if(ret == HAL_OK)
1052  {
1053  /* Set the source of USART2/3/4/5/7/8 clock */
1054  __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
1055  }
1056  else
1057  {
1058  /* set overall return value */
1059  status = ret;
1060  }
1061  }
1062 
1063  /*-------------------------- LPUART1 Configuration -------------------------*/
1064  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
1065  {
1066  switch(PeriphClkInit->Lpuart1ClockSelection)
1067  {
1068  case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
1069  /* LPUART1 clock source configuration done later after clock selection check */
1070  break;
1071 
1072  case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
1073  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
1074  /* LPUART1 clock source configuration done later after clock selection check */
1075  break;
1076 
1077  case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
1078  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
1079  /* LPUART1 clock source configuration done later after clock selection check */
1080  break;
1081 
1082  case RCC_LPUART1CLKSOURCE_HSI:
1083  /* HSI oscillator clock is used as source of LPUART1 clock */
1084  /* LPUART1 clock source configuration done later after clock selection check */
1085  break;
1086 
1087  case RCC_LPUART1CLKSOURCE_CSI:
1088  /* CSI oscillator clock is used as source of LPUART1 clock */
1089  /* LPUART1 clock source configuration done later after clock selection check */
1090  break;
1091 
1092  case RCC_LPUART1CLKSOURCE_LSE:
1093  /* LSE, oscillator is used as source of LPUART1 clock */
1094  /* LPUART1 clock source configuration done later after clock selection check */
1095  break;
1096 
1097  default:
1098  ret = HAL_ERROR;
1099  break;
1100  }
1101 
1102  if(ret == HAL_OK)
1103  {
1104  /* Set the source of LPUART1 clock */
1105  __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
1106  }
1107  else
1108  {
1109  /* set overall return value */
1110  status = ret;
1111  }
1112  }
1113 
1114  /*---------------------------- LPTIM1 configuration -------------------------------*/
1115  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1116  {
1117  switch(PeriphClkInit->Lptim1ClockSelection)
1118  {
1119  case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/
1120  /* LPTIM1 clock source configuration done later after clock selection check */
1121  break;
1122 
1123  case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
1124 
1125  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
1126 
1127  /* LPTIM1 clock source configuration done later after clock selection check */
1128  break;
1129 
1130  case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/
1131  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
1132 
1133  /* LPTIM1 clock source configuration done later after clock selection check */
1134  break;
1135 
1136  case RCC_LPTIM1CLKSOURCE_LSE:
1137  /* External low speed OSC clock is used as source of LPTIM1 clock*/
1138  /* LPTIM1 clock source configuration done later after clock selection check */
1139  break;
1140 
1141  case RCC_LPTIM1CLKSOURCE_LSI:
1142  /* Internal low speed OSC clock is used as source of LPTIM1 clock*/
1143  /* LPTIM1 clock source configuration done later after clock selection check */
1144  break;
1145  case RCC_LPTIM1CLKSOURCE_CLKP:
1146  /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
1147  /* LPTIM1 clock source configuration done later after clock selection check */
1148  break;
1149 
1150  default:
1151  ret = HAL_ERROR;
1152  break;
1153  }
1154 
1155  if(ret == HAL_OK)
1156  {
1157  /* Set the source of LPTIM1 clock*/
1158  __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
1159  }
1160  else
1161  {
1162  /* set overall return value */
1163  status = ret;
1164  }
1165  }
1166 
1167  /*---------------------------- LPTIM2 configuration -------------------------------*/
1168  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
1169  {
1170  switch(PeriphClkInit->Lptim2ClockSelection)
1171  {
1172  case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
1173  /* LPTIM2 clock source configuration done later after clock selection check */
1174  break;
1175 
1176  case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
1177 
1178  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
1179 
1180  /* LPTIM2 clock source configuration done later after clock selection check */
1181  break;
1182 
1183  case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/
1184  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
1185 
1186  /* LPTIM2 clock source configuration done later after clock selection check */
1187  break;
1188 
1189  case RCC_LPTIM2CLKSOURCE_LSE:
1190  /* External low speed OSC clock is used as source of LPTIM2 clock*/
1191  /* LPTIM2 clock source configuration done later after clock selection check */
1192  break;
1193 
1194  case RCC_LPTIM2CLKSOURCE_LSI:
1195  /* Internal low speed OSC clock is used as source of LPTIM2 clock*/
1196  /* LPTIM2 clock source configuration done later after clock selection check */
1197  break;
1198  case RCC_LPTIM2CLKSOURCE_CLKP:
1199  /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
1200  /* LPTIM2 clock source configuration done later after clock selection check */
1201  break;
1202 
1203  default:
1204  ret = HAL_ERROR;
1205  break;
1206  }
1207 
1208  if(ret == HAL_OK)
1209  {
1210  /* Set the source of LPTIM2 clock*/
1211  __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
1212  }
1213  else
1214  {
1215  /* set overall return value */
1216  status = ret;
1217  }
1218  }
1219 
1220  /*---------------------------- LPTIM345 configuration -------------------------------*/
1221  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
1222  {
1223  switch(PeriphClkInit->Lptim345ClockSelection)
1224  {
1225 
1226  case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
1227  /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1228  break;
1229 
1230  case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
1231  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
1232 
1233  /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1234  break;
1235 
1236  case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */
1237  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
1238 
1239  /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1240  break;
1241 
1242  case RCC_LPTIM345CLKSOURCE_LSE:
1243  /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
1244  /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1245  break;
1246 
1247  case RCC_LPTIM345CLKSOURCE_LSI:
1248  /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */
1249  /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1250  break;
1251  case RCC_LPTIM345CLKSOURCE_CLKP:
1252  /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
1253  /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1254  break;
1255 
1256  default:
1257  ret = HAL_ERROR;
1258  break;
1259  }
1260 
1261  if(ret == HAL_OK)
1262  {
1263  /* Set the source of LPTIM3/4/5 clock */
1264  __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
1265  }
1266  else
1267  {
1268  /* set overall return value */
1269  status = ret;
1270  }
1271  }
1272 
1273  /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/
1274 #if defined(I2C5)
1275  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
1276  {
1277  /* Check the parameters */
1278  assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
1279 
1280  if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 )
1281  {
1282  if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
1283  {
1284  status = HAL_ERROR;
1285  }
1286  }
1287 
1288  __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
1289 
1290  }
1291 #else
1292  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
1293  {
1294  /* Check the parameters */
1295  assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
1296 
1297  if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
1298  {
1299  if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
1300  {
1301  status = HAL_ERROR;
1302  }
1303  }
1304 
1305  __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
1306 
1307  }
1308 #endif /* I2C5 */
1309 
1310  /*------------------------------ I2C4 Configuration ------------------------*/
1311  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
1312  {
1313  /* Check the parameters */
1314  assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
1315 
1316  if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
1317  {
1318  if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
1319  {
1320  status = HAL_ERROR;
1321  }
1322  }
1323 
1324  __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
1325 
1326  }
1327 
1328  /*---------------------------- ADC configuration -------------------------------*/
1329  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
1330  {
1331  switch(PeriphClkInit->AdcClockSelection)
1332  {
1333 
1334  case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
1335 
1336  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
1337 
1338  /* ADC clock source configuration done later after clock selection check */
1339  break;
1340 
1341  case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/
1342  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
1343 
1344  /* ADC clock source configuration done later after clock selection check */
1345  break;
1346 
1347  case RCC_ADCCLKSOURCE_CLKP:
1348  /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
1349  /* ADC clock source configuration done later after clock selection check */
1350  break;
1351 
1352  default:
1353  ret = HAL_ERROR;
1354  break;
1355  }
1356 
1357  if(ret == HAL_OK)
1358  {
1359  /* Set the source of ADC clock*/
1360  __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
1361  }
1362  else
1363  {
1364  /* set overall return value */
1365  status = ret;
1366  }
1367  }
1368 
1369  /*------------------------------ USB Configuration -------------------------*/
1370  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
1371  {
1372 
1373  switch(PeriphClkInit->UsbClockSelection)
1374  {
1375  case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/
1376  /* Enable USB Clock output generated form System USB . */
1377  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1378 
1379  /* USB clock source configuration done later after clock selection check */
1380  break;
1381 
1382  case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
1383 
1384  ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
1385 
1386  /* USB clock source configuration done later after clock selection check */
1387  break;
1388 
1389  case RCC_USBCLKSOURCE_HSI48:
1390  /* HSI48 oscillator is used as source of USB clock */
1391  /* USB clock source configuration done later after clock selection check */
1392  break;
1393 
1394  default:
1395  ret = HAL_ERROR;
1396  break;
1397  }
1398 
1399  if(ret == HAL_OK)
1400  {
1401  /* Set the source of USB clock*/
1402  __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
1403  }
1404  else
1405  {
1406  /* set overall return value */
1407  status = ret;
1408  }
1409 
1410  }
1411 
1412  /*------------------------------------- SDMMC Configuration ------------------------------------*/
1413  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
1414  {
1415  /* Check the parameters */
1416  assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
1417 
1418  switch(PeriphClkInit->SdmmcClockSelection)
1419  {
1420  case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/
1421  /* Enable SDMMC Clock output generated form System PLL . */
1422  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1423 
1424  /* SDMMC clock source configuration done later after clock selection check */
1425  break;
1426 
1427  case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
1428 
1429  ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
1430 
1431  /* SDMMC clock source configuration done later after clock selection check */
1432  break;
1433 
1434  default:
1435  ret = HAL_ERROR;
1436  break;
1437  }
1438 
1439  if(ret == HAL_OK)
1440  {
1441  /* Set the source of SDMMC clock*/
1442  __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
1443  }
1444  else
1445  {
1446  /* set overall return value */
1447  status = ret;
1448  }
1449  }
1450 
1451 #if defined(LTDC)
1452  /*-------------------------------------- LTDC Configuration -----------------------------------*/
1453  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
1454  {
1455  if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
1456  {
1457  status=HAL_ERROR;
1458  }
1459  }
1460 #endif /* LTDC */
1461 
1462  /*------------------------------ RNG Configuration -------------------------*/
1463  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
1464  {
1465 
1466  switch(PeriphClkInit->RngClockSelection)
1467  {
1468  case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/
1469  /* Enable RNG Clock output generated form System RNG . */
1470  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1471 
1472  /* RNG clock source configuration done later after clock selection check */
1473  break;
1474 
1475  case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
1476 
1477  /* RNG clock source configuration done later after clock selection check */
1478  break;
1479 
1480  case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
1481 
1482  /* RNG clock source configuration done later after clock selection check */
1483  break;
1484  case RCC_RNGCLKSOURCE_HSI48:
1485  /* HSI48 oscillator is used as source of RNG clock */
1486  /* RNG clock source configuration done later after clock selection check */
1487  break;
1488 
1489  default:
1490  ret = HAL_ERROR;
1491  break;
1492  }
1493 
1494  if(ret == HAL_OK)
1495  {
1496  /* Set the source of RNG clock*/
1497  __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
1498  }
1499  else
1500  {
1501  /* set overall return value */
1502  status = ret;
1503  }
1504 
1505  }
1506 
1507  /*------------------------------ SWPMI1 Configuration ------------------------*/
1508  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
1509  {
1510  /* Check the parameters */
1511  assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
1512 
1513  /* Configure the SWPMI1 interface clock source */
1514  __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
1515  }
1516 #if defined(HRTIM1)
1517  /*------------------------------ HRTIM1 clock Configuration ----------------*/
1518  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
1519  {
1520  /* Check the parameters */
1521  assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
1522 
1523  /* Configure the HRTIM1 clock source */
1524  __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
1525  }
1526 #endif /*HRTIM1*/
1527  /*------------------------------ DFSDM1 Configuration ------------------------*/
1528  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
1529  {
1530  /* Check the parameters */
1531  assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
1532 
1533  /* Configure the DFSDM1 interface clock source */
1534  __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
1535  }
1536 
1537 #if defined(DFSDM2_BASE)
1538  /*------------------------------ DFSDM2 Configuration ------------------------*/
1539  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
1540  {
1541  /* Check the parameters */
1542  assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
1543 
1544  /* Configure the DFSDM2 interface clock source */
1545  __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
1546  }
1547 #endif /* DFSDM2 */
1548 
1549  /*------------------------------------ TIM configuration --------------------------------------*/
1550  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
1551  {
1552  /* Check the parameters */
1553  assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
1554 
1555  /* Configure Timer Prescaler */
1556  __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
1557  }
1558 
1559  /*------------------------------------ CKPER configuration --------------------------------------*/
1560  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
1561  {
1562  /* Check the parameters */
1563  assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
1564 
1565  /* Configure the CKPER clock source */
1566  __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
1567  }
1568 
1569  /*------------------------------ CEC Configuration ------------------------*/
1570  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
1571  {
1572  /* Check the parameters */
1573  assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
1574 
1575  /* Configure the CEC interface clock source */
1576  __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
1577  }
1578 
1579  if (status == HAL_OK)
1580  {
1581  return HAL_OK;
1582  }
1583  return HAL_ERROR;
1584 }
1585 
1597 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1598 {
1599  /* Set all possible values for the extended clock type parameter------------*/
1600  PeriphClkInit->PeriphClockSelection =
1601  RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
1602  RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 |
1603  RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 |
1604  RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
1605  RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC |
1606  RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM |
1607  RCC_PERIPHCLK_CKPER;
1608 
1609 #if defined(I2C5)
1610 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235;
1611 #else
1612 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
1613 #endif /*I2C5*/
1614 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1615  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
1616 #endif /* RCC_CDCCIP1R_SAI2ASEL */
1617 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1618  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
1619 #endif /* RCC_CDCCIP1R_SAI2BSEL */
1620 #if defined(SAI3)
1621  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
1622 #endif /* SAI3 */
1623 #if defined(SAI4)
1624  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
1625  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
1626 #endif /* SAI4 */
1627 #if defined(DFSDM2_BASE)
1628  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
1629 #endif /* DFSDM2 */
1630 #if defined(QUADSPI)
1631  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
1632 #endif /* QUADSPI */
1633 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1634  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
1635 #endif /* OCTOSPI1 || OCTOSPI2 */
1636 #if defined(HRTIM1)
1637  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
1638 #endif /* HRTIM1 */
1639 #if defined(LTDC)
1640  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
1641 #endif /* LTDC */
1642 #if defined(DSI)
1643  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
1644 #endif /* DSI */
1645 
1646  /* Get the PLL3 Clock configuration -----------------------------------------------*/
1647  PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
1648  PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
1649  PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
1650  PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
1651  PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
1652  PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
1653  PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
1654 
1655  /* Get the PLL2 Clock configuration -----------------------------------------------*/
1656  PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
1657  PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
1658  PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
1659  PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
1660  PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
1661  PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
1662  PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
1663 
1664  /* Get the USART1 configuration --------------------------------------------*/
1665  PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE();
1666  /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
1667  PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE();
1668  /* Get the LPUART1 clock source --------------------------------------------*/
1669  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
1670 #if defined(I2C5)
1671  /* Get the I2C1/2/3/5 clock source -----------------------------------------*/
1672  PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1673 #else
1674  /* Get the I2C1/2/3 clock source -------------------------------------------*/
1675  PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1676 #endif /*I2C5*/
1677  /* Get the LPTIM1 clock source ---------------------------------------------*/
1678  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1679  /* Get the LPTIM2 clock source ---------------------------------------------*/
1680  PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
1681  /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
1682  PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE();
1683  /* Get the SAI1 clock source -----------------------------------------------*/
1684  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1685 #if defined(SAI3)
1686  /* Get the SAI2/3 clock source ---------------------------------------------*/
1687  PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE();
1688 #endif /*SAI3*/
1689 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
1690  /* Get the SAI2A clock source ---------------------------------------------*/
1691  PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE();
1692 #endif /*SAI2A*/
1693 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
1694  /* Get the SAI2B clock source ---------------------------------------------*/
1695  PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE();
1696 #endif /*SAI2B*/
1697 #if defined(SAI4)
1698  /* Get the SAI4A clock source ----------------------------------------------*/
1699  PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE();
1700  /* Get the SAI4B clock source ----------------------------------------------*/
1701  PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE();
1702 #endif /*SAI4*/
1703  /* Get the RTC clock source ------------------------------------------------*/
1704  PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1705  /* Get the USB clock source ------------------------------------------------*/
1706  PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
1707  /* Get the SDMMC clock source ----------------------------------------------*/
1708  PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
1709  /* Get the RNG clock source ------------------------------------------------*/
1710  PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
1711 #if defined(HRTIM1)
1712  /* Get the HRTIM1 clock source ---------------------------------------------*/
1713  PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
1714 #endif /* HRTIM1 */
1715  /* Get the ADC clock source ------------------------------------------------*/
1716  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1717  /* Get the SWPMI1 clock source ---------------------------------------------*/
1718  PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
1719  /* Get the DFSDM1 clock source ---------------------------------------------*/
1720  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
1721 #if defined(DFSDM2_BASE)
1722  /* Get the DFSDM2 clock source ---------------------------------------------*/
1723  PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
1724 #endif /* DFSDM2 */
1725  /* Get the SPDIFRX clock source --------------------------------------------*/
1726  PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
1727  /* Get the SPI1/2/3 clock source -------------------------------------------*/
1728  PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE();
1729  /* Get the SPI4/5 clock source ---------------------------------------------*/
1730  PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
1731  /* Get the SPI6 clock source -----------------------------------------------*/
1732  PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
1733  /* Get the FDCAN clock source ----------------------------------------------*/
1734  PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
1735  /* Get the CEC clock source ------------------------------------------------*/
1736  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
1737  /* Get the FMC clock source ------------------------------------------------*/
1738  PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
1739 #if defined(QUADSPI)
1740  /* Get the QSPI clock source -----------------------------------------------*/
1741  PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
1742 #endif /* QUADSPI */
1743 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1744  /* Get the OSPI clock source -----------------------------------------------*/
1745  PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1746 #endif /* OCTOSPI1 || OCTOSPI2 */
1747 
1748 #if defined(DSI)
1749  /* Get the DSI clock source ------------------------------------------------*/
1750  PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1751 #endif /*DSI*/
1752 
1753  /* Get the CKPER clock source ----------------------------------------------*/
1754  PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
1755 
1756  /* Get the TIM Prescaler configuration -------------------------------------*/
1757  if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
1758  {
1759  PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
1760  }
1761  else
1762  {
1763  PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
1764  }
1765 }
1766 
1786 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
1787 {
1788  PLL1_ClocksTypeDef pll1_clocks;
1789  PLL2_ClocksTypeDef pll2_clocks;
1790  PLL3_ClocksTypeDef pll3_clocks;
1791 
1792  /* This variable is used to store the clock frequency (value in Hz) */
1793  uint32_t frequency;
1794  /* This variable is used to store the SAI and CKP clock source */
1795  uint32_t saiclocksource;
1796  uint32_t ckpclocksource;
1797  uint32_t srcclk;
1798 
1799  if (PeriphClk == RCC_PERIPHCLK_SAI1)
1800  {
1801 
1802  saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
1803 
1804  switch (saiclocksource)
1805  {
1806  case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
1807  {
1808  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
1809  {
1810  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1811  frequency = pll1_clocks.PLL1_Q_Frequency;
1812  }
1813  else
1814  {
1815  frequency = 0;
1816  }
1817  break;
1818  }
1819  case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
1820  {
1821  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
1822  {
1823  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1824  frequency = pll2_clocks.PLL2_P_Frequency;
1825  }
1826  else
1827  {
1828  frequency = 0;
1829  }
1830  break;
1831  }
1832 
1833  case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
1834  {
1835  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
1836  {
1837  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1838  frequency = pll3_clocks.PLL3_P_Frequency;
1839  }
1840  else
1841  {
1842  frequency = 0;
1843  }
1844  break;
1845  }
1846 
1847  case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
1848  {
1849 
1850  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
1851 
1852  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
1853  {
1854  /* In Case the CKPER Source is HSI */
1855  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
1856  }
1857 
1858  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
1859  {
1860  /* In Case the CKPER Source is CSI */
1861  frequency = CSI_VALUE;
1862  }
1863 
1864  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
1865  {
1866  /* In Case the CKPER Source is HSE */
1867  frequency = HSE_VALUE;
1868  }
1869 
1870  else
1871  {
1872  /* In Case the CKPER is disabled*/
1873  frequency = 0;
1874  }
1875 
1876  break;
1877  }
1878 
1879  case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
1880  {
1881  frequency = EXTERNAL_CLOCK_VALUE;
1882  break;
1883  }
1884  default :
1885  {
1886  frequency = 0;
1887  break;
1888  }
1889  }
1890  }
1891 
1892 #if defined(SAI3)
1893  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
1894  {
1895 
1896  saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
1897 
1898  switch (saiclocksource)
1899  {
1900  case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
1901  {
1902  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
1903  {
1904  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1905  frequency = pll1_clocks.PLL1_Q_Frequency;
1906  }
1907  else
1908  {
1909  frequency = 0;
1910  }
1911  break;
1912  }
1913  case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
1914  {
1915  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
1916  {
1917  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1918  frequency = pll2_clocks.PLL2_P_Frequency;
1919  }
1920  else
1921  {
1922  frequency = 0;
1923  }
1924  break;
1925  }
1926 
1927  case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
1928  {
1929  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
1930  {
1931  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1932  frequency = pll3_clocks.PLL3_P_Frequency;
1933  }
1934  else
1935  {
1936  frequency = 0;
1937  }
1938  break;
1939  }
1940 
1941  case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
1942  {
1943 
1944  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
1945 
1946  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
1947  {
1948  /* In Case the CKPER Source is HSI */
1949  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
1950  }
1951 
1952  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
1953  {
1954  /* In Case the CKPER Source is CSI */
1955  frequency = CSI_VALUE;
1956  }
1957 
1958  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
1959  {
1960  /* In Case the CKPER Source is HSE */
1961  frequency = HSE_VALUE;
1962  }
1963 
1964  else
1965  {
1966  /* In Case the CKPER is disabled*/
1967  frequency = 0;
1968  }
1969 
1970  break;
1971  }
1972 
1973  case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
1974  {
1975  frequency = EXTERNAL_CLOCK_VALUE;
1976  break;
1977  }
1978  default :
1979  {
1980  frequency = 0;
1981  break;
1982  }
1983  }
1984  }
1985 #endif /* SAI3 */
1986 
1987 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1988 
1989  else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
1990  {
1991  saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
1992 
1993  switch (saiclocksource)
1994  {
1995  case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */
1996  {
1997  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
1998  {
1999  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2000  frequency = pll1_clocks.PLL1_Q_Frequency;
2001  }
2002  else
2003  {
2004  frequency = 0;
2005  }
2006  break;
2007  }
2008  case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
2009  {
2010  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2011  {
2012  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2013  frequency = pll2_clocks.PLL2_P_Frequency;
2014  }
2015  else
2016  {
2017  frequency = 0;
2018  }
2019  break;
2020  }
2021 
2022  case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */
2023  {
2024  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2025  {
2026  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2027  frequency = pll3_clocks.PLL3_P_Frequency;
2028  }
2029  else
2030  {
2031  frequency = 0;
2032  }
2033  break;
2034  }
2035 
2036  case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */
2037  {
2038 
2039  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
2040 
2041  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2042  {
2043  /* In Case the CKPER Source is HSI */
2044  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2045  }
2046 
2047  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2048  {
2049  /* In Case the CKPER Source is CSI */
2050  frequency = CSI_VALUE;
2051  }
2052 
2053  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2054  {
2055  /* In Case the CKPER Source is HSE */
2056  frequency = HSE_VALUE;
2057  }
2058 
2059  else
2060  {
2061  /* In Case the CKPER is disabled*/
2062  frequency = 0;
2063  }
2064 
2065  break;
2066  }
2067 
2068  case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
2069  {
2070  frequency = EXTERNAL_CLOCK_VALUE;
2071  break;
2072  }
2073 
2074  default :
2075  {
2076  frequency = 0;
2077  break;
2078  }
2079  }
2080 
2081  }
2082 #endif
2083 
2084 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
2085  else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
2086  {
2087 
2088  saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
2089 
2090  switch (saiclocksource)
2091  {
2092  case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */
2093  {
2094  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2095  {
2096  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2097  frequency = pll1_clocks.PLL1_Q_Frequency;
2098  }
2099  else
2100  {
2101  frequency = 0;
2102  }
2103  break;
2104  }
2105  case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
2106  {
2107  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2108  {
2109  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2110  frequency = pll2_clocks.PLL2_P_Frequency;
2111  }
2112  else
2113  {
2114  frequency = 0;
2115  }
2116  break;
2117  }
2118 
2119  case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
2120  {
2121  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2122  {
2123  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2124  frequency = pll3_clocks.PLL3_P_Frequency;
2125  }
2126  else
2127  {
2128  frequency = 0;
2129  }
2130  break;
2131  }
2132 
2133  case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
2134  {
2135 
2136  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
2137 
2138  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2139  {
2140  /* In Case the CKPER Source is HSI */
2141  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2142  }
2143 
2144  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2145  {
2146  /* In Case the CKPER Source is CSI */
2147  frequency = CSI_VALUE;
2148  }
2149 
2150  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2151  {
2152  /* In Case the CKPER Source is HSE */
2153  frequency = HSE_VALUE;
2154  }
2155 
2156  else
2157  {
2158  /* In Case the CKPER is disabled*/
2159  frequency = 0;
2160  }
2161  break;
2162  }
2163 
2164  case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
2165  {
2166  frequency = EXTERNAL_CLOCK_VALUE;
2167  break;
2168  }
2169 
2170  default :
2171  {
2172  frequency = 0;
2173  break;
2174  }
2175  }
2176  }
2177 #endif
2178 
2179 #if defined(SAI4)
2180  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
2181  {
2182 
2183  saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
2184 
2185  switch (saiclocksource)
2186  {
2187  case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
2188  {
2189  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2190  {
2191  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2192  frequency = pll1_clocks.PLL1_Q_Frequency;
2193  }
2194  else
2195  {
2196  frequency = 0;
2197  }
2198  break;
2199  }
2200  case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
2201  {
2202  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2203  {
2204  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2205  frequency = pll2_clocks.PLL2_P_Frequency;
2206  }
2207  else
2208  {
2209  frequency = 0;
2210  }
2211  break;
2212  }
2213 
2214  case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
2215  {
2216  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2217  {
2218  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2219  frequency = pll3_clocks.PLL3_P_Frequency;
2220  }
2221  else
2222  {
2223  frequency = 0;
2224  }
2225  break;
2226  }
2227 
2228  case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
2229  {
2230 
2231  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
2232 
2233  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2234  {
2235  /* In Case the CKPER Source is HSI */
2236  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2237  }
2238 
2239  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2240  {
2241  /* In Case the CKPER Source is CSI */
2242  frequency = CSI_VALUE;
2243  }
2244 
2245  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2246  {
2247  /* In Case the CKPER Source is HSE */
2248  frequency = HSE_VALUE;
2249  }
2250 
2251  else
2252  {
2253  /* In Case the CKPER is disabled*/
2254  frequency = 0;
2255  }
2256 
2257  break;
2258  }
2259 
2260  case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
2261  {
2262  frequency = EXTERNAL_CLOCK_VALUE;
2263  break;
2264  }
2265 
2266  default :
2267  {
2268  frequency = 0;
2269  break;
2270  }
2271  }
2272  }
2273 
2274  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
2275  {
2276 
2277  saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
2278 
2279  switch (saiclocksource)
2280  {
2281  case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
2282  {
2283  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2284  {
2285  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2286  frequency = pll1_clocks.PLL1_Q_Frequency;
2287  }
2288  else
2289  {
2290  frequency = 0;
2291  }
2292  break;
2293  }
2294  case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
2295  {
2296  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2297  {
2298  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2299  frequency = pll2_clocks.PLL2_P_Frequency;
2300  }
2301  else
2302  {
2303  frequency = 0;
2304  }
2305  break;
2306  }
2307 
2308  case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
2309  {
2310  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2311  {
2312  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2313  frequency = pll3_clocks.PLL3_P_Frequency;
2314  }
2315  else
2316  {
2317  frequency = 0;
2318  }
2319  break;
2320  }
2321 
2322  case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
2323  {
2324 
2325  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
2326 
2327  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2328  {
2329  /* In Case the CKPER Source is HSI */
2330  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2331  }
2332 
2333  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2334  {
2335  /* In Case the CKPER Source is CSI */
2336  frequency = CSI_VALUE;
2337  }
2338 
2339  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2340  {
2341  /* In Case the CKPER Source is HSE */
2342  frequency = HSE_VALUE;
2343  }
2344 
2345  else
2346  {
2347  /* In Case the CKPER is disabled*/
2348  frequency = 0;
2349  }
2350 
2351  break;
2352  }
2353 
2354  case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
2355  {
2356  frequency = EXTERNAL_CLOCK_VALUE;
2357  break;
2358  }
2359 
2360  default :
2361  {
2362  frequency = 0;
2363  break;
2364  }
2365  }
2366  }
2367 #endif /*SAI4*/
2368  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
2369  {
2370  /* Get SPI1/2/3 clock source */
2371  srcclk= __HAL_RCC_GET_SPI123_SOURCE();
2372 
2373  switch (srcclk)
2374  {
2375  case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
2376  {
2377  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2378  {
2379  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2380  frequency = pll1_clocks.PLL1_Q_Frequency;
2381  }
2382  else
2383  {
2384  frequency = 0;
2385  }
2386  break;
2387  }
2388  case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
2389  {
2390  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2391  {
2392  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2393  frequency = pll2_clocks.PLL2_P_Frequency;
2394  }
2395  else
2396  {
2397  frequency = 0;
2398  }
2399  break;
2400  }
2401 
2402  case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
2403  {
2404  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2405  {
2406  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2407  frequency = pll3_clocks.PLL3_P_Frequency;
2408  }
2409  else
2410  {
2411  frequency = 0;
2412  }
2413  break;
2414  }
2415 
2416  case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
2417  {
2418 
2419  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
2420 
2421  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2422  {
2423  /* In Case the CKPER Source is HSI */
2424  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2425  }
2426 
2427  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2428  {
2429  /* In Case the CKPER Source is CSI */
2430  frequency = CSI_VALUE;
2431  }
2432 
2433  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2434  {
2435  /* In Case the CKPER Source is HSE */
2436  frequency = HSE_VALUE;
2437  }
2438 
2439  else
2440  {
2441  /* In Case the CKPER is disabled*/
2442  frequency = 0;
2443  }
2444 
2445  break;
2446  }
2447 
2448  case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
2449  {
2450  frequency = EXTERNAL_CLOCK_VALUE;
2451  break;
2452  }
2453  default :
2454  {
2455  frequency = 0;
2456  break;
2457  }
2458  }
2459  }
2460  else if (PeriphClk == RCC_PERIPHCLK_ADC)
2461  {
2462  /* Get ADC clock source */
2463  srcclk= __HAL_RCC_GET_ADC_SOURCE();
2464 
2465  switch (srcclk)
2466  {
2467  case RCC_ADCCLKSOURCE_PLL2:
2468  {
2469  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2470  {
2471  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2472  frequency = pll2_clocks.PLL2_P_Frequency;
2473  }
2474  else
2475  {
2476  frequency = 0;
2477  }
2478  break;
2479  }
2480  case RCC_ADCCLKSOURCE_PLL3:
2481  {
2482  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2483  {
2484  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2485  frequency = pll3_clocks.PLL3_R_Frequency;
2486  }
2487  else
2488  {
2489  frequency = 0;
2490  }
2491  break;
2492  }
2493 
2494  case RCC_ADCCLKSOURCE_CLKP:
2495  {
2496 
2497  ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
2498 
2499  if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2500  {
2501  /* In Case the CKPER Source is HSI */
2502  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2503  }
2504 
2505  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2506  {
2507  /* In Case the CKPER Source is CSI */
2508  frequency = CSI_VALUE;
2509  }
2510 
2511  else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2512  {
2513  /* In Case the CKPER Source is HSE */
2514  frequency = HSE_VALUE;
2515  }
2516 
2517  else
2518  {
2519  /* In Case the CKPER is disabled*/
2520  frequency = 0;
2521  }
2522 
2523  break;
2524  }
2525 
2526  default :
2527  {
2528  frequency = 0;
2529  break;
2530  }
2531  }
2532  }
2533  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
2534  {
2535  /* Get SDMMC clock source */
2536  srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
2537 
2538  switch (srcclk)
2539  {
2540  case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
2541  {
2542  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2543  {
2544  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2545  frequency = pll1_clocks.PLL1_Q_Frequency;
2546  }
2547  else
2548  {
2549  frequency = 0;
2550  }
2551  break;
2552  }
2553  case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
2554  {
2555  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2556  {
2557  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2558  frequency = pll2_clocks.PLL2_R_Frequency;
2559  }
2560  else
2561  {
2562  frequency = 0;
2563  }
2564  break;
2565  }
2566 
2567  default :
2568  {
2569  frequency = 0;
2570  break;
2571  }
2572  }
2573  }
2574  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
2575  {
2576  /* Get SPI6 clock source */
2577  srcclk= __HAL_RCC_GET_SPI6_SOURCE();
2578 
2579  switch (srcclk)
2580  {
2581  case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
2582  {
2583  frequency = HAL_RCCEx_GetD3PCLK1Freq();
2584  break;
2585  }
2586  case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
2587  {
2588  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2589  {
2590  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2591  frequency = pll2_clocks.PLL2_Q_Frequency;
2592  }
2593  else
2594  {
2595  frequency = 0;
2596  }
2597  break;
2598  }
2599  case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
2600  {
2601  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2602  {
2603  HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2604  frequency = pll3_clocks.PLL3_Q_Frequency;
2605  }
2606  else
2607  {
2608  frequency = 0;
2609  }
2610  break;
2611  }
2612  case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
2613  {
2614  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2615  {
2616  frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2617  }
2618  else
2619  {
2620  frequency = 0;
2621  }
2622  break;
2623  }
2624  case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
2625  {
2626  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
2627  {
2628  frequency = CSI_VALUE;
2629  }
2630  else
2631  {
2632  frequency = 0;
2633  }
2634  break;
2635  }
2636  case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
2637  {
2638  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2639  {
2640  frequency = HSE_VALUE;
2641  }
2642  else
2643  {
2644  frequency = 0;
2645  }
2646  break;
2647  }
2648 #if defined(RCC_SPI6CLKSOURCE_PIN)
2649  case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
2650  {
2651  frequency = EXTERNAL_CLOCK_VALUE;
2652  break;
2653  }
2654 #endif /* RCC_SPI6CLKSOURCE_PIN */
2655  default :
2656  {
2657  frequency = 0;
2658  break;
2659  }
2660  }
2661  }
2662  else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
2663  {
2664  /* Get FDCAN clock source */
2665  srcclk= __HAL_RCC_GET_FDCAN_SOURCE();
2666 
2667  switch (srcclk)
2668  {
2669  case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
2670  {
2671  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2672  {
2673  frequency = HSE_VALUE;
2674  }
2675  else
2676  {
2677  frequency = 0;
2678  }
2679  break;
2680  }
2681  case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
2682  {
2683  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2684  {
2685  HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2686  frequency = pll1_clocks.PLL1_Q_Frequency;
2687  }
2688  else
2689  {
2690  frequency = 0;
2691  }
2692  break;
2693  }
2694  case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
2695  {
2696  if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2697  {
2698  HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2699  frequency = pll2_clocks.PLL2_Q_Frequency;
2700  }
2701  else
2702  {
2703  frequency = 0;
2704  }
2705  break;
2706  }
2707  default :
2708  {
2709  frequency = 0;
2710  break;
2711  }
2712  }
2713  }
2714  else
2715  {
2716  frequency = 0;
2717  }
2718 
2719  return frequency;
2720 }
2721 
2722 
2729 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
2730 {
2731 #if defined(RCC_D1CFGR_D1PPRE)
2732  /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
2733  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
2734 #else
2735 /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
2736  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
2737 #endif
2738 }
2739 
2746 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
2747 {
2748 #if defined(RCC_D3CFGR_D3PPRE)
2749  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
2750  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
2751 #else
2752  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
2753  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
2754 #endif
2755 }
2770 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
2771 {
2772  uint32_t pllsource, pll2m, pll2fracen, hsivalue;
2773  float_t fracn2, pll2vco;
2774 
2775  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
2776  PLL2xCLK = PLL2_VCO / PLL2x
2777  */
2778  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
2779  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12);
2780  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
2781  fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
2782 
2783  if (pll2m != 0U)
2784  {
2785  switch (pllsource)
2786  {
2787 
2788  case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
2789 
2790  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
2791  {
2792  hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2793  pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2794  }
2795  else
2796  {
2797  pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2798  }
2799  break;
2800 
2801  case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
2802  pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2803  break;
2804 
2805  case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
2806  pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2807  break;
2808 
2809  default:
2810  pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2811  break;
2812  }
2813  PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + (float_t)1 )) ;
2814  PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
2815  PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
2816  }
2817  else
2818  {
2819  PLL2_Clocks->PLL2_P_Frequency = 0U;
2820  PLL2_Clocks->PLL2_Q_Frequency = 0U;
2821  PLL2_Clocks->PLL2_R_Frequency = 0U;
2822  }
2823 }
2824 
2839 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
2840 {
2841  uint32_t pllsource, pll3m, pll3fracen, hsivalue;
2842  float_t fracn3, pll3vco;
2843 
2844  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
2845  PLL3xCLK = PLL3_VCO / PLLxR
2846  */
2847  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
2848  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ;
2849  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
2850  fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
2851 
2852  if (pll3m != 0U)
2853  {
2854  switch (pllsource)
2855  {
2856  case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
2857 
2858  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
2859  {
2860  hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2861  pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2862  }
2863  else
2864  {
2865  pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2866  }
2867  break;
2868  case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
2869  pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2870  break;
2871 
2872  case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
2873  pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2874  break;
2875 
2876  default:
2877  pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2878  break;
2879  }
2880  PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + (float_t)1 )) ;
2881  PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
2882  PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
2883  }
2884  else
2885  {
2886  PLL3_Clocks->PLL3_P_Frequency = 0U;
2887  PLL3_Clocks->PLL3_Q_Frequency = 0U;
2888  PLL3_Clocks->PLL3_R_Frequency = 0U;
2889  }
2890 
2891 }
2892 
2907 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
2908 {
2909  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
2910  float_t fracn1, pll1vco;
2911 
2912  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
2913  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
2914  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
2915  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
2916 
2917  if (pll1m != 0U)
2918  {
2919  switch (pllsource)
2920  {
2921 
2922  case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
2923 
2924  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
2925  {
2926  hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
2927  pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2928  }
2929  else
2930  {
2931  pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2932  }
2933  break;
2934  case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
2935  pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2936  break;
2937 
2938  case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
2939  pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2940  break;
2941 
2942  default:
2943  pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2944  break;
2945  }
2946 
2947  PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + (float_t)1 )) ;
2948  PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
2949  PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
2950  }
2951  else
2952  {
2953  PLL1_Clocks->PLL1_P_Frequency = 0U;
2954  PLL1_Clocks->PLL1_Q_Frequency = 0U;
2955  PLL1_Clocks->PLL1_R_Frequency = 0U;
2956  }
2957 
2958 }
2959 
2968 uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
2969 {
2970 uint32_t common_system_clock;
2971 
2972 #if defined(RCC_D1CFGR_D1CPRE)
2973  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
2974 #else
2975  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
2976 #endif
2977 
2978  /* Update the SystemD2Clock global variable */
2979 #if defined(RCC_D1CFGR_HPRE)
2980  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
2981 #else
2982  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
2983 #endif
2984 
2985 #if defined(DUAL_CORE) && defined(CORE_CM4)
2986  SystemCoreClock = SystemD2Clock;
2987 #else
2988  SystemCoreClock = common_system_clock;
2989 #endif /* DUAL_CORE && CORE_CM4 */
2990 
2991  return common_system_clock;
2992 }
3008 void HAL_RCCEx_EnableLSECSS(void)
3009 {
3010  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3011 }
3012 
3018 void HAL_RCCEx_DisableLSECSS(void)
3019 {
3020  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3021  /* Disable LSE CSS IT if any */
3022  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
3023 }
3024 
3030 void HAL_RCCEx_EnableLSECSS_IT(void)
3031 {
3032  /* Enable LSE CSS */
3033  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3034 
3035  /* Enable LSE CSS IT */
3036  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
3037 
3038  /* Enable IT on EXTI Line 18 */
3039 #if defined(DUAL_CORE) && defined(CORE_CM4)
3040  __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
3041 #else
3042  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
3043 #endif /* DUAL_CORE && CORE_CM4 */
3044  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
3045 }
3046 
3057 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
3058 {
3059  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
3060 
3061  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3062 }
3063 
3072 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
3073 {
3074  assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
3075 
3076  __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3077 }
3078 
3079 #if defined(DUAL_CORE)
3080 
3090 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
3091 {
3092  assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
3093  SET_BIT(RCC->GCR, RCC_BootCx) ;
3094 }
3095 
3096 #endif /*DUAL_CORE*/
3097 
3098 #if defined(DUAL_CORE)
3099 
3109 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3110 {
3111  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
3112  SET_BIT(RCC->GCR, RCC_WWDGx) ;
3113 }
3114 
3115 #else
3116 #if defined(RCC_GCR_WW1RSC)
3117 
3126 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3127 {
3128  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
3129  SET_BIT(RCC->GCR, RCC_WWDGx) ;
3130 }
3131 #endif
3132 #endif /*DUAL_CORE*/
3133 
3207 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
3208 {
3209  uint32_t value;
3210 
3211  /* Check the parameters */
3212  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
3213  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
3214  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
3215  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
3216  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
3217  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
3218 
3219  /* CONFIGURATION */
3220 
3221  /* Before configuration, reset CRS registers to their default values*/
3222  __HAL_RCC_CRS_FORCE_RESET();
3223  __HAL_RCC_CRS_RELEASE_RESET();
3224 
3225  /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
3226  /* Set the SYNCSRC[1:0] bits according to Source value */
3227  /* Set the SYNCSPOL bit according to Polarity value */
3228  if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
3229  {
3230  /* Use Rev.Y value of USB2 */
3231  value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
3232  }
3233  else
3234  {
3235  value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
3236  }
3237  /* Set the RELOAD[15:0] bits according to ReloadValue value */
3238  value |= pInit->ReloadValue;
3239  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
3240  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
3241  WRITE_REG(CRS->CFGR, value);
3242 
3243  /* Adjust HSI48 oscillator smooth trimming */
3244  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
3245  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
3246 
3247  /* START AUTOMATIC SYNCHRONIZATION*/
3248 
3249  /* Enable Automatic trimming & Frequency error counter */
3250  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
3251 }
3252 
3257 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
3258 {
3259  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
3260 }
3261 
3267 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
3268 {
3269  /* Check the parameter */
3270  assert_param(pSynchroInfo != (void *)NULL);
3271 
3272  /* Get the reload value */
3273  pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
3274 
3275  /* Get HSI48 oscillator smooth trimming */
3276  pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
3277 
3278  /* Get Frequency error capture */
3279  pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
3280 
3281  /* Get Frequency error direction */
3282  pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
3283 }
3284 
3300 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
3301 {
3302  uint32_t crsstatus = RCC_CRS_NONE;
3303  uint32_t tickstart;
3304 
3305  /* Get time-out */
3306  tickstart = HAL_GetTick();
3307 
3308  /* Wait for CRS flag or time-out detection */
3309  do
3310  {
3311  if(Timeout != HAL_MAX_DELAY)
3312  {
3313  if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3314  {
3315  crsstatus = RCC_CRS_TIMEOUT;
3316  }
3317  }
3318  /* Check CRS SYNCOK flag */
3319  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
3320  {
3321  /* CRS SYNC event OK */
3322  crsstatus |= RCC_CRS_SYNCOK;
3323 
3324  /* Clear CRS SYNC event OK bit */
3325  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
3326  }
3327 
3328  /* Check CRS SYNCWARN flag */
3329  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
3330  {
3331  /* CRS SYNC warning */
3332  crsstatus |= RCC_CRS_SYNCWARN;
3333 
3334  /* Clear CRS SYNCWARN bit */
3335  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
3336  }
3337 
3338  /* Check CRS TRIM overflow flag */
3339  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
3340  {
3341  /* CRS SYNC Error */
3342  crsstatus |= RCC_CRS_TRIMOVF;
3343 
3344  /* Clear CRS Error bit */
3345  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
3346  }
3347 
3348  /* Check CRS Error flag */
3349  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
3350  {
3351  /* CRS SYNC Error */
3352  crsstatus |= RCC_CRS_SYNCERR;
3353 
3354  /* Clear CRS Error bit */
3355  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
3356  }
3357 
3358  /* Check CRS SYNC Missed flag */
3359  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
3360  {
3361  /* CRS SYNC Missed */
3362  crsstatus |= RCC_CRS_SYNCMISS;
3363 
3364  /* Clear CRS SYNC Missed bit */
3365  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
3366  }
3367 
3368  /* Check CRS Expected SYNC flag */
3369  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
3370  {
3371  /* frequency error counter reached a zero value */
3372  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
3373  }
3374  } while(RCC_CRS_NONE == crsstatus);
3375 
3376  return crsstatus;
3377 }
3378 
3383 void HAL_RCCEx_CRS_IRQHandler(void)
3384 {
3385  uint32_t crserror = RCC_CRS_NONE;
3386  /* Get current IT flags and IT sources values */
3387  uint32_t itflags = READ_REG(CRS->ISR);
3388  uint32_t itsources = READ_REG(CRS->CR);
3389 
3390  /* Check CRS SYNCOK flag */
3391  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
3392  {
3393  /* Clear CRS SYNC event OK flag */
3394  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
3395 
3396  /* user callback */
3397  HAL_RCCEx_CRS_SyncOkCallback();
3398  }
3399  /* Check CRS SYNCWARN flag */
3400  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
3401  {
3402  /* Clear CRS SYNCWARN flag */
3403  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
3404 
3405  /* user callback */
3406  HAL_RCCEx_CRS_SyncWarnCallback();
3407  }
3408  /* Check CRS Expected SYNC flag */
3409  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
3410  {
3411  /* frequency error counter reached a zero value */
3412  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
3413 
3414  /* user callback */
3415  HAL_RCCEx_CRS_ExpectedSyncCallback();
3416  }
3417  /* Check CRS Error flags */
3418  else
3419  {
3420  if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
3421  {
3422  if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
3423  {
3424  crserror |= RCC_CRS_SYNCERR;
3425  }
3426  if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
3427  {
3428  crserror |= RCC_CRS_SYNCMISS;
3429  }
3430  if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
3431  {
3432  crserror |= RCC_CRS_TRIMOVF;
3433  }
3434 
3435  /* Clear CRS Error flags */
3436  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
3437 
3438  /* user error callback */
3439  HAL_RCCEx_CRS_ErrorCallback(crserror);
3440  }
3441  }
3442 }
3443 
3448 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
3449 {
3450  /* NOTE : This function should not be modified, when the callback is needed,
3451  the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
3452  */
3453 }
3454 
3459 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
3460 {
3461  /* NOTE : This function should not be modified, when the callback is needed,
3462  the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
3463  */
3464 }
3465 
3470 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
3471 {
3472  /* NOTE : This function should not be modified, when the callback is needed,
3473  the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
3474  */
3475 }
3476 
3486 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
3487 {
3488  /* Prevent unused argument(s) compilation warning */
3489  UNUSED(Error);
3490 
3491  /* NOTE : This function should not be modified, when the callback is needed,
3492  the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
3493  */
3494 }
3495 
3496 
3517 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
3518 {
3519 
3520  uint32_t tickstart;
3521  HAL_StatusTypeDef status = HAL_OK;
3522  assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
3523  assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
3524  assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
3525  assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
3526  assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
3527  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
3528  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
3529  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
3530 
3531  /* Check that PLL2 OSC clock source is already set */
3532  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
3533  {
3534  return HAL_ERROR;
3535  }
3536 
3537 
3538  else
3539  {
3540  /* Disable PLL2. */
3541  __HAL_RCC_PLL2_DISABLE();
3542 
3543  /* Get Start Tick*/
3544  tickstart = HAL_GetTick();
3545 
3546  /* Wait till PLL is disabled */
3547  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
3548  {
3549  if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
3550  {
3551  return HAL_TIMEOUT;
3552  }
3553  }
3554 
3555  /* Configure PLL2 multiplication and division factors. */
3556  __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
3557  pll2->PLL2N,
3558  pll2->PLL2P,
3559  pll2->PLL2Q,
3560  pll2->PLL2R);
3561 
3562  /* Select PLL2 input reference frequency range: VCI */
3563  __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
3564 
3565  /* Select PLL2 output frequency range : VCO */
3566  __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
3567 
3568  /* Disable PLL2FRACN . */
3569  __HAL_RCC_PLL2FRACN_DISABLE();
3570 
3571  /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
3572  __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
3573 
3574  /* Enable PLL2FRACN . */
3575  __HAL_RCC_PLL2FRACN_ENABLE();
3576 
3577  /* Enable the PLL2 clock output */
3578  if(Divider == DIVIDER_P_UPDATE)
3579  {
3580  __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
3581  }
3582  else if(Divider == DIVIDER_Q_UPDATE)
3583  {
3584  __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
3585  }
3586  else
3587  {
3588  __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
3589  }
3590 
3591  /* Enable PLL2. */
3592  __HAL_RCC_PLL2_ENABLE();
3593 
3594  /* Get Start Tick*/
3595  tickstart = HAL_GetTick();
3596 
3597  /* Wait till PLL2 is ready */
3598  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
3599  {
3600  if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
3601  {
3602  return HAL_TIMEOUT;
3603  }
3604  }
3605 
3606  }
3607 
3608 
3609  return status;
3610 }
3611 
3612 
3622 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
3623 {
3624  uint32_t tickstart;
3625  HAL_StatusTypeDef status = HAL_OK;
3626  assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
3627  assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
3628  assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
3629  assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
3630  assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
3631  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
3632  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
3633  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
3634 
3635  /* Check that PLL3 OSC clock source is already set */
3636  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
3637  {
3638  return HAL_ERROR;
3639  }
3640 
3641 
3642  else
3643  {
3644  /* Disable PLL3. */
3645  __HAL_RCC_PLL3_DISABLE();
3646 
3647  /* Get Start Tick*/
3648  tickstart = HAL_GetTick();
3649  /* Wait till PLL3 is ready */
3650  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
3651  {
3652  if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
3653  {
3654  return HAL_TIMEOUT;
3655  }
3656  }
3657 
3658  /* Configure the PLL3 multiplication and division factors. */
3659  __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
3660  pll3->PLL3N,
3661  pll3->PLL3P,
3662  pll3->PLL3Q,
3663  pll3->PLL3R);
3664 
3665  /* Select PLL3 input reference frequency range: VCI */
3666  __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
3667 
3668  /* Select PLL3 output frequency range : VCO */
3669  __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
3670 
3671  /* Disable PLL3FRACN . */
3672  __HAL_RCC_PLL3FRACN_DISABLE();
3673 
3674  /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
3675  __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
3676 
3677  /* Enable PLL3FRACN . */
3678  __HAL_RCC_PLL3FRACN_ENABLE();
3679 
3680  /* Enable the PLL3 clock output */
3681  if(Divider == DIVIDER_P_UPDATE)
3682  {
3683  __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
3684  }
3685  else if(Divider == DIVIDER_Q_UPDATE)
3686  {
3687  __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
3688  }
3689  else
3690  {
3691  __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
3692  }
3693 
3694  /* Enable PLL3. */
3695  __HAL_RCC_PLL3_ENABLE();
3696 
3697  /* Get Start Tick*/
3698  tickstart = HAL_GetTick();
3699 
3700  /* Wait till PLL3 is ready */
3701  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
3702  {
3703  if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
3704  {
3705  return HAL_TIMEOUT;
3706  }
3707  }
3708 
3709  }
3710 
3711 
3712  return status;
3713 }
3714 
3719 void HAL_RCCEx_LSECSS_IRQHandler(void)
3720 {
3721  /* Check RCC LSE CSSF flag */
3722  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
3723  {
3724 
3725  /* Clear RCC LSE CSS pending bit */
3726  __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
3727 
3728  /* RCC LSE Clock Security System interrupt user callback */
3729  HAL_RCCEx_LSECSS_Callback();
3730 
3731  }
3732 }
3733 
3738 __weak void HAL_RCCEx_LSECSS_Callback(void)
3739 {
3740  /* NOTE : This function should not be modified, when the callback is needed,
3741  the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
3742  */
3743 }
3744 
3745 
3746 
3751 #endif /* HAL_RCC_MODULE_ENABLED */
3752 
3760 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_SPI123CLKSOURCE_PIN
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Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1062
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#define CRS
Definition: stm32h735xx.h:2563
__HAL_RCC_PLL2CLKOUT_ENABLE
#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1786
__HAL_RCC_LPTIM1_CONFIG
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__)
Macro to configure the LPTIM1 clock (LPTIM1CLK).
Definition: stm32f7xx_hal_rcc_ex.h:3068
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uint32_t SystemD2Clock
Definition: stm32h735/stm32h735g-dk/Src/system_stm32h7xx.c:114
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Include module's header file.
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:353
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Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1459
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Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1059
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RCC_PLL3DIVR_R3_Pos
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Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:420
__HAL_RCC_TIMCLKPRESCALER
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
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#define RCC_D1CFGR_HPRE_Pos
Definition: stm32h735xx.h:15037
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Definition: stm32h735xx.h:14819
RCC_FMCCLKSOURCE_CLKP
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Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1426
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#define IS_RCC_PLL2RGE_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4290
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#define RCC_CRS_IT_ESYNC
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1726
__HAL_RCC_GET_LPTIM345_SOURCE
#define __HAL_RCC_GET_LPTIM345_SOURCE()
macro to get the LPTIM3/4/5 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2897
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uint32_t HSI48CalibrationValue
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:313
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Definition: stm32h735xx.h:15330
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HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
RCC_LPTIM345CLKSOURCE_PCLK4
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Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1300
__HAL_RCC_LSECSS_EXTI_ENABLE_IT
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()
Enable the RCC LSE CSS Extended Interrupt Line.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3609
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#define RCC_CFGR_TIMPRE
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__HAL_RCC_CEC_CONFIG
#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__)
Macro to configure the CEC clock (CECCLK).
Definition: stm32f7xx_hal_rcc_ex.h:3087
__HAL_RCC_ADC_CONFIG
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__)
Macro to configure the ADC clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3116
__HAL_RCC_RNG_CONFIG
#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__)
macro to configure the RNG clock (RNGCLK).
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3556
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#define RCC_PLL1DIVR_Q1
Definition: stm32h735xx.h:15327
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#define RCC_D1CFGR_D1CPRE_Pos
Definition: stm32h735xx.h:15094
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#define RCC_PLLSOURCE_HSI
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:181
__HAL_RCC_PLL3FRACN_ENABLE
#define __HAL_RCC_PLL3FRACN_ENABLE()
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1897
RCC_SPI45CLKSOURCE_PLL2
#define RCC_SPI45CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1124
__HAL_RCC_PLL3_VCIRANGE
#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__)
Macro to select the PLL3 reference frequency range.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1988
__HAL_RCC_PLL2FRACN_ENABLE
#define __HAL_RCC_PLL2FRACN_ENABLE()
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1795
__HAL_RCC_SAI1_CONFIG
#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)
Macro to configure SAI1 clock source selection.
Definition: stm32f7xx_hal_rcc_ex.h:2735
__HAL_RCC_USB_CONFIG
#define __HAL_RCC_USB_CONFIG(__USBCLKSource__)
Macro to configure the USB clock (USBCLK).
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3089
RCC_LPTIM1CLKSOURCE_LSI
#define RCC_LPTIM1CLKSOURCE_LSI
Definition: stm32f7xx_hal_rcc_ex.h:490
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#define RCC_FLAG_PLL3RDY
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:670
PWR
#define PWR
Definition: stm32f407xx.h:1083
RCC_CRS_NONE
#define RCC_CRS_NONE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1636
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
RCC_LPUART1CLKSOURCE_PCLK4
#define RCC_LPUART1CLKSOURCE_PCLK4
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:768
RCC_PERIPHCLK_RNG
#define RCC_PERIPHCLK_RNG
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:430
PLL3_ClocksTypeDef::PLL3_Q_Frequency
uint32_t PLL3_Q_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:134
NULL
#define NULL
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/speex_resampler/thirdparty/resample.c:92
RCC_PERIPHCLK_LPUART1
#define RCC_PERIPHCLK_LPUART1
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:376
IS_RCC_SCOPE_WWDG
#define IS_RCC_SCOPE_WWDG(WWDG)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4431
RCC_CRSInitTypeDef::Polarity
uint32_t Polarity
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:303
HAL_RCCEx_CRS_ErrorCallback
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
RCC_RTCCLKSOURCE_LSE
#define RCC_RTCCLKSOURCE_LSE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:256
__HAL_RCC_SWPMI1_CONFIG
#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__)
Macro to configure the SWPMI1 clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3142
RCC_PLLCKSELR_DIVM3
#define RCC_PLLCKSELR_DIVM3
Definition: stm32h735xx.h:15235
RCC_PERIPHCLK_SPI6
#define RCC_PERIPHCLK_SPI6
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:427
IS_RCC_PLL2R_VALUE
#define IS_RCC_PLL2R_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4288
RCC_PLL3InitTypeDef
PLL3 Clock structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:79
RCC_LPTIM345CLKSOURCE_LSI
#define RCC_LPTIM345CLKSOURCE_LSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1305
RCC_PeriphCLKInitTypeDef::Spi123ClockSelection
uint32_t Spi123ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:196
RCC_IT_LSECSS
#define RCC_IT_LSECSS
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:634
RCC_PLL2FRACR_FRACN2
#define RCC_PLL2FRACR_FRACN2
Definition: stm32h735xx.h:15354
__HAL_RCC_I2C4_CONFIG
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__)
Macro to configure the I2C4 clock (I2C4CLK).
Definition: stm32f7xx_hal_rcc_ex.h:2880
RCC_LPUART1CLKSOURCE_LSE
#define RCC_LPUART1CLKSOURCE_LSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:774
RCC_CRS_IT_SYNCWARN
#define RCC_CRS_IT_SYNCWARN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1724
RCC_LPTIM2CLKSOURCE_LSI
#define RCC_LPTIM2CLKSOURCE_LSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1278
RCC_SPI123CLKSOURCE_CLKP
#define RCC_SPI123CLKSOURCE_CLKP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1063
RCC_D1CFGR_D1PPRE
#define RCC_D1CFGR_D1PPRE
Definition: stm32h735xx.h:15075
RCC_FLAG_HSIDIV
#define RCC_FLAG_HSIDIV
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:652
__HAL_RCC_USART234578_CONFIG
#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__)
macro to configure the USART234578 clock (USART234578CLK).
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2502
RCC_PERIPHCLK_DSI
#define RCC_PERIPHCLK_DSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:447
RCC_SPDIFRXCLKSOURCE_PLL
#define RCC_SPDIFRXCLKSOURCE_PLL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1536
RCC_PERIPHCLK_SPDIFRX
#define RCC_PERIPHCLK_SPDIFRX
Definition: stm32f7xx_hal_rcc_ex.h:261
__HAL_RCC_SPI45_CONFIG
#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__)
Macro to Configure the SPI4/5 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3408
RCC_CRS_SYNCMISS
#define RCC_CRS_SYNCMISS
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1641
RCC_CRSInitTypeDef
RCC_CRS Init structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:295
IS_RCC_TIMPRES
#define IS_RCC_TIMPRES(VALUE)
Definition: stm32f7xx_hal_rcc_ex.h:3458
__HAL_RCC_LPTIM2_CONFIG
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__)
macro to configure the LPTIM2 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2848
RCC_FLAG_LSERDY
#define RCC_FLAG_LSERDY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:355
RCC_PLLSOURCE_NONE
#define RCC_PLLSOURCE_NONE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:268
__HAL_RCC_GET_RNG_SOURCE
#define __HAL_RCC_GET_RNG_SOURCE()
macro to get the RNG clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3570
__HAL_RCC_GET_SPI45_SOURCE
#define __HAL_RCC_GET_SPI45_SOURCE()
Macro to get the SPI4/5 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3424
RCC_PERIPHCLK_USART16
#define RCC_PERIPHCLK_USART16
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:363
IS_RCC_PLL2P_VALUE
#define IS_RCC_PLL2P_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4286
RCC_CR_HSIRDY
#define RCC_CR_HSIRDY
Definition: stm32f407xx.h:9431
RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection
uint32_t Swpmi1ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:218
__HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG
#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__)
Macro to configure the Kernel wake up from stop clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:7780
RCC_PLL3_DIVR
#define RCC_PLL3_DIVR
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:479
RCC_PERIPHCLK_DFSDM1
#define RCC_PERIPHCLK_DFSDM1
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:434
RCC_LPTIM345CLKSOURCE_PLL2
#define RCC_LPTIM345CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1302
RCC_USART16CLKSOURCE_PLL2
#define RCC_USART16CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:575
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:128
HAL_RCCEx_GetD3PCLK1Freq
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
RCC_USBCLKSOURCE_PLL
#define RCC_USBCLKSOURCE_PLL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:950
IS_RCC_CECCLKSOURCE
#define IS_RCC_CECCLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3385
IS_RCC_PLL3P_VALUE
#define IS_RCC_PLL3P_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4280
RCC_PeriphCLKInitTypeDef::PLL2
RCC_PLL2InitTypeDef PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:147
RCC_PLL3InitTypeDef::PLL3Q
uint32_t PLL3Q
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:94
HAL_RCCEx_WakeUpStopCLKConfig
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:326
RCC_FLAG_PLL2RDY
#define RCC_FLAG_PLL2RDY
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:669
__HAL_RCC_GET_DFSDM1_SOURCE
#define __HAL_RCC_GET_DFSDM1_SOURCE()
Macro to get the DFSDM1 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3179
RCC_I2C4CLKSOURCE_PLL3
#define RCC_I2C4CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:889
RCC_CRS_SYNCOK
#define RCC_CRS_SYNCOK
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1638
RCC_CRSInitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:297
__HAL_RCC_GET_LPUART1_SOURCE
#define __HAL_RCC_GET_LPUART1_SOURCE()
macro to get the LPUART1 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2796
PLL2_ClocksTypeDef::PLL2_P_Frequency
uint32_t PLL2_P_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:123
RCC_PLLCFGR_PLL2FRACEN
#define RCC_PLLCFGR_PLL2FRACEN
Definition: stm32h735xx.h:15261
HAL_RCCEx_CRS_SyncOkCallback
void HAL_RCCEx_CRS_SyncOkCallback(void)
IS_RCC_PLL2VCO_VALUE
#define IS_RCC_PLL2VCO_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4300
HAL_ERROR
@ HAL_ERROR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:43
RCC_LPTIM1CLKSOURCE_LSE
#define RCC_LPTIM1CLKSOURCE_LSE
Definition: stm32f7xx_hal_rcc_ex.h:492
__HAL_RCC_SPDIFRX_CONFIG
#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__)
Macro to Configure the SPDIFRX clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2053
RCC_SPI6CLKSOURCE_HSI
#define RCC_SPI6CLKSOURCE_HSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1180
RCC_CRS_FLAG_ESYNC
#define RCC_CRS_FLAG_ESYNC
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1741
RCC_PLL3InitTypeDef::PLL3R
uint32_t PLL3R
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:97
RCC_ADCCLKSOURCE_PLL3
#define RCC_ADCCLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1475
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:214
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323
RCC_D3CFGR_D3PPRE_Pos
#define RCC_D3CFGR_D3PPRE_Pos
Definition: stm32h735xx.h:15175
HAL_RCCEx_GetPLL1ClockFreq
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
RCC_ADCCLKSOURCE_PLL2
#define RCC_ADCCLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1474
RCC_PLL2InitTypeDef::PLL2M
uint32_t PLL2M
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:50
RCC_CRSInitTypeDef::ReloadValue
uint32_t ReloadValue
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:306
RCC_PERIPHCLK_LPTIM2
#define RCC_PERIPHCLK_LPTIM2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:395
RCC_PeriphCLKInitTypeDef::TIMPresSelection
uint32_t TIMPresSelection
Definition: stm32f7xx_hal_rcc_ex.h:154
PLL1_ClocksTypeDef::PLL1_Q_Frequency
uint32_t PLL1_Q_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:114
RCC_PLL2DIVR_P2
#define RCC_PLL2DIVR_P2
Definition: stm32h735xx.h:15343
RCC_PERIPHCLK_FMC
#define RCC_PERIPHCLK_FMC
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:440
RCC_SPI123CLKSOURCE_PLL3
#define RCC_SPI123CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1061
RCC_PLLCFGR_PLL1FRACEN
#define RCC_PLLCFGR_PLL1FRACEN
Definition: stm32h735xx.h:15247
CRS_CFGR_RELOAD
#define CRS_CFGR_RELOAD
Definition: stm32h735xx.h:5954
RCC_LPUART1CLKSOURCE_PLL2
#define RCC_LPUART1CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:770
RCC_CRS_FLAG_SYNCERR
#define RCC_CRS_FLAG_SYNCERR
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1742
__HAL_RCC_CRS_GET_FLAG
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)
Check whether the specified CRS flag is set or not.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3805
__HAL_RCC_GET_PLL_OSCSOURCE
#define __HAL_RCC_GET_PLL_OSCSOURCE()
Macro to get the oscillator used as PLL clock source.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1096
RCC_PLL3InitTypeDef::PLL3FRACN
uint32_t PLL3FRACN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:104
HAL_RCCEx_CRSWaitSynchronization
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
__HAL_RCC_FMC_CONFIG
#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__)
macro to configure the FMC clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3061
RCC_PLL3InitTypeDef::PLL3RGE
uint32_t PLL3RGE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:99
RCC_CLKPSOURCE_HSI
#define RCC_CLKPSOURCE_HSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1570
IS_RCC_CRS_HSI48CALIBRATION
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4452
RCC_CRS_SYNCERR
#define RCC_CRS_SYNCERR
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1640
RCC_LPTIM345CLKSOURCE_CLKP
#define RCC_LPTIM345CLKSOURCE_CLKP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1306
RCC_PLL3DIVR_N3_Pos
#define RCC_PLL3DIVR_N3_Pos
Definition: stm32h735xx.h:15357
__HAL_RCC_GET_SPDIFRX_SOURCE
#define __HAL_RCC_GET_SPDIFRX_SOURCE()
Macro to get the SPDIFRX clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2064
RCC_PeriphCLKInitTypeDef::Lptim345ClockSelection
uint32_t Lptim345ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:256
RCC_CR_HSERDY
#define RCC_CR_HSERDY
Definition: stm32f407xx.h:9459
RCC_PLL2DIVR_N2
#define RCC_PLL2DIVR_N2
Definition: stm32h735xx.h:15340
RCC_SPDIFRXCLKSOURCE_HSI
#define RCC_SPDIFRXCLKSOURCE_HSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1539
RCC_CRS_IT_SYNCOK
#define RCC_CRS_IT_SYNCOK
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1723
RCC_PLL3DIVR_P3
#define RCC_PLL3DIVR_P3
Definition: stm32h735xx.h:15362
RCC_PLL3DIVR_Q3_Pos
#define RCC_PLL3DIVR_Q3_Pos
Definition: stm32h735xx.h:15363
__HAL_RCC_SPI123_CONFIG
#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__)
Macro to Configure the SPI1/2/3 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3301
RCC_PERIPHCLK_SWPMI1
#define RCC_PERIPHCLK_SWPMI1
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:433
HAL_RCCEx_CRS_SyncWarnCallback
void HAL_RCCEx_CRS_SyncWarnCallback(void)
__HAL_RCC_PLL2_VCORANGE
#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__)
Macro to select the PLL2 reference frequency range.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1880
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
IS_RCC_CRS_RELOADVALUE
#define IS_RCC_CRS_RELOADVALUE(__VALUE__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4448
RCC_PLL2InitTypeDef::PLL2VCOSEL
uint32_t PLL2VCOSEL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:69
RCC_PLL3_DIVQ
#define RCC_PLL3_DIVQ
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:478
RCC_LPTIM1CLKSOURCE_PLL3
#define RCC_LPTIM1CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1248
RCC_PLL1_DIVQ
#define RCC_PLL1_DIVQ
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:277
CRS_ISR_FECAP_Pos
#define CRS_ISR_FECAP_Pos
Definition: stm32h735xx.h:6001
HAL_OK
@ HAL_OK
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:42
RCC_SAI1CLKSOURCE_PLL2
#define RCC_SAI1CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:970
RCC_LPTIM2CLKSOURCE_PLL3
#define RCC_LPTIM2CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1276
RCC_PLL3InitTypeDef::PLL3P
uint32_t PLL3P
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:90
PLL1_ClocksTypeDef::PLL1_R_Frequency
uint32_t PLL1_R_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:115
RCC_LPUART1CLKSOURCE_CSI
#define RCC_LPUART1CLKSOURCE_CSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:773
RCC_D1CFGR_HPRE
#define RCC_D1CFGR_HPRE
Definition: stm32h735xx.h:15039
REV_ID_Y
#define REV_ID_Y
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:60
RCC_PERIPHCLK_I2C123
#define RCC_PERIPHCLK_I2C123
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:385
HAL_RCCEx_CRSGetSynchronizationInfo
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
RCC_PLL3InitTypeDef::PLL3VCOSEL
uint32_t PLL3VCOSEL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:101
RCC_PeriphCLKInitTypeDef::Spi6ClockSelection
uint32_t Spi6ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:269
RCC_PLL2InitTypeDef::PLL2N
uint32_t PLL2N
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:53
__HAL_RCC_GET_SAI1_SOURCE
#define __HAL_RCC_GET_SAI1_SOURCE()
Macro to get the SAI1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2750
UNUSED
#define UNUSED(x)
Definition: porcupine/demo/c/dr_libs/old/dr.h:92
RCC_PLL2_DIVQ
#define RCC_PLL2_DIVQ
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:467
RCC_PERIPHCLK_FDCAN
#define RCC_PERIPHCLK_FDCAN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:428
RCC_CRSSynchroInfoTypeDef::FreqErrorDirection
uint32_t FreqErrorDirection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:333
RCC_PLLCFGR_PLL3VCOSEL_Pos
#define RCC_PLLCFGR_PLL3VCOSEL_Pos
Definition: stm32h735xx.h:15276
RCC_PLLCFGR_PLL3FRACEN
#define RCC_PLLCFGR_PLL3FRACEN
Definition: stm32h735xx.h:15275
RCC_LPTIM2CLKSOURCE_CLKP
#define RCC_LPTIM2CLKSOURCE_CLKP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1279
RCC_LPTIM345CLKSOURCE_LSE
#define RCC_LPTIM345CLKSOURCE_LSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1304
IS_RCC_PLL2M_VALUE
#define IS_RCC_PLL2M_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4284
RCC_PERIPHCLK_USART234578
#define RCC_PERIPHCLK_USART234578
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:369
RCC_PLLCFGR_PLL3RGE
#define RCC_PLLCFGR_PLL3RGE
Definition: stm32h735xx.h:15281
RCC_PLL2InitTypeDef::PLL2Q
uint32_t PLL2Q
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:62
__HAL_RCC_GET_RTC_SOURCE
#define __HAL_RCC_GET_RTC_SOURCE()
Macro to get the RTC clock source.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1005
__HAL_RCC_GET_IT
#define __HAL_RCC_GET_IT(__INTERRUPT__)
Check the RCC's interrupt has occurred or not.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1204
RCC_CRSSynchroInfoTypeDef::FreqErrorCapture
uint32_t FreqErrorCapture
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:329
RCC_PLLCKSELR_DIVM1
#define RCC_PLLCKSELR_DIVM1
Definition: stm32h735xx.h:15215
HAL_RCCEx_CRSConfig
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
PLL3_ClocksTypeDef::PLL3_P_Frequency
uint32_t PLL3_P_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:133
RCC_PeriphCLKInitTypeDef::Usart234578ClockSelection
uint32_t Usart234578ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:221
HSI_VALUE
#define HSI_VALUE
Internal High Speed oscillator (HSI) value. This value is used by the RCC HAL module to compute the s...
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:82
CRS_ISR_FEDIR
#define CRS_ISR_FEDIR
Definition: stm32h735xx.h:6000
CRS_ICR_SYNCWARNC
#define CRS_ICR_SYNCWARNC
Definition: stm32h735xx.h:6011
RCC_PeriphCLKInitTypeDef::SdmmcClockSelection
uint32_t SdmmcClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:172
__HAL_RCC_PLLCLKOUT_ENABLE
#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)
Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:7537
RCC_LPUART1CLKSOURCE_PLL3
#define RCC_LPUART1CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:771
IS_RCC_SWPMI1CLKSOURCE
#define IS_RCC_SWPMI1CLKSOURCE(SOURCE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4395
RCC_PLL3DIVR_P3_Pos
#define RCC_PLL3DIVR_P3_Pos
Definition: stm32h735xx.h:15360
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:199
RCC_PLL3_DIVP
#define RCC_PLL3_DIVP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:477
__HAL_RCC_CRS_CLEAR_FLAG
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3825
IS_RCC_PLL3VCO_VALUE
#define IS_RCC_PLL3VCO_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4303
__HAL_RCC_PLL3_VCORANGE
#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__)
Macro to select the PLL3 reference frequency range.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2002
RCC_SPI45CLKSOURCE_PCLK1
#define RCC_SPI45CLKSOURCE_PCLK1
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1123
RCC_USART16CLKSOURCE_PLL3
#define RCC_USART16CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:576
RCC_SPI45CLKSOURCE_PLL3
#define RCC_SPI45CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1125
__HAL_RCC_GET_CEC_SOURCE
#define __HAL_RCC_GET_CEC_SOURCE()
macro to get the CEC clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3095
CSI_VALUE
#define CSI_VALUE
Internal oscillator (CSI) default value. This value is the default CSI value after Reset.
Definition: stm32h735/stm32h735g-dk/Inc/stm32h7xx_hal_conf.h:120
__HAL_RCC_I2C1235_CONFIG
#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__)
macro to configure the I2C1/2/3/5* clock (I2C123CLK).
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2273
PLL2_ClocksTypeDef::PLL2_R_Frequency
uint32_t PLL2_R_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:125
RCC_PLLCFGR_PLL2VCOSEL_Pos
#define RCC_PLLCFGR_PLL2VCOSEL_Pos
Definition: stm32h735xx.h:15262
HAL_GetREVID
uint32_t HAL_GetREVID(void)
Returns the device revision identifier.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:450
__HAL_RCC_PLL3CLKOUT_ENABLE
#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1917
RCC_TIMPRES_ACTIVATED
#define RCC_TIMPRES_ACTIVATED
Definition: stm32f7xx_hal_rcc_ex.h:511
RCC_PLL2DIVR_P2_Pos
#define RCC_PLL2DIVR_P2_Pos
Definition: stm32h735xx.h:15341
RCC_LPTIM2CLKSOURCE_LSE
#define RCC_LPTIM2CLKSOURCE_LSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1277
IS_RCC_CLKPSOURCE
#define IS_RCC_CLKPSOURCE(SOURCE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4415
RCC_PLL2InitTypeDef::PLL2P
uint32_t PLL2P
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:58
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_MIMXRT1052.c:69
__HAL_RCC_CLEAR_IT
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__)
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selec...
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1190
RCC_SPDIFRXCLKSOURCE_PLL2
#define RCC_SPDIFRXCLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1537
CRS_CFGR_FELIM_Pos
#define CRS_CFGR_FELIM_Pos
Definition: stm32h735xx.h:5955
RCC_USART234578CLKSOURCE_PLL2
#define RCC_USART234578CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:659
RCC_PLLCFGR_PLL2RGE
#define RCC_PLLCFGR_PLL2RGE
Definition: stm32h735xx.h:15267
RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:321
RCC_CRSInitTypeDef::Source
uint32_t Source
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:300
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:224
__HAL_RCC_BACKUPRESET_RELEASE
#define __HAL_RCC_BACKUPRESET_RELEASE()
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1021
RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:205
__HAL_RCC_DISABLE_IT
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__)
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1176
__HAL_RCC_PLL3FRACN_DISABLE
#define __HAL_RCC_PLL3FRACN_DISABLE()
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1899
__HAL_RCC_GET_SPI123_SOURCE
#define __HAL_RCC_GET_SPI123_SOURCE()
Macro to get the SPI1/2/3 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3316
RCC_SAI1CLKSOURCE_CLKP
#define RCC_SAI1CLKSOURCE_CLKP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:973
__HAL_RCC_GET_SDMMC_SOURCE
#define __HAL_RCC_GET_SDMMC_SOURCE()
Macro to get the SDMMC clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3540
RCC_LPTIM2CLKSOURCE_PCLK4
#define RCC_LPTIM2CLKSOURCE_PCLK4
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1273
RCC_SAI1CLKSOURCE_PLL3
#define RCC_SAI1CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:971
CRS_CR_SWSYNC
#define CRS_CR_SWSYNC
Definition: stm32h735xx.h:5946
RCC_SPI6CLKSOURCE_PCLK4
#define RCC_SPI6CLKSOURCE_PCLK4
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1177
RCC_SPI6CLKSOURCE_PLL2
#define RCC_SPI6CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1178
__HAL_RCC_CRS_RELEASE_RESET
#define __HAL_RCC_CRS_RELEASE_RESET()
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:5012
RCC_LPUART1CLKSOURCE_HSI
#define RCC_LPUART1CLKSOURCE_HSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:772
RCC_CRS_IT_ERR
#define RCC_CRS_IT_ERR
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1725
RCC_PLL3DIVR_R3
#define RCC_PLL3DIVR_R3
Definition: stm32h735xx.h:15368
RCC_CRS_FLAG_ERR
#define RCC_CRS_FLAG_ERR
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1740
RCC_PLLCKSELR_DIVM2_Pos
#define RCC_PLLCKSELR_DIVM2_Pos
Definition: stm32h735xx.h:15223
RCC_USART16CLKSOURCE_HSI
#define RCC_USART16CLKSOURCE_HSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:577
RCC_PLL3InitTypeDef::PLL3M
uint32_t PLL3M
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:82
EXTERNAL_CLOCK_VALUE
#define EXTERNAL_CLOCK_VALUE
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S ...
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:110
RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection
uint32_t Lptim2ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:253
RCC_LPTIM2CLKSOURCE_PLL2
#define RCC_LPTIM2CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1275
__HAL_RCC_GET_LPTIM2_SOURCE
#define __HAL_RCC_GET_LPTIM2_SOURCE()
macro to get the LPTIM2 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2864
RCC_SPI45CLKSOURCE_CSI
#define RCC_SPI45CLKSOURCE_CSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1127
__HAL_RCC_USART16_CONFIG
#define __HAL_RCC_USART16_CONFIG
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2461
RCC_CRSInitTypeDef::ErrorLimitValue
uint32_t ErrorLimitValue
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:310
__HAL_RCC_ENABLE_IT
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__)
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1163
RCC_PLLSOURCE_CSI
#define RCC_PLLSOURCE_CSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:266
RCC_TIMPRES_DESACTIVATED
#define RCC_TIMPRES_DESACTIVATED
Definition: stm32f7xx_hal_rcc_ex.h:510
RCC_PLL2_DIVP
#define RCC_PLL2_DIVP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:466
__HAL_RCC_PLL2_CONFIG
#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
Macro to configures the PLL2 multiplication and division factors.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1831
PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:121
__HAL_RCC_PLL3_DISABLE
#define __HAL_RCC_PLL3_DISABLE()
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1890
__HAL_RCC_PLL3_ENABLE
#define __HAL_RCC_PLL3_ENABLE()
Macros to enable or disable the main PLL3.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1889
IS_RCC_PLL3R_VALUE
#define IS_RCC_PLL3R_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4282
__HAL_RCC_GET_CLKP_SOURCE
#define __HAL_RCC_GET_CLKP_SOURCE()
Macro to get the Oscillator clock for peripheral source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3252
RCC_PeriphCLKInitTypeDef::PLL3
RCC_PLL3InitTypeDef PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:150
__HAL_RCC_GET_FMC_SOURCE
#define __HAL_RCC_GET_FMC_SOURCE()
macro to get the FMC clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3075
RCC_CRS_FLAG_SYNCMISS
#define RCC_CRS_FLAG_SYNCMISS
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1743
RCC_PeriphCLKInitTypeDef::Usart16ClockSelection
uint32_t Usart16ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:224
PWR_CR1_DBP
#define PWR_CR1_DBP
Definition: stm32f769xx.h:10473
__HAL_RCC_GET_I2C1_SOURCE
#define __HAL_RCC_GET_I2C1_SOURCE()
Macro to get the I2C1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:2832
RCC_CLKPSOURCE_HSE
#define RCC_CLKPSOURCE_HSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1572
RCC_RNGCLKSOURCE_HSI48
#define RCC_RNGCLKSOURCE_HSI48
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:920
IS_RCC_I2C4CLKSOURCE
#define IS_RCC_I2C4CLKSOURCE(SOURCE)
Definition: stm32f7xx_hal_rcc_ex.h:3446
IS_RCC_STOP_WAKEUPCLOCK
#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:8242
__HAL_RCC_PLL3FRACN_CONFIG
#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__)
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1977
CRS_ICR_ERRC
#define CRS_ICR_ERRC
Definition: stm32h735xx.h:6014
IS_RCC_PLL3M_VALUE
#define IS_RCC_PLL3M_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4278
HAL_RCCEx_EnableLSECSS_IT
void HAL_RCCEx_EnableLSECSS_IT(void)
RCC_PLL2InitTypeDef::PLL2FRACN
uint32_t PLL2FRACN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:72
__HAL_RCC_GET_ADC_SOURCE
#define __HAL_RCC_GET_ADC_SOURCE()
Macro to get the ADC clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3129
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:216
RCC_PERIPHCLK_I2C4
#define RCC_PERIPHCLK_I2C4
Definition: stm32f7xx_hal_rcc_ex.h:254
RCC_PLL2DIVR_Q2
#define RCC_PLL2DIVR_Q2
Definition: stm32h735xx.h:15346
RCC_SPI45CLKSOURCE_HSI
#define RCC_SPI45CLKSOURCE_HSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1126
__HAL_RCC_LPUART1_CONFIG
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__)
macro to configure the LPUART1 clock (LPUART1CLK).
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2780
RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection
uint32_t SpdifrxClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:202
RCC_PLLSOURCE_HSE
#define RCC_PLLSOURCE_HSE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:182
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:61
RCC_D1CFGR_D1CPRE
#define RCC_D1CFGR_D1CPRE
Definition: stm32h735xx.h:15096
RCC_CR_PLL1RDY
#define RCC_CR_PLL1RDY
Definition: stm32h735xx.h:14856
CRS_CR_AUTOTRIMEN
#define CRS_CR_AUTOTRIMEN
Definition: stm32h735xx.h:5943
IS_RCC_CRS_SYNC_POLARITY
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4445
RCC_LPTIM345CLKSOURCE_PLL3
#define RCC_LPTIM345CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1303
RCC_CRS_SYNC_SOURCE_PIN
#define RCC_CRS_SYNC_SOURCE_PIN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1650
RCC_CRS_FLAG_SYNCWARN
#define RCC_CRS_FLAG_SYNCWARN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1739
RCC_PLL2InitTypeDef::PLL2R
uint32_t PLL2R
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:65
__HAL_RCC_PLL2FRACN_CONFIG
#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__)
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1854
RCC_PeriphCLKInitTypeDef::CkperClockSelection
uint32_t CkperClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:175
RCC_PLLCFGR_PLL3RGE_Pos
#define RCC_PLLCFGR_PLL3RGE_Pos
Definition: stm32h735xx.h:15279
__HAL_RCC_GET_USART16_SOURCE
#define __HAL_RCC_GET_USART16_SOURCE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2484
RCC_PeriphCLKInitTypeDef::CecClockSelection
uint32_t CecClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:202
IS_RCC_PLL2Q_VALUE
#define IS_RCC_PLL2Q_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4287
RCC_LSE_TIMEOUT_VALUE
#define RCC_LSE_TIMEOUT_VALUE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1336
RCC_SPI6CLKSOURCE_PLL3
#define RCC_SPI6CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1179
RCC_FMCCLKSOURCE_PLL2
#define RCC_FMCCLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1425
RCC_PLL3InitTypeDef::PLL3N
uint32_t PLL3N
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:85
RCC_PeriphCLKInitTypeDef::UsbClockSelection
uint32_t UsbClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:238
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
HAL_RCCEx_GetPLL3ClockFreq
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
RCC_PLL1DIVR_P1
#define RCC_PLL1DIVR_P1
Definition: stm32h735xx.h:15324
RCC_USART234578CLKSOURCE_CSI
#define RCC_USART234578CLKSOURCE_CSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:662
RCC_D3CFGR_D3PPRE
#define RCC_D3CFGR_D3PPRE
Definition: stm32h735xx.h:15177
RCC_SPI6CLKSOURCE_PIN
#define RCC_SPI6CLKSOURCE_PIN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1183
HAL_RCCEx_KerWakeUpStopCLKConfig
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
RCC
#define RCC
Definition: stm32f407xx.h:1113
IS_RCC_PLLFRACN_VALUE
#define IS_RCC_PLLFRACN_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:8084
RCC_PLL2_DIVR
#define RCC_PLL2_DIVR
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:468
CRS_CR_TRIM_Pos
#define CRS_CR_TRIM_Pos
Definition: stm32h735xx.h:5947
RCC_CR_PLL2RDY
#define RCC_CR_PLL2RDY
Definition: stm32h735xx.h:14862
RCC_RNGCLKSOURCE_LSI
#define RCC_RNGCLKSOURCE_LSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:923
__HAL_RCC_CLKP_CONFIG
#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__)
Macro to configure the CLKP : Oscillator clock for peripheral.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3239
RCC_PLLCKSELR_DIVM2
#define RCC_PLLCKSELR_DIVM2
Definition: stm32h735xx.h:15225
__HAL_RCC_LPTIM345_CONFIG
#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__)
macro to configure the LPTIM3/4/5 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2881
PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:111
HAL_TIMEOUT
@ HAL_TIMEOUT
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:45
RCC_PERIPHCLK_CEC
#define RCC_PERIPHCLK_CEC
Definition: stm32f7xx_hal_rcc_ex.h:259
PLL2_ClocksTypeDef::PLL2_Q_Frequency
uint32_t PLL2_Q_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:124
RCC_USART16CLKSOURCE_PCLK2
#define RCC_USART16CLKSOURCE_PCLK2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:574
RCC_PLLCKSELR_DIVM3_Pos
#define RCC_PLLCKSELR_DIVM3_Pos
Definition: stm32h735xx.h:15233
__HAL_RCC_GET_SPI6_SOURCE
#define __HAL_RCC_GET_SPI6_SOURCE()
Macro to get the SPI6 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3518
RCC_PLL3DIVR_N3
#define RCC_PLL3DIVR_N3
Definition: stm32h735xx.h:15359
RCC_FMCCLKSOURCE_PLL
#define RCC_FMCCLKSOURCE_PLL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1424
RCC_PeriphCLKInitTypeDef::Spi45ClockSelection
uint32_t Spi45ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:199
RCC_PLLCFGR_PLL3VCOSEL
#define RCC_PLLCFGR_PLL3VCOSEL
Definition: stm32h735xx.h:15278
RCC_PLLCFGR_PLL2VCOSEL
#define RCC_PLLCFGR_PLL2VCOSEL
Definition: stm32h735xx.h:15264
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:196
RCC_PLLCFGR_PLL2RGE_Pos
#define RCC_PLLCFGR_PLL2RGE_Pos
Definition: stm32h735xx.h:15265
RCC_USART16CLKSOURCE_LSE
#define RCC_USART16CLKSOURCE_LSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:579
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3673
RCC_PERIPHCLK_USB
#define RCC_PERIPHCLK_USB
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:431
RCC_PERIPHCLK_SAI1
#define RCC_PERIPHCLK_SAI1
Definition: stm32f7xx_hal_rcc_ex.h:256
RCC_USART234578CLKSOURCE_PLL3
#define RCC_USART234578CLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:660
IS_RCC_PLL3Q_VALUE
#define IS_RCC_PLL3Q_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4281
RCC_PERIPHCLK_SDMMC
#define RCC_PERIPHCLK_SDMMC
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:429
HAL_RCCEx_LSECSS_Callback
void HAL_RCCEx_LSECSS_Callback(void)
RCC_RNGCLKSOURCE_LSE
#define RCC_RNGCLKSOURCE_LSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:922
__HAL_RCC_PLL2_ENABLE
#define __HAL_RCC_PLL2_ENABLE()
Macros to enable or disable PLL2.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1767
PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:131
RCC_PERIPHCLK_LPTIM345
#define RCC_PERIPHCLK_LPTIM345
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:396
RCC_SPI45CLKSOURCE_HSE
#define RCC_SPI45CLKSOURCE_HSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1128
RCC_USART234578CLKSOURCE_PCLK1
#define RCC_USART234578CLKSOURCE_PCLK1
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:657
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_SPDIFRXCLKSOURCE_PLL3
#define RCC_SPDIFRXCLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1538
RCC_PLL1DIVR_N1
#define RCC_PLL1DIVR_N1
Definition: stm32h735xx.h:15321
__HAL_RCC_GET_FLAG
#define __HAL_RCC_GET_FLAG(__FLAG__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1230
RCC_SAI1CLKSOURCE_PIN
#define RCC_SAI1CLKSOURCE_PIN
Definition: stm32f7xx_hal_rcc_ex.h:327
RCC_PLLCKSELR_PLLSRC
#define RCC_PLLCKSELR_PLLSRC
Definition: stm32h735xx.h:15200
RCC_PERIPHCLK_TIM
#define RCC_PERIPHCLK_TIM
Definition: stm32f7xx_hal_rcc_ex.h:241
RCC_SDMMCCLKSOURCE_PLL
#define RCC_SDMMCCLKSOURCE_PLL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1458
RCC_BDCR_LSECSSON
#define RCC_BDCR_LSECSSON
Definition: stm32h735xx.h:15659
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
RCC_USART16CLKSOURCE_CSI
#define RCC_USART16CLKSOURCE_CSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:578
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:157
__HAL_RCC_GET_SWPMI1_SOURCE
#define __HAL_RCC_GET_SWPMI1_SOURCE()
Macro to get the SWPMI1 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3154
RCC_RNGCLKSOURCE_PLL
#define RCC_RNGCLKSOURCE_PLL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:921
RCC_PLL2InitTypeDef
PLL2 Clock structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:47
__HAL_RCC_PLL2FRACN_DISABLE
#define __HAL_RCC_PLL2FRACN_DISABLE()
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1797
RCC_PeriphCLKInitTypeDef::FmcClockSelection
uint32_t FmcClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:153
HAL_RCCEx_GetD1PCLK1Freq
uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
RCC_CRS_FLAG_TRIMOVF
#define RCC_CRS_FLAG_TRIMOVF
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1744
RCC_FMCCLKSOURCE_HCLK
#define RCC_FMCCLKSOURCE_HCLK
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1421
RCC_SPI123CLKSOURCE_PLL2
#define RCC_SPI123CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1060
RCC_DBP_TIMEOUT_VALUE
#define RCC_DBP_TIMEOUT_VALUE
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1335
__HAL_RCC_BACKUPRESET_FORCE
#define __HAL_RCC_BACKUPRESET_FORCE()
Macros to force or release the Backup domain reset.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1020
RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection
uint32_t Lpuart1ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:247
PLL3_ClocksTypeDef::PLL3_R_Frequency
uint32_t PLL3_R_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:135
HAL_RCCEx_CRS_IRQHandler
void HAL_RCCEx_CRS_IRQHandler(void)
CRS_ICR_SYNCOKC
#define CRS_ICR_SYNCOKC
Definition: stm32h735xx.h:6008
RCC_PERIPHCLK_LPTIM1
#define RCC_PERIPHCLK_LPTIM1
Definition: stm32f7xx_hal_rcc_ex.h:255
RCC_PeriphCLKInitTypeDef::I2c123ClockSelection
uint32_t I2c123ClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:234
RCC_CR_PLL3RDY
#define RCC_CR_PLL3RDY
Definition: stm32h735xx.h:14868
RCC_PERIPHCLK_RTC
#define RCC_PERIPHCLK_RTC
Definition: stm32f7xx_hal_rcc_ex.h:242
HSE_VALUE
#define HSE_VALUE
Adjust the value of External High Speed oscillator (HSE) used in your application....
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:69
RCC_CRS_SYNC_SOURCE_USB2
#define RCC_CRS_SYNC_SOURCE_USB2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1653
IS_RCC_I2C123CLKSOURCE
#define IS_RCC_I2C123CLKSOURCE(SOURCE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4093
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:63
HAL_RCCEx_GetD1SysClockFreq
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:220
PLL1_ClocksTypeDef::PLL1_P_Frequency
uint32_t PLL1_P_Frequency
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:113
RCC_BDCR_RTCSEL
#define RCC_BDCR_RTCSEL
Definition: stm32f407xx.h:10285
RCC_CRS_SYNCWARN
#define RCC_CRS_SYNCWARN
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1639
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition: stm32f7xx_hal_rcc_ex.h:126
RCC_SAI1CLKSOURCE_PLL
#define RCC_SAI1CLKSOURCE_PLL
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:969
RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK1
Definition: stm32f7xx_hal_rcc_ex.h:489
HAL_RCCEx_GetPLL2ClockFreq
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
RCC_CRS_TIMEOUT
#define RCC_CRS_TIMEOUT
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1637
RCC_PeriphCLKInitTypeDef::AdcClockSelection
uint32_t AdcClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:259
IS_RCC_RTCCLKSOURCE
#define IS_RCC_RTCCLKSOURCE(__SOURCE__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:1381
__HAL_RCC_GET_LPTIM1_SOURCE
#define __HAL_RCC_GET_LPTIM1_SOURCE()
macro to get the LPTIM1 clock source.
Definition: stm32f7xx_hal_rcc_ex.h:3078
RCC_ADCCLKSOURCE_CLKP
#define RCC_ADCCLKSOURCE_CLKP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1476
RCC_PLL2InitTypeDef::PLL2RGE
uint32_t PLL2RGE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:67
RCC_USART234578CLKSOURCE_LSE
#define RCC_USART234578CLKSOURCE_LSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:663
RCC_PeriphCLKInitTypeDef::RngClockSelection
uint32_t RngClockSelection
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:227
RCC_LPTIM1CLKSOURCE_PLL2
#define RCC_LPTIM1CLKSOURCE_PLL2
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1247
RCC_PLL1FRACR_FRACN1
#define RCC_PLL1FRACR_FRACN1
Definition: stm32h735xx.h:15335
__HAL_RCC_WAKEUPSTOP_CLK_CONFIG
#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__)
Macro to configure the wake up from stop clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:7769
READ_REG
#define READ_REG(REG)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:222
__HAL_RCC_SDMMC_CONFIG
#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__)
Macro to configure the SDMMC clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3531
RCC_SPI6CLKSOURCE_CSI
#define RCC_SPI6CLKSOURCE_CSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1181
__HAL_RCC_RTC_CONFIG
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:994
CRS_ISR_FECAP
#define CRS_ISR_FECAP
Definition: stm32h735xx.h:6003
RCC_PLLCFGR_PLL2FRACEN_Pos
#define RCC_PLLCFGR_PLL2FRACEN_Pos
Definition: stm32h735xx.h:15259
RCC_SPI6CLKSOURCE_D3PCLK1
#define RCC_SPI6CLKSOURCE_D3PCLK1
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1176
SET_BIT
#define SET_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:212
RCC_D1CFGR_D1PPRE_Pos
#define RCC_D1CFGR_D1PPRE_Pos
Definition: stm32h735xx.h:15073
CRS_ICR_ESYNCC
#define CRS_ICR_ESYNCC
Definition: stm32h735xx.h:6017
__HAL_RCC_GET_USART234578_SOURCE
#define __HAL_RCC_GET_USART234578_SOURCE()
macro to get the USART2/3/4/5/7/8 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2518
RCC_CRS_TRIMOVF
#define RCC_CRS_TRIMOVF
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1642
HAL_RCCEx_LSECSS_IRQHandler
void HAL_RCCEx_LSECSS_IRQHandler(void)
RCC_CRSSynchroInfoTypeDef::ReloadValue
uint32_t ReloadValue
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:323
IS_RCC_CRS_ERRORLIMIT
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4450
IS_RCC_STOP_KERWAKEUPCLOCK
#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:8245
RCC_PLL2DIVR_R2
#define RCC_PLL2DIVR_R2
Definition: stm32h735xx.h:15349
IS_RCC_PLL3N_VALUE
#define IS_RCC_PLL3N_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4279
RCC_PERIPHCLK_ADC
#define RCC_PERIPHCLK_ADC
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:432
__HAL_RCC_PLL2_DISABLE
#define __HAL_RCC_PLL2_DISABLE()
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1768
IS_RCC_PLL2N_VALUE
#define IS_RCC_PLL2N_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4285
HAL_RCCEx_CRS_ExpectedSyncCallback
void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
__HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__)
Macro to configure the DFSDM1 clock.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3167
__HAL_RCC_SPI6_CONFIG
#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__)
Macro to Configure the SPI6 clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3501
RCC_PLL3FRACR_FRACN3
#define RCC_PLL3FRACR_FRACN3
Definition: stm32h735xx.h:15373
HAL_RCCEx_DisableLSECSS
void HAL_RCCEx_DisableLSECSS(void)
__HAL_RCC_GET_HSI_DIVIDER
#define __HAL_RCC_GET_HSI_DIVIDER()
Macro to get the HSI divider.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:7145
RCC_USBCLKSOURCE_HSI48
#define RCC_USBCLKSOURCE_HSI48
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:952
RCC_PLL2DIVR_Q2_Pos
#define RCC_PLL2DIVR_Q2_Pos
Definition: stm32h735xx.h:15344
RCC_USART234578CLKSOURCE_HSI
#define RCC_USART234578CLKSOURCE_HSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:661
RCC_PLLCFGR_PLL3FRACEN_Pos
#define RCC_PLLCFGR_PLL3FRACEN_Pos
Definition: stm32h735xx.h:15273
__HAL_RCC_I2C123_CONFIG
#define __HAL_RCC_I2C123_CONFIG
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:2276
IS_RCC_SDMMC
#define IS_RCC_SDMMC(__SOURCE__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4387
CRS_CR_CEN
#define CRS_CR_CEN
Definition: stm32h735xx.h:5940
RCC_PLL2DIVR_N2_Pos
#define RCC_PLL2DIVR_N2_Pos
Definition: stm32h735xx.h:15338
RCC_PERIPHCLK_CKPER
#define RCC_PERIPHCLK_CKPER
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:456
RCC_SPI6CLKSOURCE_HSE
#define RCC_SPI6CLKSOURCE_HSE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1182
__HAL_RCC_GET_USB_SOURCE
#define __HAL_RCC_GET_USB_SOURCE()
Macro to get the USB clock source.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:3102
IS_RCC_DFSDM1CLKSOURCE
#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4398
__HAL_RCC_PLL2_VCIRANGE
#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__)
Macro to select the PLL2 reference frequency range.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1866
RCC_LPTIM1CLKSOURCE_CLKP
#define RCC_LPTIM1CLKSOURCE_CLKP
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1251
IS_RCC_CRS_SYNC_SOURCE
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4435
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
CRS_CR_TRIM
#define CRS_CR_TRIM
Definition: stm32h735xx.h:5949
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition: stm32f7xx_hal_rcc_ex.h:148
RCC_PERIPHCLK_SPI45
#define RCC_PERIPHCLK_SPI45
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:424
__HAL_RCC_PLL3_CONFIG
#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
Macro to configures the PLL3 multiplication and division factors.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1953
RCC_CLKPSOURCE_CSI
#define RCC_CLKPSOURCE_CSI
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1571
RCC_USBCLKSOURCE_PLL3
#define RCC_USBCLKSOURCE_PLL3
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:951
D1CorePrescTable
const uint8_t D1CorePrescTable[16]
Definition: stm32h735/stm32h735g-dk/Src/system_stm32h7xx.c:115
IS_RCC_CRS_SYNC_DIV
#define IS_RCC_CRS_SYNC_DIV(__DIV__)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4440
RCC_PLL2DIVR_R2_Pos
#define RCC_PLL2DIVR_R2_Pos
Definition: stm32h735xx.h:15347
__HAL_RCC_CRS_FORCE_RESET
#define __HAL_RCC_CRS_FORCE_RESET()
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:4971
RCC_PLL3DIVR_Q3
#define RCC_PLL3DIVR_Q3
Definition: stm32h735xx.h:15365
RCC_CRS_FLAG_SYNCOK
#define RCC_CRS_FLAG_SYNCOK
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:1738
IS_RCC_PLL3RGE_VALUE
#define IS_RCC_PLL3RGE_VALUE(VALUE)
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:4295

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:55