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21 #ifndef STM32H7xx_HAL_RCC_EX_H
22 #define STM32H7xx_HAL_RCC_EX_H
144 uint32_t PeriphClockSelection;
157 uint32_t QspiClockSelection;
161 #if defined(OCTOSPI1) || defined(OCTOSPI2)
162 uint32_t OspiClockSelection;
168 uint32_t DsiClockSelection;
178 uint32_t Sai1ClockSelection;
182 uint32_t Sai23ClockSelection;
186 #if defined(RCC_CDCCIP1R_SAI2ASEL)
187 uint32_t Sai2AClockSelection;
191 #if defined(RCC_CDCCIP1R_SAI2BSEL)
192 uint32_t Sai2BClockSelection;
208 #if defined(DFSDM2_BASE)
209 uint32_t Dfsdm2ClockSelection;
213 #if defined(FDCAN1) || defined(FDCAN2)
214 uint32_t FdcanClockSelection;
241 uint32_t CecClockSelection;
244 uint32_t Lptim1ClockSelection;
250 uint32_t I2c4ClockSelection;
262 uint32_t Sai4AClockSelection;
265 uint32_t Sai4BClockSelection;
272 uint32_t RTCClockSelection;
276 uint32_t Hrtim1ClockSelection;
280 uint32_t TIMPresSelection;
286 #define I2c123ClockSelection I2c1235ClockSelection
288 #define I2c1235ClockSelection I2c123ClockSelection
354 #if defined(UART9) && defined(USART10)
355 #define RCC_PERIPHCLK_USART16910 (0x00000001U)
356 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910
357 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910
358 #define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910
359 #define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910
361 #define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910
363 #define RCC_PERIPHCLK_USART16 (0x00000001U)
364 #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16
365 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16
367 #define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16
369 #define RCC_PERIPHCLK_USART234578 (0x00000002U)
370 #define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
371 #define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
372 #define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
373 #define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
374 #define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
375 #define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
376 #define RCC_PERIPHCLK_LPUART1 (0x00000004U)
378 #define RCC_PERIPHCLK_I2C1235 (0x00000008U)
379 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235
380 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235
381 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235
383 #define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235
385 #define RCC_PERIPHCLK_I2C123 (0x00000008U)
386 #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
387 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
388 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
390 #define RCC_PERIPHCLK_I2C4 (0x00000010U)
392 #define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235
394 #define RCC_PERIPHCLK_LPTIM1 (0x00000020U)
395 #define RCC_PERIPHCLK_LPTIM2 (0x00000040U)
396 #define RCC_PERIPHCLK_LPTIM345 (0x00000080U)
397 #define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
399 #define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345
402 #define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345
404 #define RCC_PERIPHCLK_SAI1 (0x00000100U)
406 #define RCC_PERIPHCLK_SAI23 (0x00000200U)
407 #define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23
408 #define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23
410 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
411 #define RCC_PERIPHCLK_SAI2A (0x00000200U)
413 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
414 #define RCC_PERIPHCLK_SAI2B (0x00000400U)
417 #define RCC_PERIPHCLK_SAI4A (0x00000400U)
418 #define RCC_PERIPHCLK_SAI4B (0x00000800U)
420 #define RCC_PERIPHCLK_SPI123 (0x00001000U)
421 #define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
422 #define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
423 #define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
424 #define RCC_PERIPHCLK_SPI45 (0x00002000U)
425 #define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
426 #define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
427 #define RCC_PERIPHCLK_SPI6 (0x00004000U)
428 #define RCC_PERIPHCLK_FDCAN (0x00008000U)
429 #define RCC_PERIPHCLK_SDMMC (0x00010000U)
430 #define RCC_PERIPHCLK_RNG (0x00020000U)
431 #define RCC_PERIPHCLK_USB (0x00040000U)
432 #define RCC_PERIPHCLK_ADC (0x00080000U)
433 #define RCC_PERIPHCLK_SWPMI1 (0x00100000U)
434 #define RCC_PERIPHCLK_DFSDM1 (0x00200000U)
435 #if defined(DFSDM2_BASE)
436 #define RCC_PERIPHCLK_DFSDM2 (0x00000800U)
438 #define RCC_PERIPHCLK_RTC (0x00400000U)
439 #define RCC_PERIPHCLK_CEC (0x00800000U)
440 #define RCC_PERIPHCLK_FMC (0x01000000U)
442 #define RCC_PERIPHCLK_QSPI (0x02000000U)
444 #if defined(OCTOSPI1) || defined(OCTOSPI2)
445 #define RCC_PERIPHCLK_OSPI (0x02000000U)
447 #define RCC_PERIPHCLK_DSI (0x04000000U)
448 #define RCC_PERIPHCLK_SPDIFRX (0x08000000U)
450 #define RCC_PERIPHCLK_HRTIM1 (0x10000000U)
453 #define RCC_PERIPHCLK_LTDC (0x20000000U)
455 #define RCC_PERIPHCLK_TIM (0x40000000U)
456 #define RCC_PERIPHCLK_CKPER (0x80000000U)
466 #define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
467 #define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
468 #define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN
477 #define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
478 #define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
479 #define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN
488 #define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
489 #define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
490 #define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
491 #define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
501 #define RCC_PLL2VCOWIDE (0x00000000U)
502 #define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL
511 #define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
512 #define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
513 #define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
514 #define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
524 #define RCC_PLL3VCOWIDE (0x00000000U)
525 #define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL
534 #if defined(RCC_D2CCIP2R_USART16SEL)
535 #define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U)
537 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
538 #define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
539 #define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
540 #define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
541 #define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
542 #define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
544 #elif defined(RCC_CDCCIP2R_USART16910SEL)
545 #define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U)
547 #define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
548 #define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0
549 #define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1
550 #define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
551 #define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2
552 #define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
555 #define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2
556 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
557 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2
558 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
559 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
560 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
561 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
562 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
565 #define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U)
566 #define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0
567 #define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1
568 #define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
569 #define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2
570 #define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
573 #define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
574 #define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2
575 #define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2
576 #define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3
577 #define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI
578 #define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI
579 #define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE
588 #define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
589 #define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
590 #define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
591 #define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
592 #define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
593 #define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
601 #define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
602 #define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
603 #define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
604 #define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
605 #define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
606 #define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
616 #define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
617 #define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
618 #define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
619 #define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
620 #define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
621 #define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
631 #define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
632 #define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
633 #define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
634 #define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
635 #define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
636 #define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
645 #if defined(RCC_D2CCIP2R_USART28SEL)
646 #define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U)
648 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
649 #define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
650 #define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
651 #define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
652 #define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
653 #define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
655 #define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U)
657 #define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
658 #define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1
659 #define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0
660 #define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1
661 #define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
662 #define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2
663 #define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
672 #define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
673 #define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
674 #define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
675 #define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
676 #define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
677 #define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
686 #define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
687 #define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
688 #define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
689 #define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
690 #define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
691 #define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
700 #define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
701 #define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
702 #define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
703 #define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
704 #define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
705 #define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
714 #define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
715 #define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
716 #define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
717 #define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
718 #define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
719 #define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
728 #define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
729 #define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
730 #define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
731 #define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
732 #define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
733 #define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
742 #define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
743 #define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
744 #define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
745 #define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
746 #define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
747 #define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
756 #if defined(RCC_D3CCIPR_LPUART1SEL)
757 #define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U)
759 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1
760 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0
761 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1
762 #define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
763 #define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2
764 #define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
766 #define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U)
768 #define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4
769 #define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4
770 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0
771 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1
772 #define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
773 #define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2
774 #define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
783 #if defined (RCC_D2CCIP2R_I2C123SEL)
784 #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U)
785 #define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
786 #define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
787 #define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
789 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
790 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
791 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
792 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
793 #elif defined(RCC_CDCCIP2R_I2C123SEL)
794 #define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U)
796 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1
797 #define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0
798 #define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1
799 #define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
801 #define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
802 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
803 #define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
804 #define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
806 #define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U)
807 #define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0
808 #define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1
809 #define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
811 #define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
812 #define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
813 #define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
814 #define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
824 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
825 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
826 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
827 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
829 #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
830 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
831 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
832 #define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
843 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
844 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
845 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
846 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
848 #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
849 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
850 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
851 #define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
862 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
863 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
864 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
865 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
867 #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
868 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
869 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
870 #define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
880 #if defined(RCC_D3CCIPR_I2C4SEL)
881 #define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U)
882 #define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0
883 #define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1
884 #define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
886 #define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U)
888 #define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4
889 #define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0
890 #define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1
891 #define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
901 #define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1
902 #define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3
903 #define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI
904 #define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI
914 #if defined(RCC_D2CCIP2R_RNGSEL)
915 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
916 #define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0
917 #define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1
918 #define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL
920 #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
921 #define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0
922 #define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1
923 #define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL
934 #define RCC_HRTIM1CLK_TIMCLK (0x00000000U)
935 #define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL
945 #if defined(RCC_D2CCIP2R_USBSEL)
946 #define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
947 #define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
948 #define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
950 #define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0
951 #define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1
952 #define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL
962 #if defined(RCC_D2CCIP1R_SAI1SEL)
963 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
964 #define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0
965 #define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1
966 #define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
967 #define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2
969 #define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
970 #define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0
971 #define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1
972 #define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
973 #define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2
983 #define RCC_SAI23CLKSOURCE_PLL (0x00000000U)
984 #define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
985 #define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
986 #define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
987 #define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2
995 #define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
996 #define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
997 #define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
998 #define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
999 #define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
1008 #define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
1009 #define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
1010 #define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
1011 #define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
1012 #define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
1018 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1022 #define RCC_SAI2ACLKSOURCE_PLL (0x00000000U)
1023 #define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0
1024 #define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1
1025 #define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
1026 #define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2
1027 #define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
1033 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1037 #define RCC_SAI2BCLKSOURCE_PLL (0x00000000U)
1038 #define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0
1039 #define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1
1040 #define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
1041 #define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2
1042 #define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
1052 #if defined(RCC_D2CCIP1R_SPI123SEL)
1053 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
1054 #define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0
1055 #define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
1056 #define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
1057 #define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
1059 #define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
1060 #define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0
1061 #define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1
1062 #define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
1063 #define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2
1072 #define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1073 #define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1074 #define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1075 #define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1076 #define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1085 #define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1086 #define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1087 #define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1088 #define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1089 #define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1098 #define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
1099 #define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
1100 #define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
1101 #define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
1102 #define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
1111 #if defined(RCC_D2CCIP1R_SPI45SEL)
1112 #define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U)
1113 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
1114 #define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
1115 #define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
1116 #define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
1117 #define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
1118 #define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
1120 #define RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U)
1122 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1
1123 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1
1124 #define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0
1125 #define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1
1126 #define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
1127 #define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2
1128 #define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
1137 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
1138 #define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
1139 #define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
1140 #define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
1141 #define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
1142 #define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
1151 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
1152 #define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
1153 #define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
1154 #define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
1155 #define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
1156 #define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
1165 #if defined(RCC_D3CCIPR_SPI6SEL)
1166 #define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U)
1167 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1
1168 #define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0
1169 #define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1
1170 #define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
1171 #define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2
1172 #define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
1174 #define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U)
1176 #define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4
1177 #define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4
1178 #define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0
1179 #define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1
1180 #define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
1181 #define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2
1182 #define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
1183 #define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
1191 #if defined(SAI4_Block_A)
1195 #define RCC_SAI4ACLKSOURCE_PLL (0x00000000U)
1196 #define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0
1197 #define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
1198 #define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
1199 #define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2
1200 #if defined(RCC_VER_3_0)
1201 #define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
1211 #if defined(SAI4_Block_B)
1215 #define RCC_SAI4BCLKSOURCE_PLL (0x00000000U)
1216 #define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0
1217 #define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
1218 #define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
1219 #define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2
1220 #if defined(RCC_VER_3_0)
1221 #define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
1233 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
1234 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U)
1236 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1
1237 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0
1238 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1
1239 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
1240 #define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2
1241 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
1243 #define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U)
1245 #define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
1246 #define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1
1247 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0
1248 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1
1249 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
1250 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2
1251 #define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
1261 #if defined(RCC_D3CCIPR_LPTIM2SEL)
1262 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U)
1264 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1
1265 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0
1266 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1
1267 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
1268 #define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2
1269 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
1271 #define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U)
1273 #define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4
1274 #define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4
1275 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0
1276 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1
1277 #define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
1278 #define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2
1279 #define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
1288 #if defined(RCC_D3CCIPR_LPTIM345SEL)
1289 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U)
1291 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1
1292 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
1293 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
1294 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
1295 #define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
1296 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
1298 #define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U)
1300 #define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4
1301 #define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4
1302 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0
1303 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1
1304 #define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
1305 #define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2
1306 #define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
1315 #define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1316 #define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1317 #define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1318 #define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1319 #define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1320 #define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1329 #define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1330 #define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1331 #define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1332 #define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1333 #define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1334 #define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1344 #define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
1345 #define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
1346 #define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
1347 #define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
1348 #define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
1349 #define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
1356 #if defined(QUADSPI)
1360 #define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U)
1361 #define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0
1362 #define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1
1363 #define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL
1371 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1376 #if defined(RCC_CDCCIPR_OCTOSPISEL)
1377 #define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U)
1379 #define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK
1380 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK
1381 #define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0
1382 #define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1
1383 #define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL
1385 #define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U)
1386 #define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK
1387 #define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0
1388 #define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1
1389 #define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL
1402 #define RCC_DSICLKSOURCE_PHY (0x00000000U)
1403 #define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL
1413 #if defined(RCC_D1CCIPR_FMCSEL)
1414 #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U)
1415 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK
1416 #define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0
1417 #define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1
1418 #define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL
1420 #define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U)
1421 #define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK
1423 #define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK
1424 #define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0
1425 #define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1
1426 #define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL
1432 #if defined(FDCAN1) || defined(FDCAN2)
1436 #if defined(RCC_D2CCIP1R_FDCANSEL)
1437 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
1438 #define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0
1439 #define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1
1441 #define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
1442 #define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0
1443 #define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1
1454 #if defined(RCC_D1CCIPR_SDMMCSEL)
1455 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
1456 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL
1458 #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
1459 #define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL
1469 #if defined(RCC_D3CCIPR_ADCSEL_0)
1470 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
1471 #define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0
1472 #define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1
1474 #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
1475 #define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0
1476 #define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1
1485 #if defined(RCC_D2CCIP1R_SWPSEL)
1486 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U)
1487 #define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL
1489 #define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U)
1491 #define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1
1492 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL
1501 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
1502 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U)
1503 #define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL
1505 #define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U)
1507 #define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1
1508 #define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL
1514 #if defined(DFSDM2_BASE)
1518 #define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U)
1520 #define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4
1521 #define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL
1530 #if defined(RCC_D2CCIP1R_SPDIFSEL_0)
1531 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
1532 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0
1533 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1
1534 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL
1536 #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
1537 #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0
1538 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1
1539 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL
1548 #if defined(RCC_D2CCIP2R_CECSEL_0)
1549 #define RCC_CECCLKSOURCE_LSE (0x00000000U)
1550 #define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0
1551 #define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1
1553 #define RCC_CECCLKSOURCE_LSE (0x00000000U)
1554 #define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0
1555 #define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1
1565 #if defined(RCC_D1CCIPR_CKPERSEL_0)
1566 #define RCC_CLKPSOURCE_HSI (0x00000000U)
1567 #define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0
1568 #define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1
1570 #define RCC_CLKPSOURCE_HSI (0x00000000U)
1571 #define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0
1572 #define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1
1581 #define RCC_TIMPRES_DESACTIVATED (0x00000000U)
1582 #define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE
1588 #if defined(DUAL_CORE)
1593 #define RCC_BOOT_C1 RCC_GCR_BOOT_C1
1594 #define RCC_BOOT_C2 RCC_GCR_BOOT_C2
1601 #if defined(DUAL_CORE)
1605 #define RCC_WWDG1 RCC_GCR_WW1RSC
1606 #define RCC_WWDG2 RCC_GCR_WW2RSC
1617 #define RCC_WWDG1 RCC_GCR_WW1RSC
1628 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18
1636 #define RCC_CRS_NONE (0x00000000U)
1637 #define RCC_CRS_TIMEOUT (0x00000001U)
1638 #define RCC_CRS_SYNCOK (0x00000002U)
1639 #define RCC_CRS_SYNCWARN (0x00000004U)
1640 #define RCC_CRS_SYNCERR (0x00000008U)
1641 #define RCC_CRS_SYNCMISS (0x00000010U)
1642 #define RCC_CRS_TRIMOVF (0x00000020U)
1650 #define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U)
1651 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
1652 #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1
1653 #define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)
1663 #define RCC_CRS_SYNC_DIV1 (0x00000000U)
1664 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
1665 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
1666 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
1667 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
1668 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
1669 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
1670 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
1678 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U)
1679 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
1687 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU)
1696 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U)
1704 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U)
1714 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U)
1715 #define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR)
1723 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
1724 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
1725 #define RCC_CRS_IT_ERR CRS_CR_ERRIE
1726 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
1727 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
1728 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
1729 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
1738 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
1739 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
1740 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF
1741 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
1742 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
1743 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
1744 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
1767 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
1768 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
1786 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
1788 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
1795 #define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
1797 #define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
1831 #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
1833 MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
1834 WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
1835 ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
1854 #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
1855 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
1866 #define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
1867 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
1880 #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
1881 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
1889 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
1890 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
1897 #define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
1899 #define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
1917 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
1919 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
1953 #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
1954 do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \
1955 WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
1956 ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
1977 #define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
1988 #define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
1989 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
2002 #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
2003 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
2016 #if defined(RCC_D2CCIP1R_SAI1SEL)
2017 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
2018 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
2020 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
2021 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
2032 #if defined(RCC_D2CCIP1R_SAI1SEL)
2033 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
2035 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
2049 #if defined(RCC_D2CCIP1R_SPDIFSEL)
2050 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
2051 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
2053 #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
2054 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
2061 #if defined(RCC_D2CCIP1R_SPDIFSEL)
2062 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
2064 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
2080 #define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
2081 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
2091 #define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
2105 #define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG
2115 #define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE
2129 #define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
2139 #define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE
2142 #if defined(RCC_CDCCIP1R_SAI2ASEL)
2156 #define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
2157 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
2168 #define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
2171 #if defined(RCC_CDCCIP1R_SAI2BSEL)
2185 #define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
2186 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
2197 #define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
2201 #if defined(SAI4_Block_A)
2214 #define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
2215 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
2225 #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
2228 #if defined(SAI4_Block_B)
2241 #define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
2242 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
2252 #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
2266 #if defined(RCC_D2CCIP2R_I2C123SEL)
2267 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
2268 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
2269 #elif defined(RCC_CDCCIP2R_I2C123SEL)
2270 #define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \
2271 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))
2273 #define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \
2274 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))
2276 #define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG
2288 #if defined(RCC_D2CCIP2R_I2C123SEL)
2289 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
2290 #elif defined(RCC_CDCCIP2R_I2C123SEL)
2291 #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
2293 #define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))
2295 #define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2308 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG
2310 #define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG
2321 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2323 #define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2336 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG
2338 #define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
2349 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2351 #define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2364 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG
2366 #define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
2377 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2379 #define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
2391 #if defined(RCC_D3CCIPR_I2C4SEL)
2392 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
2393 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
2395 #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
2396 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
2406 #if defined(RCC_D3CCIPR_I2C4SEL)
2407 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
2409 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL)))
2422 #define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG
2433 #define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE
2449 #if defined(RCC_D2CCIP2R_USART16SEL)
2450 #define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \
2451 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__))
2452 #elif defined(RCC_CDCCIP2R_USART16910SEL)
2453 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
2454 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
2456 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
2458 #define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
2459 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
2461 #define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG
2475 #if defined(RCC_D2CCIP2R_USART16SEL)
2476 #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
2477 #elif defined(RCC_CDCCIP2R_USART16910SEL)
2478 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
2480 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
2482 #define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))
2484 #define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE
2498 #if defined(RCC_D2CCIP2R_USART28SEL)
2499 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
2500 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
2502 #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
2503 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
2515 #if defined(RCC_D2CCIP2R_USART28SEL)
2516 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
2518 #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
2532 #define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG
2543 #define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE
2556 #define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG
2567 #define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2580 #define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG
2591 #define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2604 #define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG
2615 #define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2628 #define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG
2639 #define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2652 #define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG
2663 #define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE
2676 #define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG
2687 #define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2700 #define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG
2711 #define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE
2725 #define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG
2736 #define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE
2739 #if defined(USART10)
2751 #define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG
2762 #define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE
2776 #if defined (RCC_D3CCIPR_LPUART1SEL)
2777 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
2778 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
2780 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
2781 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
2793 #if defined (RCC_D3CCIPR_LPUART1SEL)
2794 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
2796 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
2810 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
2811 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
2812 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
2814 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
2815 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
2827 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
2828 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
2830 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
2844 #if defined(RCC_D3CCIPR_LPTIM2SEL)
2845 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
2846 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
2848 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
2849 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
2861 #if defined(RCC_D3CCIPR_LPTIM2SEL)
2862 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
2864 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
2877 #if defined(RCC_D3CCIPR_LPTIM345SEL)
2878 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
2879 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
2881 #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
2882 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))
2894 #if defined(RCC_D3CCIPR_LPTIM345SEL)
2895 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
2897 #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
2910 #define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG
2921 #define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
2934 #define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG
2946 #define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
2960 #define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG
2972 #define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE
2975 #if defined(QUADSPI)
2984 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
2985 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
2995 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
2998 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3007 #if defined(RCC_CDCCIPR_OCTOSPISEL)
3008 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
3009 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
3011 #define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
3012 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
3022 #if defined(RCC_CDCCIPR_OCTOSPISEL)
3023 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
3025 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)))
3037 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
3038 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
3046 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
3057 #if defined(RCC_D1CCIPR_FMCSEL)
3058 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
3059 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
3061 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
3062 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
3072 #if defined(RCC_D1CCIPR_FMCSEL)
3073 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
3075 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
3085 #if defined(RCC_D2CCIP2R_USBSEL)
3086 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3087 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
3089 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3090 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
3099 #if defined(RCC_D2CCIP2R_USBSEL)
3100 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
3102 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
3112 #if defined(RCC_D3CCIPR_ADCSEL)
3113 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
3114 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
3116 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
3117 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
3126 #if defined(RCC_D3CCIPR_ADCSEL)
3127 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
3129 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
3138 #if defined(RCC_D2CCIP1R_SWPSEL)
3139 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
3140 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
3142 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
3143 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
3151 #if defined(RCC_D2CCIP1R_SWPSEL)
3152 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
3154 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
3163 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3164 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
3165 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
3167 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
3168 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
3176 #if defined (RCC_D2CCIP1R_DFSDM1SEL)
3177 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
3179 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
3182 #if defined(DFSDM2_BASE)
3189 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
3190 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
3197 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
3208 #if defined(RCC_D2CCIP2R_CECSEL)
3209 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3210 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
3212 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3213 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
3222 #if defined(RCC_D2CCIP2R_CECSEL)
3223 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
3225 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
3235 #if defined(RCC_D1CCIPR_CKPERSEL)
3236 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
3237 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
3239 #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
3240 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
3249 #if defined(RCC_D1CCIPR_CKPERSEL)
3250 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
3252 #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
3255 #if defined(FDCAN1) || defined(FDCAN2)
3263 #if defined(RCC_D2CCIP1R_FDCANSEL)
3264 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
3265 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
3267 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
3268 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
3277 #if defined(RCC_D2CCIP1R_FDCANSEL)
3278 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
3280 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
3297 #if defined(RCC_D2CCIP1R_SPI123SEL)
3298 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
3299 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
3301 #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
3302 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
3313 #if defined(RCC_D2CCIP1R_SPI123SEL)
3314 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
3316 #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
3331 #define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG
3341 #define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3355 #define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG
3365 #define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3379 #define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG
3389 #define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE
3404 #if defined(RCC_D2CCIP1R_SPI45SEL)
3405 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
3406 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
3408 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
3409 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
3421 #if defined(RCC_D2CCIP1R_SPI45SEL)
3422 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
3424 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
3440 #define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG
3451 #define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE
3466 #define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG
3477 #define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE
3497 #if defined(RCC_D3CCIPR_SPI6SEL)
3498 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
3499 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
3501 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
3502 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
3515 #if defined(RCC_D3CCIPR_SPI6SEL)
3516 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
3518 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
3527 #if defined(RCC_D1CCIPR_SDMMCSEL)
3528 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
3529 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
3531 #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
3532 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
3537 #if defined(RCC_D1CCIPR_SDMMCSEL)
3538 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
3540 #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
3552 #if defined(RCC_D2CCIP2R_RNGSEL)
3553 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
3554 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
3556 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
3557 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
3567 #if defined(RCC_D2CCIP2R_RNGSEL)
3568 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
3570 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
3580 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
3581 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
3588 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
3601 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
3602 RCC->CFGR |= (__PRESC__); \
3609 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
3615 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
3621 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
3627 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
3629 #if defined(DUAL_CORE)
3634 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
3640 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
3646 #define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
3652 #define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
3659 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
3666 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
3673 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
3679 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
3685 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
3687 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
3688 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
3695 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
3697 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
3698 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
3705 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
3711 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
3713 #if defined(DUAL_CORE)
3718 #define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
3724 #define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
3730 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
3742 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
3754 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
3765 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
3779 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
3781 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
3782 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
3784 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
3788 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
3805 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
3823 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
3825 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
3826 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
3828 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
3832 WRITE_REG(CRS->ICR, (__FLAG__)); \
3844 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
3850 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
3857 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
3863 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
3875 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
3919 #if defined(DUAL_CORE)
3920 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
3922 #if defined(RCC_GCR_WW1RSC)
3923 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
3960 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
3961 ((VALUE) == RCC_PLL2_DIVQ) || \
3962 ((VALUE) == RCC_PLL2_DIVR))
3964 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
3965 ((VALUE) == RCC_PLL3_DIVQ) || \
3966 ((VALUE) == RCC_PLL3_DIVR))
3968 #if defined(RCC_D2CCIP2R_USART16SEL)
3969 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
3970 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
3971 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
3972 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
3973 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
3974 ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
3976 #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
3977 ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
3978 ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \
3979 ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \
3980 ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \
3981 ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \
3982 ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
3984 #define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE
3987 #if defined(RCC_D2CCIP2R_USART28SEL)
3988 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
3989 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
3990 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
3991 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
3992 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
3993 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
3995 #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
3996 ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
3997 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \
3998 ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \
3999 ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \
4000 ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \
4001 ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
4004 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
4005 ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \
4006 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \
4007 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \
4008 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
4009 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
4011 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
4012 ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \
4013 ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \
4014 ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \
4015 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
4016 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
4018 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
4019 ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \
4020 ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \
4021 ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \
4022 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
4023 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
4025 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
4026 ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \
4027 ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \
4028 ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \
4029 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
4030 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
4032 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
4033 ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \
4034 ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \
4035 ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \
4036 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
4037 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
4039 #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
4040 ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \
4041 ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \
4042 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \
4043 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
4044 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
4046 #define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
4047 ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \
4048 ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \
4049 ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \
4050 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
4051 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
4053 #define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
4054 ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \
4055 ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \
4056 ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \
4057 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
4058 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
4061 #define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
4062 ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \
4063 ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \
4064 ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \
4065 ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \
4066 ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
4069 #if defined(USART10)
4070 #define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
4071 ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \
4072 ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \
4073 ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \
4074 ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \
4075 ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
4078 #define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
4079 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \
4080 ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \
4081 ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \
4082 ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \
4083 ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
4086 #define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \
4087 ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \
4088 ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \
4089 ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI))
4091 #define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE
4093 #define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \
4094 ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \
4095 ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
4096 ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
4099 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \
4100 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
4101 ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
4102 ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
4104 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \
4105 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
4106 ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
4107 ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
4109 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \
4110 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
4111 ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
4112 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
4114 #define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \
4115 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \
4116 ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
4117 ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
4120 #define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \
4121 ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \
4122 ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \
4123 ((SOURCE) == RCC_I2C5CLKSOURCE_CSI))
4126 #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
4127 ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \
4128 ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \
4129 ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
4132 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
4133 ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
4136 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
4137 ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
4138 ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
4140 #define IS_RCC_SAI1CLK(__SOURCE__) \
4141 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
4142 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
4143 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
4144 ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
4145 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
4148 #define IS_RCC_SAI23CLK(__SOURCE__) \
4149 (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \
4150 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
4151 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
4152 ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
4153 ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
4155 #define IS_RCC_SAI2CLK(__SOURCE__) \
4156 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
4157 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
4158 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
4159 ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
4160 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
4163 #define IS_RCC_SAI3CLK(__SOURCE__) \
4164 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \
4165 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
4166 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
4167 ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
4168 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
4171 #if defined(RCC_CDCCIP1R_SAI2ASEL)
4172 #define IS_RCC_SAI2ACLK(__SOURCE__) \
4173 (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \
4174 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
4175 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
4176 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
4177 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
4178 ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
4181 #if defined(RCC_CDCCIP1R_SAI2BSEL)
4182 #define IS_RCC_SAI2BCLK(__SOURCE__) \
4183 (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \
4184 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
4185 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
4186 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
4187 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
4188 ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
4191 #define IS_RCC_SPI123CLK(__SOURCE__) \
4192 (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \
4193 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
4194 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
4195 ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
4196 ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
4198 #define IS_RCC_SPI1CLK(__SOURCE__) \
4199 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \
4200 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
4201 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
4202 ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
4203 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
4205 #define IS_RCC_SPI2CLK(__SOURCE__) \
4206 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \
4207 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
4208 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
4209 ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
4210 ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
4212 #define IS_RCC_SPI3CLK(__SOURCE__) \
4213 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \
4214 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
4215 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
4216 ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
4217 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
4219 #define IS_RCC_SPI45CLK(__SOURCE__) \
4220 (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \
4221 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \
4222 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \
4223 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \
4224 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \
4225 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
4227 #define IS_RCC_SPI4CLK(__SOURCE__) \
4228 (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \
4229 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \
4230 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \
4231 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \
4232 ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \
4233 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
4235 #define IS_RCC_SPI5CLK(__SOURCE__) \
4236 (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
4237 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \
4238 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \
4239 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \
4240 ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \
4241 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
4243 #if defined(RCC_D3CCIPR_SPI6SEL)
4244 #define IS_RCC_SPI6CLK(__SOURCE__) \
4245 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
4246 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
4247 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
4248 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
4249 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
4250 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
4252 #define IS_RCC_SPI6CLK(__SOURCE__) \
4253 (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
4254 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \
4255 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \
4256 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
4257 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
4258 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \
4259 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
4263 #define IS_RCC_SAI4ACLK(__SOURCE__) \
4264 (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \
4265 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
4266 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
4267 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
4268 ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
4270 #define IS_RCC_SAI4BCLK(__SOURCE__) \
4271 (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \
4272 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
4273 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
4274 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
4275 ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
4278 #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
4279 #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
4280 #define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4281 #define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4282 #define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4284 #define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
4285 #define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
4286 #define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4287 #define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4288 #define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
4290 #define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \
4291 ((VALUE) == RCC_PLL2VCIRANGE_1) || \
4292 ((VALUE) == RCC_PLL2VCIRANGE_2) || \
4293 ((VALUE) == RCC_PLL2VCIRANGE_3))
4295 #define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \
4296 ((VALUE) == RCC_PLL3VCIRANGE_1) || \
4297 ((VALUE) == RCC_PLL3VCIRANGE_2) || \
4298 ((VALUE) == RCC_PLL3VCIRANGE_3))
4300 #define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \
4301 ((VALUE) == RCC_PLL2VCOMEDIUM))
4303 #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \
4304 ((VALUE) == RCC_PLL3VCOMEDIUM))
4306 #define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
4307 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \
4308 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \
4309 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \
4310 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
4311 ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
4313 #define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
4314 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \
4315 ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \
4316 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \
4317 ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \
4318 ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
4320 #define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
4321 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \
4322 ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \
4323 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \
4324 ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \
4325 ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
4327 #define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \
4328 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \
4329 ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \
4330 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \
4331 ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \
4332 ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
4335 #define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
4336 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \
4337 ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \
4338 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \
4339 ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \
4340 ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
4344 #define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
4345 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \
4346 ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \
4347 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \
4348 ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \
4349 ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
4352 #if defined(QUADSPI)
4353 #define IS_RCC_QSPICLK(__SOURCE__) \
4354 (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \
4355 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \
4356 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \
4357 ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
4360 #if defined(OCTOSPI1) || defined(OCTOSPI1)
4361 #define IS_RCC_OSPICLK(__SOURCE__) \
4362 (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \
4363 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \
4364 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \
4365 ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
4369 #define IS_RCC_DSICLK(__SOURCE__) \
4370 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \
4371 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
4374 #define IS_RCC_FMCCLK(__SOURCE__) \
4375 (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \
4376 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \
4377 ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \
4378 ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
4380 #if defined(FDCAN1) || defined(FDCAN2)
4381 #define IS_RCC_FDCANCLK(__SOURCE__) \
4382 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
4383 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
4384 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
4387 #define IS_RCC_SDMMC(__SOURCE__) \
4388 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \
4389 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
4391 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
4392 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
4393 ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
4395 #define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
4396 ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
4398 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
4399 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
4401 #if defined(DFSDM2_BASE)
4402 #define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
4403 ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
4406 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \
4407 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
4408 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
4409 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
4411 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
4412 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
4413 ((SOURCE) == RCC_CECCLKSOURCE_CSI))
4415 #define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \
4416 ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
4417 ((SOURCE) == RCC_CLKPSOURCE_HSE))
4418 #define IS_RCC_TIMPRES(VALUE) \
4419 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
4420 ((VALUE) == RCC_TIMPRES_ACTIVATED))
4422 #if defined(DUAL_CORE)
4423 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \
4424 ((CORE) == RCC_BOOT_C2))
4427 #if defined(DUAL_CORE)
4428 #define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \
4429 ((WWDG) == RCC_WWDG2))
4431 #define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
4435 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
4436 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
4437 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
4438 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
4440 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
4441 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
4442 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
4443 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
4445 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
4446 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
4448 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
4450 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
4452 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
4454 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
4455 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
void HAL_RCCEx_EnableLSECSS(void)
uint32_t HSI48CalibrationValue
HAL_StatusTypeDef
HAL Status structures definition
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
uint32_t PLL3_Q_Frequency
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
PLL3 Clock structure definition.
#define I2c1235ClockSelection
uint32_t Spi123ClockSelection
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_CRS Init structure definition.
uint32_t Swpmi1ClockSelection
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
uint32_t PLL2_P_Frequency
void HAL_RCCEx_CRS_SyncOkCallback(void)
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
uint32_t PLL1_Q_Frequency
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
uint32_t Lptim345ClockSelection
void HAL_RCCEx_CRS_SyncWarnCallback(void)
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
uint32_t PLL1_R_Frequency
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
uint32_t Spi6ClockSelection
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
uint32_t Usart234578ClockSelection
uint32_t PLL3_P_Frequency
uint32_t SdmmcClockSelection
uint32_t PLL2_R_Frequency
uint32_t Dfsdm1ClockSelection
uint32_t Lptim2ClockSelection
RCC PLL2 Clocks structure definition.
uint32_t Usart16ClockSelection
void HAL_RCCEx_EnableLSECSS_IT(void)
uint32_t SpdifrxClockSelection
uint32_t CkperClockSelection
uint32_t UsbClockSelection
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
RCC PLL1 Clocks structure definition.
uint32_t PLL2_Q_Frequency
uint32_t Spi45ClockSelection
void HAL_RCCEx_LSECSS_Callback(void)
RCC PLL3 Clocks structure definition.
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PLL2 Clock structure definition.
uint32_t FmcClockSelection
uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
uint32_t Lpuart1ClockSelection
uint32_t PLL3_R_Frequency
void HAL_RCCEx_CRS_IRQHandler(void)
uint32_t I2c123ClockSelection
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
uint32_t PLL1_P_Frequency
RCC extended clocks structure definition.
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
uint32_t AdcClockSelection
uint32_t RngClockSelection
void HAL_RCCEx_LSECSS_IRQHandler(void)
void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
void HAL_RCCEx_DisableLSECSS(void)
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)