21 #ifndef STM32H7xx_HAL_TIM_H
22 #define STM32H7xx_HAL_TIM_H
59 uint32_t ClockDivision;
62 uint32_t RepetitionCounter;
71 uint32_t AutoReloadPreload;
102 uint32_t OCNIdleState;
121 uint32_t OCNPolarity;
125 uint32_t OCIdleState;
129 uint32_t OCNIdleState;
136 uint32_t ICSelection;
151 uint32_t ICSelection;
154 uint32_t ICPrescaler;
166 uint32_t EncoderMode;
169 uint32_t IC1Polarity;
172 uint32_t IC1Selection;
175 uint32_t IC1Prescaler;
181 uint32_t IC2Polarity;
184 uint32_t IC2Selection;
187 uint32_t IC2Prescaler;
199 uint32_t ClockSource;
201 uint32_t ClockPolarity;
203 uint32_t ClockPrescaler;
205 uint32_t ClockFilter;
214 uint32_t ClearInputState;
216 uint32_t ClearInputSource;
218 uint32_t ClearInputPolarity;
220 uint32_t ClearInputPrescaler;
222 uint32_t ClearInputFilter;
233 uint32_t MasterOutputTrigger;
235 uint32_t MasterOutputTrigger2;
237 uint32_t MasterSlaveMode;
253 uint32_t InputTrigger;
255 uint32_t TriggerPolarity;
257 uint32_t TriggerPrescaler;
259 uint32_t TriggerFilter;
271 uint32_t OffStateRunMode;
273 uint32_t OffStateIDLEMode;
281 uint32_t BreakPolarity;
283 uint32_t BreakFilter;
285 uint32_t Break2State;
287 uint32_t Break2Polarity;
289 uint32_t Break2Filter;
291 uint32_t AutomaticOutput;
344 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
345 typedef struct __TIM_HandleTypeDef
361 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
362 void (* Base_MspInitCallback)(
struct __TIM_HandleTypeDef *htim);
363 void (* Base_MspDeInitCallback)(
struct __TIM_HandleTypeDef *htim);
364 void (* IC_MspInitCallback)(
struct __TIM_HandleTypeDef *htim);
365 void (* IC_MspDeInitCallback)(
struct __TIM_HandleTypeDef *htim);
366 void (* OC_MspInitCallback)(
struct __TIM_HandleTypeDef *htim);
367 void (* OC_MspDeInitCallback)(
struct __TIM_HandleTypeDef *htim);
368 void (* PWM_MspInitCallback)(
struct __TIM_HandleTypeDef *htim);
369 void (* PWM_MspDeInitCallback)(
struct __TIM_HandleTypeDef *htim);
370 void (* OnePulse_MspInitCallback)(
struct __TIM_HandleTypeDef *htim);
371 void (* OnePulse_MspDeInitCallback)(
struct __TIM_HandleTypeDef *htim);
372 void (* Encoder_MspInitCallback)(
struct __TIM_HandleTypeDef *htim);
373 void (* Encoder_MspDeInitCallback)(
struct __TIM_HandleTypeDef *htim);
374 void (* HallSensor_MspInitCallback)(
struct __TIM_HandleTypeDef *htim);
375 void (* HallSensor_MspDeInitCallback)(
struct __TIM_HandleTypeDef *htim);
376 void (* PeriodElapsedCallback)(
struct __TIM_HandleTypeDef *htim);
377 void (* PeriodElapsedHalfCpltCallback)(
struct __TIM_HandleTypeDef *htim);
378 void (* TriggerCallback)(
struct __TIM_HandleTypeDef *htim);
379 void (* TriggerHalfCpltCallback)(
struct __TIM_HandleTypeDef *htim);
380 void (* IC_CaptureCallback)(
struct __TIM_HandleTypeDef *htim);
381 void (* IC_CaptureHalfCpltCallback)(
struct __TIM_HandleTypeDef *htim);
382 void (* OC_DelayElapsedCallback)(
struct __TIM_HandleTypeDef *htim);
383 void (* PWM_PulseFinishedCallback)(
struct __TIM_HandleTypeDef *htim);
384 void (* PWM_PulseFinishedHalfCpltCallback)(
struct __TIM_HandleTypeDef *htim);
385 void (* ErrorCallback)(
struct __TIM_HandleTypeDef *htim);
386 void (* CommutationCallback)(
struct __TIM_HandleTypeDef *htim);
387 void (* CommutationHalfCpltCallback)(
struct __TIM_HandleTypeDef *htim);
388 void (* BreakCallback)(
struct __TIM_HandleTypeDef *htim);
389 void (* Break2Callback)(
struct __TIM_HandleTypeDef *htim);
393 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
399 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U
400 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U
401 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U
402 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U
403 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U
404 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U
405 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U
406 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U
407 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U
408 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U
409 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU
410 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU
411 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU
412 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU
413 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU
414 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU
415 , HAL_TIM_TRIGGER_CB_ID = 0x10U
416 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U
418 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U
419 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U
420 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U
421 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U
422 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U
423 , HAL_TIM_ERROR_CB_ID = 0x17U
424 , HAL_TIM_COMMUTATION_CB_ID = 0x18U
425 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U
426 , HAL_TIM_BREAK_CB_ID = 0x1AU
427 , HAL_TIM_BREAK2_CB_ID = 0x1BU
428 } HAL_TIM_CallbackIDTypeDef;
450 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
451 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
459 #define TIM_DMABASE_CR1 0x00000000U
460 #define TIM_DMABASE_CR2 0x00000001U
461 #define TIM_DMABASE_SMCR 0x00000002U
462 #define TIM_DMABASE_DIER 0x00000003U
463 #define TIM_DMABASE_SR 0x00000004U
464 #define TIM_DMABASE_EGR 0x00000005U
465 #define TIM_DMABASE_CCMR1 0x00000006U
466 #define TIM_DMABASE_CCMR2 0x00000007U
467 #define TIM_DMABASE_CCER 0x00000008U
468 #define TIM_DMABASE_CNT 0x00000009U
469 #define TIM_DMABASE_PSC 0x0000000AU
470 #define TIM_DMABASE_ARR 0x0000000BU
471 #define TIM_DMABASE_RCR 0x0000000CU
472 #define TIM_DMABASE_CCR1 0x0000000DU
473 #define TIM_DMABASE_CCR2 0x0000000EU
474 #define TIM_DMABASE_CCR3 0x0000000FU
475 #define TIM_DMABASE_CCR4 0x00000010U
476 #define TIM_DMABASE_BDTR 0x00000011U
477 #define TIM_DMABASE_DCR 0x00000012U
478 #define TIM_DMABASE_DMAR 0x00000013U
479 #define TIM_DMABASE_CCMR3 0x00000015U
480 #define TIM_DMABASE_CCR5 0x00000016U
481 #define TIM_DMABASE_CCR6 0x00000017U
482 #if defined(TIM_BREAK_INPUT_SUPPORT)
483 #define TIM_DMABASE_AF1 0x00000018U
484 #define TIM_DMABASE_AF2 0x00000019U
486 #define TIM_DMABASE_TISEL 0x0000001AU
494 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
495 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
496 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
497 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
498 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
499 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
500 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
501 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
502 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
510 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
511 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
512 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
520 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
521 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U
529 #define TIM_ETRPRESCALER_DIV1 0x00000000U
530 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
531 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
532 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
540 #define TIM_COUNTERMODE_UP 0x00000000U
541 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
542 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
543 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
544 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
552 #define TIM_UIFREMAP_DISABLE 0x00000000U
553 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP
561 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
562 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
563 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
571 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
572 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
580 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
581 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
590 #define TIM_OCFAST_DISABLE 0x00000000U
591 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
599 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
600 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
608 #define TIM_OCPOLARITY_HIGH 0x00000000U
609 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P
617 #define TIM_OCNPOLARITY_HIGH 0x00000000U
618 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
626 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1
627 #define TIM_OCIDLESTATE_RESET 0x00000000U
635 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
636 #define TIM_OCNIDLESTATE_RESET 0x00000000U
644 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
645 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
646 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
654 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
655 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
663 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
665 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
667 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
675 #define TIM_ICPSC_DIV1 0x00000000U
676 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
677 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
678 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
686 #define TIM_OPMODE_SINGLE TIM_CR1_OPM
687 #define TIM_OPMODE_REPETITIVE 0x00000000U
695 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
696 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
697 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
705 #define TIM_IT_UPDATE TIM_DIER_UIE
706 #define TIM_IT_CC1 TIM_DIER_CC1IE
707 #define TIM_IT_CC2 TIM_DIER_CC2IE
708 #define TIM_IT_CC3 TIM_DIER_CC3IE
709 #define TIM_IT_CC4 TIM_DIER_CC4IE
710 #define TIM_IT_COM TIM_DIER_COMIE
711 #define TIM_IT_TRIGGER TIM_DIER_TIE
712 #define TIM_IT_BREAK TIM_DIER_BIE
720 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS
721 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
729 #define TIM_DMA_UPDATE TIM_DIER_UDE
730 #define TIM_DMA_CC1 TIM_DIER_CC1DE
731 #define TIM_DMA_CC2 TIM_DIER_CC2DE
732 #define TIM_DMA_CC3 TIM_DIER_CC3DE
733 #define TIM_DMA_CC4 TIM_DIER_CC4DE
734 #define TIM_DMA_COM TIM_DIER_COMDE
735 #define TIM_DMA_TRIGGER TIM_DIER_TDE
743 #define TIM_FLAG_UPDATE TIM_SR_UIF
744 #define TIM_FLAG_CC1 TIM_SR_CC1IF
745 #define TIM_FLAG_CC2 TIM_SR_CC2IF
746 #define TIM_FLAG_CC3 TIM_SR_CC3IF
747 #define TIM_FLAG_CC4 TIM_SR_CC4IF
748 #define TIM_FLAG_CC5 TIM_SR_CC5IF
749 #define TIM_FLAG_CC6 TIM_SR_CC6IF
750 #define TIM_FLAG_COM TIM_SR_COMIF
751 #define TIM_FLAG_TRIGGER TIM_SR_TIF
752 #define TIM_FLAG_BREAK TIM_SR_BIF
753 #define TIM_FLAG_BREAK2 TIM_SR_B2IF
754 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
755 #define TIM_FLAG_CC1OF TIM_SR_CC1OF
756 #define TIM_FLAG_CC2OF TIM_SR_CC2OF
757 #define TIM_FLAG_CC3OF TIM_SR_CC3OF
758 #define TIM_FLAG_CC4OF TIM_SR_CC4OF
766 #define TIM_CHANNEL_1 0x00000000U
767 #define TIM_CHANNEL_2 0x00000004U
768 #define TIM_CHANNEL_3 0x00000008U
769 #define TIM_CHANNEL_4 0x0000000CU
770 #define TIM_CHANNEL_5 0x00000010U
771 #define TIM_CHANNEL_6 0x00000014U
772 #define TIM_CHANNEL_ALL 0x0000003CU
780 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
781 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
782 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
783 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
784 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
785 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
786 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
787 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
788 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
789 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
790 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4
791 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5
792 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6
793 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7
794 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8
802 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
803 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
804 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
805 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
806 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
814 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
815 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
816 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
817 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
825 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
826 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
834 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
835 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
836 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
837 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
845 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR
846 #define TIM_OSSR_DISABLE 0x00000000U
854 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI
855 #define TIM_OSSI_DISABLE 0x00000000U
862 #define TIM_LOCKLEVEL_OFF 0x00000000U
863 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
864 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
865 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
873 #define TIM_BREAK_ENABLE TIM_BDTR_BKE
874 #define TIM_BREAK_DISABLE 0x00000000U
882 #define TIM_BREAKPOLARITY_LOW 0x00000000U
883 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
891 #define TIM_BREAK2_DISABLE 0x00000000U
892 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E
900 #define TIM_BREAK2POLARITY_LOW 0x00000000U
901 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
909 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
910 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
919 #define TIM_GROUPCH5_NONE 0x00000000U
920 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
921 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
922 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
930 #define TIM_TRGO_RESET 0x00000000U
931 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0
932 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1
933 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
934 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2
935 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
936 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
937 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
945 #define TIM_TRGO2_RESET 0x00000000U
946 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
947 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
948 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
949 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
950 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
951 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
952 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
953 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
954 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
955 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
956 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
957 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
958 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
959 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
960 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
968 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
969 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
977 #define TIM_SLAVEMODE_DISABLE 0x00000000U
978 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
979 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
980 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
981 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
982 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
990 #define TIM_OCMODE_TIMING 0x00000000U
991 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
992 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
993 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
994 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
995 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
996 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
997 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
998 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
999 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
1000 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
1001 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
1002 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
1003 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M
1011 #define TIM_TS_ITR0 0x00000000U
1012 #define TIM_TS_ITR1 TIM_SMCR_TS_0
1013 #define TIM_TS_ITR2 TIM_SMCR_TS_1
1014 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
1015 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2
1016 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
1017 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
1018 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
1019 #define TIM_TS_ITR4 (TIM_SMCR_TS_3)
1020 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)
1021 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
1022 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)
1023 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
1024 #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
1025 #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
1026 #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)
1027 #define TIM_TS_ITR12 (TIM_SMCR_TS_4)
1028 #define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)
1029 #define TIM_TS_NONE 0x0000FFFFU
1037 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
1038 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
1039 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
1040 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
1041 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
1049 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
1050 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
1051 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
1052 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
1060 #define TIM_TI1SELECTION_CH1 0x00000000U
1061 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
1069 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
1070 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
1071 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
1072 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
1073 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
1074 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
1075 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
1076 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
1077 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
1078 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
1079 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
1080 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
1081 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
1082 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
1083 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
1084 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
1085 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
1086 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
1094 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
1095 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
1096 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
1097 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
1098 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
1099 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
1100 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
1108 #define TIM_CCx_ENABLE 0x00000001U
1109 #define TIM_CCx_DISABLE 0x00000000U
1110 #define TIM_CCxN_ENABLE 0x00000004U
1111 #define TIM_CCxN_DISABLE 0x00000000U
1119 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
1120 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
1121 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
1122 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
1141 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1142 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1143 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1144 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1145 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1146 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1147 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1148 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1149 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1150 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1151 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1152 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1153 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1154 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1155 (__HANDLE__)->Base_MspInitCallback = NULL; \
1156 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1157 (__HANDLE__)->IC_MspInitCallback = NULL; \
1158 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1159 (__HANDLE__)->OC_MspInitCallback = NULL; \
1160 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1161 (__HANDLE__)->PWM_MspInitCallback = NULL; \
1162 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1163 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1164 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1165 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1166 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1167 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1168 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1171 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1172 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1173 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1174 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1175 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1176 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1177 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1178 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1179 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1180 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1181 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1182 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1183 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1192 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1199 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1206 #define __HAL_TIM_DISABLE(__HANDLE__) \
1208 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1210 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1212 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1223 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1225 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1227 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1229 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1240 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1256 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1272 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1287 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1302 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1326 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1350 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1367 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1368 == (__INTERRUPT__)) ? SET : RESET)
1384 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1393 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
1401 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
1409 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
1418 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1426 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1436 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1443 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1451 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1453 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1454 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1462 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1474 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1476 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1477 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1478 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1489 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1508 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1510 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1511 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1529 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1530 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1531 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1532 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1533 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1549 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1550 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1551 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1552 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1553 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1554 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1555 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1570 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1571 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1572 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1573 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1574 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1575 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1576 ((__HANDLE__)->Instance->CCR6))
1591 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1592 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1593 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1594 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1595 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1596 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1597 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1612 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1613 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1614 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1615 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1616 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
1617 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
1618 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
1637 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1638 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1639 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1640 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1641 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
1642 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
1643 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
1662 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1663 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1664 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1665 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1666 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
1667 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
1668 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
1678 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1691 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1708 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1710 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1711 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1725 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1726 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1736 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1737 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1739 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1740 ((__BASE__) == TIM_DMABASE_CR2) || \
1741 ((__BASE__) == TIM_DMABASE_SMCR) || \
1742 ((__BASE__) == TIM_DMABASE_DIER) || \
1743 ((__BASE__) == TIM_DMABASE_SR) || \
1744 ((__BASE__) == TIM_DMABASE_EGR) || \
1745 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1746 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1747 ((__BASE__) == TIM_DMABASE_CCER) || \
1748 ((__BASE__) == TIM_DMABASE_CNT) || \
1749 ((__BASE__) == TIM_DMABASE_PSC) || \
1750 ((__BASE__) == TIM_DMABASE_ARR) || \
1751 ((__BASE__) == TIM_DMABASE_RCR) || \
1752 ((__BASE__) == TIM_DMABASE_CCR1) || \
1753 ((__BASE__) == TIM_DMABASE_CCR2) || \
1754 ((__BASE__) == TIM_DMABASE_CCR3) || \
1755 ((__BASE__) == TIM_DMABASE_CCR4) || \
1756 ((__BASE__) == TIM_DMABASE_BDTR) || \
1757 ((__BASE__) == TIM_DMABASE_CCMR3) || \
1758 ((__BASE__) == TIM_DMABASE_CCR5) || \
1759 ((__BASE__) == TIM_DMABASE_CCR6) || \
1760 ((__BASE__) == TIM_DMABASE_AF1) || \
1761 ((__BASE__) == TIM_DMABASE_AF2) || \
1762 ((__BASE__) == TIM_DMABASE_TISEL))
1765 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1767 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1768 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1769 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1770 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1771 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1773 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
1774 ((__MODE__) == TIM_UIFREMAP_ENALE))
1776 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1777 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1778 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1780 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1781 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1783 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1784 ((__STATE__) == TIM_OCFAST_ENABLE))
1786 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1787 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1789 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1790 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1792 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1793 ((__STATE__) == TIM_OCIDLESTATE_RESET))
1795 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1796 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1798 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
1799 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1801 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1802 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1803 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1805 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1806 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1807 ((__SELECTION__) == TIM_ICSELECTION_TRC))
1809 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1810 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1811 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1812 ((__PRESCALER__) == TIM_ICPSC_DIV8))
1814 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1815 ((__MODE__) == TIM_OPMODE_REPETITIVE))
1817 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1818 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1819 ((__MODE__) == TIM_ENCODERMODE_TI12))
1821 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1823 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1824 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1825 ((__CHANNEL__) == TIM_CHANNEL_3) || \
1826 ((__CHANNEL__) == TIM_CHANNEL_4) || \
1827 ((__CHANNEL__) == TIM_CHANNEL_5) || \
1828 ((__CHANNEL__) == TIM_CHANNEL_6) || \
1829 ((__CHANNEL__) == TIM_CHANNEL_ALL))
1831 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1832 ((__CHANNEL__) == TIM_CHANNEL_2))
1834 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1835 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1836 ((__CHANNEL__) == TIM_CHANNEL_3))
1838 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1839 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1840 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1841 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1842 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1843 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1844 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1845 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1846 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1847 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1849 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1850 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1851 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1852 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1853 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1855 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1856 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1857 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1858 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1860 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1862 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1863 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1865 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1866 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1867 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1868 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1870 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1872 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1873 ((__STATE__) == TIM_OSSR_DISABLE))
1875 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1876 ((__STATE__) == TIM_OSSI_DISABLE))
1878 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1879 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1880 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1881 ((__LEVEL__) == TIM_LOCKLEVEL_3))
1883 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1886 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1887 ((__STATE__) == TIM_BREAK_DISABLE))
1889 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1890 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1892 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1893 ((__STATE__) == TIM_BREAK2_DISABLE))
1895 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1896 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1898 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1899 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1901 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1903 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1904 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1905 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1906 ((__SOURCE__) == TIM_TRGO_OC1) || \
1907 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1908 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1909 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1910 ((__SOURCE__) == TIM_TRGO_OC4REF))
1912 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1913 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1914 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1915 ((__SOURCE__) == TIM_TRGO2_OC1) || \
1916 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1917 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1918 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1919 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1920 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1921 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1922 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1923 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1924 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1925 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1926 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1927 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
1928 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1930 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1931 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1933 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1934 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1935 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1936 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1937 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
1938 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1940 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1941 ((__MODE__) == TIM_OCMODE_PWM2) || \
1942 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
1943 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
1944 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
1945 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
1947 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1948 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1949 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1950 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1951 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1952 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
1953 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
1954 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
1956 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1957 ((__SELECTION__) == TIM_TS_ITR1) || \
1958 ((__SELECTION__) == TIM_TS_ITR2) || \
1959 ((__SELECTION__) == TIM_TS_ITR3) || \
1960 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1961 ((__SELECTION__) == TIM_TS_TI1FP1) || \
1962 ((__SELECTION__) == TIM_TS_TI2FP2) || \
1963 ((__SELECTION__) == TIM_TS_ETRF) || \
1964 ((__SELECTION__) == TIM_TS_ITR4) || \
1965 ((__SELECTION__) == TIM_TS_ITR5) || \
1966 ((__SELECTION__) == TIM_TS_ITR6) || \
1967 ((__SELECTION__) == TIM_TS_ITR7) || \
1968 ((__SELECTION__) == TIM_TS_ITR8) || \
1969 ((__SELECTION__) == TIM_TS_ITR12) || \
1970 ((__SELECTION__) == TIM_TS_ITR13))
1972 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1973 ((__SELECTION__) == TIM_TS_ITR1) || \
1974 ((__SELECTION__) == TIM_TS_ITR2) || \
1975 ((__SELECTION__) == TIM_TS_ITR3) || \
1976 ((__SELECTION__) == TIM_TS_ITR4) || \
1977 ((__SELECTION__) == TIM_TS_ITR5) || \
1978 ((__SELECTION__) == TIM_TS_ITR6) || \
1979 ((__SELECTION__) == TIM_TS_ITR7) || \
1980 ((__SELECTION__) == TIM_TS_ITR8) || \
1981 ((__SELECTION__) == TIM_TS_ITR12) || \
1982 ((__SELECTION__) == TIM_TS_ITR13) || \
1983 ((__SELECTION__) == TIM_TS_NONE))
1985 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1986 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1987 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1988 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1989 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1991 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1992 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1993 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1994 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1996 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1998 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1999 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
2001 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
2002 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
2003 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
2004 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
2005 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
2006 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
2007 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
2008 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
2009 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
2010 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
2011 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
2012 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
2013 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
2014 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
2015 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
2016 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
2017 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
2018 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
2020 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
2022 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2024 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
2026 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
2027 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
2028 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
2029 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2031 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
2032 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2034 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
2035 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
2036 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
2037 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
2038 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
2040 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
2041 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
2042 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
2043 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
2044 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
2046 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
2047 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
2048 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
2049 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
2050 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
2052 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
2053 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
2054 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
2055 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
2056 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
2058 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
2059 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
2060 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
2061 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
2062 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
2063 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
2064 (__HANDLE__)->ChannelState[5])
2066 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2067 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
2068 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
2069 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
2070 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
2071 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
2072 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
2074 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
2075 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
2076 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
2077 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
2078 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
2079 (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
2080 (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
2083 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
2084 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
2085 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
2086 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
2087 (__HANDLE__)->ChannelNState[3])
2089 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2090 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
2091 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
2092 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
2093 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
2095 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
2096 (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
2097 (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
2098 (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
2099 (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
2239 uint32_t *pData2, uint16_t Length);
2264 uint32_t OutputChannel, uint32_t InputChannel);
2272 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2274 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2275 uint32_t DataLength);
2278 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2280 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2281 uint32_t DataLength);
2306 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2308 pTIM_CallbackTypeDef pCallback);
2349 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2357 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)