Header file of DMA HAL module. More...
Go to the source code of this file.
Classes | |
struct | __DMA_HandleTypeDef |
DMA handle Structure definition. More... | |
struct | DMA_InitTypeDef |
DMA Configuration Structure definition. More... | |
Macros | |
#define | __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__))) |
#define | __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__))) |
#define | __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__)))) |
#define | __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__) |
Returns the current BDMA Channel Global interrupt flag. More... | |
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) |
Clear the DMA Stream pending flags. More... | |
#define | __HAL_DMA_DISABLE(__HANDLE__) |
Disable the specified DMA Stream. More... | |
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) |
Disable the specified DMA Stream interrupts. More... | |
#define | __HAL_DMA_ENABLE(__HANDLE__) |
Enable the specified DMA Stream. More... | |
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) |
Enable the specified DMA Stream interrupts. More... | |
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) |
Returns the number of remaining data units in the current DMAy Streamx transfer. More... | |
#define | __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__) |
Return the current DMA Stream direct mode error flag. More... | |
#define | __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__) |
Return the current DMA Stream FIFO error flag. More... | |
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) |
Get the DMA Stream pending flags. More... | |
#define | __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) |
Return the current DMA Stream FIFO filled level. More... | |
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) |
Return the current DMA Stream half transfer complete flag. More... | |
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) |
Check whether the specified DMA Stream interrupt is enabled or not. More... | |
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) |
Return the current DMA Stream transfer complete flag. More... | |
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) |
Return the current DMA Stream transfer error flag. More... | |
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
Reset DMA handle state. More... | |
#define | __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) |
Writes the number of data units to be transferred on the DMA Stream. More... | |
#define | __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) |
#define | __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) |
#define | __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) |
#define | BDMA_FLAG_GL0 ((uint32_t)0x00000001) |
#define | BDMA_FLAG_GL1 ((uint32_t)0x00000010) |
#define | BDMA_FLAG_GL2 ((uint32_t)0x00000100) |
#define | BDMA_FLAG_GL3 ((uint32_t)0x00001000) |
#define | BDMA_FLAG_GL4 ((uint32_t)0x00010000) |
#define | BDMA_FLAG_GL5 ((uint32_t)0x00100000) |
#define | BDMA_FLAG_GL6 ((uint32_t)0x01000000) |
#define | BDMA_FLAG_GL7 ((uint32_t)0x10000000) |
#define | BDMA_FLAG_HT0 ((uint32_t)0x00000004) |
#define | BDMA_FLAG_HT1 ((uint32_t)0x00000040) |
#define | BDMA_FLAG_HT2 ((uint32_t)0x00000400) |
#define | BDMA_FLAG_HT3 ((uint32_t)0x00004000) |
#define | BDMA_FLAG_HT4 ((uint32_t)0x00040000) |
#define | BDMA_FLAG_HT5 ((uint32_t)0x00400000) |
#define | BDMA_FLAG_HT6 ((uint32_t)0x04000000) |
#define | BDMA_FLAG_HT7 ((uint32_t)0x40000000) |
#define | BDMA_FLAG_TC0 ((uint32_t)0x00000002) |
#define | BDMA_FLAG_TC1 ((uint32_t)0x00000020) |
#define | BDMA_FLAG_TC2 ((uint32_t)0x00000200) |
#define | BDMA_FLAG_TC3 ((uint32_t)0x00002000) |
#define | BDMA_FLAG_TC4 ((uint32_t)0x00020000) |
#define | BDMA_FLAG_TC5 ((uint32_t)0x00200000) |
#define | BDMA_FLAG_TC6 ((uint32_t)0x02000000) |
#define | BDMA_FLAG_TC7 ((uint32_t)0x20000000) |
#define | BDMA_FLAG_TE0 ((uint32_t)0x00000008) |
#define | BDMA_FLAG_TE1 ((uint32_t)0x00000080) |
#define | BDMA_FLAG_TE2 ((uint32_t)0x00000800) |
#define | BDMA_FLAG_TE3 ((uint32_t)0x00008000) |
#define | BDMA_FLAG_TE4 ((uint32_t)0x00080000) |
#define | BDMA_FLAG_TE5 ((uint32_t)0x00800000) |
#define | BDMA_FLAG_TE6 ((uint32_t)0x08000000) |
#define | BDMA_FLAG_TE7 ((uint32_t)0x80000000) |
#define | BDMA_REQUEST_GENERATOR0 1U |
#define | BDMA_REQUEST_GENERATOR1 2U |
#define | BDMA_REQUEST_GENERATOR2 3U |
#define | BDMA_REQUEST_GENERATOR3 4U |
#define | BDMA_REQUEST_GENERATOR4 5U |
#define | BDMA_REQUEST_GENERATOR5 6U |
#define | BDMA_REQUEST_GENERATOR6 7U |
#define | BDMA_REQUEST_GENERATOR7 8U |
#define | BDMA_REQUEST_I2C4_RX 13U |
#define | BDMA_REQUEST_I2C4_TX 14U |
#define | BDMA_REQUEST_LPUART1_RX 9U |
#define | BDMA_REQUEST_LPUART1_TX 10U |
#define | BDMA_REQUEST_MEM2MEM 0U |
#define | BDMA_REQUEST_SPI6_RX 11U |
#define | BDMA_REQUEST_SPI6_TX 12U |
#define | DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) |
#define | DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) |
#define | DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) |
#define | DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) |
#define | DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) |
#define | DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) |
#define | DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) |
#define | DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) |
#define | DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) |
#define | DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) |
#define | DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) |
#define | DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) |
#define | DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) |
#define | DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) |
#define | DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) |
#define | DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) |
#define | DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) |
#define | DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) |
#define | DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) |
#define | DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) |
#define | DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) |
#define | DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) |
#define | DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) |
#define | DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) |
#define | DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) |
#define | DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) |
#define | DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) |
#define | DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) |
#define | DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) |
#define | DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
#define | DMA_IT_FE ((uint32_t)0x00000080U) |
#define | DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
#define | DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
#define | DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
#define | DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
#define | DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
#define | DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
#define | DMA_MBURST_SINGLE ((uint32_t)0x00000000U) |
#define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) |
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) |
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) |
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) |
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) |
#define | DMA_MINC_DISABLE ((uint32_t)0x00000000U) |
#define | DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) |
#define | DMA_NORMAL ((uint32_t)0x00000000U) |
#define | DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
#define | DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
#define | DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
#define | DMA_PBURST_SINGLE ((uint32_t)0x00000000U) |
#define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) |
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) |
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) |
#define | DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) |
#define | DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) |
#define | DMA_PINC_DISABLE ((uint32_t)0x00000000U) |
#define | DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) |
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) |
#define | DMA_PRIORITY_LOW ((uint32_t)0x00000000U) |
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) |
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) |
#define | DMA_REQUEST_ADC1 9U |
#define | DMA_REQUEST_ADC2 10U |
#define | DMA_REQUEST_CRYP_IN 76U |
#define | DMA_REQUEST_CRYP_OUT 77U |
#define | DMA_REQUEST_DAC1_CH1 67U |
#define | DMA_REQUEST_DAC1_CH2 68U |
#define | DMA_REQUEST_DCMI 75U |
#define | DMA_REQUEST_DFSDM1_FLT0 101U |
#define | DMA_REQUEST_DFSDM1_FLT1 102U |
#define | DMA_REQUEST_DFSDM1_FLT2 103U |
#define | DMA_REQUEST_DFSDM1_FLT3 104U |
#define | DMA_REQUEST_GENERATOR0 1U |
#define | DMA_REQUEST_GENERATOR1 2U |
#define | DMA_REQUEST_GENERATOR2 3U |
#define | DMA_REQUEST_GENERATOR3 4U |
#define | DMA_REQUEST_GENERATOR4 5U |
#define | DMA_REQUEST_GENERATOR5 6U |
#define | DMA_REQUEST_GENERATOR6 7U |
#define | DMA_REQUEST_GENERATOR7 8U |
#define | DMA_REQUEST_HASH_IN 78U |
#define | DMA_REQUEST_I2C1_RX 33U |
#define | DMA_REQUEST_I2C1_TX 34U |
#define | DMA_REQUEST_I2C2_RX 35U |
#define | DMA_REQUEST_I2C2_TX 36U |
#define | DMA_REQUEST_I2C3_RX 73U |
#define | DMA_REQUEST_I2C3_TX 74U |
#define | DMA_REQUEST_MEM2MEM 0U |
#define | DMA_REQUEST_SAI1_A 87U |
#define | DMA_REQUEST_SAI1_B 88U |
#define | DMA_REQUEST_SPDIF_RX_CS 94U |
#define | DMA_REQUEST_SPDIF_RX_DT 93U |
#define | DMA_REQUEST_SPI1_RX 37U |
#define | DMA_REQUEST_SPI1_TX 38U |
#define | DMA_REQUEST_SPI2_RX 39U |
#define | DMA_REQUEST_SPI2_TX 40U |
#define | DMA_REQUEST_SPI3_RX 61U |
#define | DMA_REQUEST_SPI3_TX 62U |
#define | DMA_REQUEST_SPI4_RX 83U |
#define | DMA_REQUEST_SPI4_TX 84U |
#define | DMA_REQUEST_SPI5_RX 85U |
#define | DMA_REQUEST_SPI5_TX 86U |
#define | DMA_REQUEST_SWPMI_RX 91U |
#define | DMA_REQUEST_SWPMI_TX 92U |
#define | DMA_REQUEST_TIM15_CH1 105U |
#define | DMA_REQUEST_TIM15_COM 108U |
#define | DMA_REQUEST_TIM15_TRIG 107U |
#define | DMA_REQUEST_TIM15_UP 106U |
#define | DMA_REQUEST_TIM16_CH1 109U |
#define | DMA_REQUEST_TIM16_UP 110U |
#define | DMA_REQUEST_TIM17_CH1 111U |
#define | DMA_REQUEST_TIM17_UP 112U |
#define | DMA_REQUEST_TIM1_CH1 11U |
#define | DMA_REQUEST_TIM1_CH2 12U |
#define | DMA_REQUEST_TIM1_CH3 13U |
#define | DMA_REQUEST_TIM1_CH4 14U |
#define | DMA_REQUEST_TIM1_COM 17U |
#define | DMA_REQUEST_TIM1_TRIG 16U |
#define | DMA_REQUEST_TIM1_UP 15U |
#define | DMA_REQUEST_TIM2_CH1 18U |
#define | DMA_REQUEST_TIM2_CH2 19U |
#define | DMA_REQUEST_TIM2_CH3 20U |
#define | DMA_REQUEST_TIM2_CH4 21U |
#define | DMA_REQUEST_TIM2_UP 22U |
#define | DMA_REQUEST_TIM3_CH1 23U |
#define | DMA_REQUEST_TIM3_CH2 24U |
#define | DMA_REQUEST_TIM3_CH3 25U |
#define | DMA_REQUEST_TIM3_CH4 26U |
#define | DMA_REQUEST_TIM3_TRIG 28U |
#define | DMA_REQUEST_TIM3_UP 27U |
#define | DMA_REQUEST_TIM4_CH1 29U |
#define | DMA_REQUEST_TIM4_CH2 30U |
#define | DMA_REQUEST_TIM4_CH3 31U |
#define | DMA_REQUEST_TIM4_UP 32U |
#define | DMA_REQUEST_TIM5_CH1 55U |
#define | DMA_REQUEST_TIM5_CH2 56U |
#define | DMA_REQUEST_TIM5_CH3 57U |
#define | DMA_REQUEST_TIM5_CH4 58U |
#define | DMA_REQUEST_TIM5_TRIG 60U |
#define | DMA_REQUEST_TIM5_UP 59U |
#define | DMA_REQUEST_TIM6_UP 69U |
#define | DMA_REQUEST_TIM7_UP 70U |
#define | DMA_REQUEST_TIM8_CH1 47U |
#define | DMA_REQUEST_TIM8_CH2 48U |
#define | DMA_REQUEST_TIM8_CH3 49U |
#define | DMA_REQUEST_TIM8_CH4 50U |
#define | DMA_REQUEST_TIM8_COM 53U |
#define | DMA_REQUEST_TIM8_TRIG 52U |
#define | DMA_REQUEST_TIM8_UP 51U |
#define | DMA_REQUEST_UART4_RX 63U |
#define | DMA_REQUEST_UART4_TX 64U |
#define | DMA_REQUEST_UART5_RX 65U |
#define | DMA_REQUEST_UART5_TX 66U |
#define | DMA_REQUEST_UART7_RX 79U |
#define | DMA_REQUEST_UART7_TX 80U |
#define | DMA_REQUEST_UART8_RX 81U |
#define | DMA_REQUEST_UART8_TX 82U |
#define | DMA_REQUEST_USART1_RX 41U |
#define | DMA_REQUEST_USART1_TX 42U |
#define | DMA_REQUEST_USART2_RX 43U |
#define | DMA_REQUEST_USART2_TX 44U |
#define | DMA_REQUEST_USART3_RX 45U |
#define | DMA_REQUEST_USART3_TX 46U |
#define | DMA_REQUEST_USART6_RX 71U |
#define | DMA_REQUEST_USART6_TX 72U |
#define | DMA_TO_BDMA_IT(__DMA_IT__) |
#define | HAL_DMA_ERROR_BUSY (0x00000800U) |
#define | HAL_DMA_ERROR_DME (0x00000004U) |
#define | HAL_DMA_ERROR_FE (0x00000002U) |
#define | HAL_DMA_ERROR_NO_XFER (0x00000080U) |
#define | HAL_DMA_ERROR_NONE (0x00000000U) |
#define | HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) |
#define | HAL_DMA_ERROR_PARAM (0x00000040U) |
#define | HAL_DMA_ERROR_REQGEN (0x00000400U) |
#define | HAL_DMA_ERROR_SYNC (0x00000200U) |
#define | HAL_DMA_ERROR_TE (0x00000001U) |
#define | HAL_DMA_ERROR_TIMEOUT (0x00000020U) |
#define | IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0)) |
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) |
#define | IS_DMA_DIRECTION(DIRECTION) |
#define | IS_DMA_FIFO_MODE_STATE(STATE) |
#define | IS_DMA_FIFO_THRESHOLD(THRESHOLD) |
#define | IS_DMA_MEMORY_BURST(BURST) |
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE) |
#define | IS_DMA_MEMORY_INC_STATE(STATE) |
#define | IS_DMA_MODE(MODE) |
#define | IS_DMA_PERIPHERAL_BURST(BURST) |
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) |
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE) |
#define | IS_DMA_PRIORITY(PRIORITY) |
#define | IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX)) |
Typedefs | |
typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef |
DMA handle Structure definition. More... | |
Header file of DMA HAL module.
This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause
Definition in file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h.