stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h
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1 /******************************************************************************
2  * @file mpu_armv7.h
3  * @brief CMSIS MPU API for Armv7-M MPU
4  * @version V5.0.4
5  * @date 10. January 2018
6  ******************************************************************************/
7 /*
8  * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef ARM_MPU_ARMV7_H
32 #define ARM_MPU_ARMV7_H
33 
34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
62 
63 #define ARM_MPU_AP_NONE 0U
64 #define ARM_MPU_AP_PRIV 1U
65 #define ARM_MPU_AP_URO 2U
66 #define ARM_MPU_AP_FULL 3U
67 #define ARM_MPU_AP_PRO 5U
68 #define ARM_MPU_AP_RO 6U
69 
70 
75 #define ARM_MPU_RBAR(Region, BaseAddress) \
76  (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77  ((Region) & MPU_RBAR_REGION_Msk) | \
78  (MPU_RBAR_VALID_Msk))
79 
88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90  (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91  (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92  (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 
103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105  (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106  (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 
130 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 
141 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 
154 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 
159 #define ARM_MPU_CACHEP_NOCACHE 0U
160 
164 #define ARM_MPU_CACHEP_WB_WRA 1U
165 
169 #define ARM_MPU_CACHEP_WT_NWA 2U
170 
174 #define ARM_MPU_CACHEP_WB_NWA 3U
175 
176 
180 typedef struct {
181  uint32_t RBAR;
182  uint32_t RASR;
184 
188 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 {
190  __DSB();
191  __ISB();
192  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 #endif
196 }
197 
201 {
202  __DSB();
203  __ISB();
204 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 #endif
207  MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 }
209 
214 {
215  MPU->RNR = rnr;
216  MPU->RASR = 0U;
217 }
218 
223 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 {
225  MPU->RBAR = rbar;
226  MPU->RASR = rasr;
227 }
228 
234 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 {
236  MPU->RNR = rnr;
237  MPU->RBAR = rbar;
238  MPU->RASR = rasr;
239 }
240 
246 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 {
248  uint32_t i;
249  for (i = 0U; i < len; ++i)
250  {
251  dst[i] = src[i];
252  }
253 }
254 
259 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 {
261  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262  while (cnt > MPU_TYPE_RALIASES) {
263  orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264  table += MPU_TYPE_RALIASES;
265  cnt -= MPU_TYPE_RALIASES;
266  }
267  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 }
269 
270 #endif
SCB
#define SCB
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:1778
ARM_MPU_SetRegionEx
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
Definition: stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h:234
ARM_MPU_ClrRegion
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Definition: stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h:213
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:944
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_gcc.h:933
__RESTRICT
#define __RESTRICT
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:105
orderedCpy
__STATIC_INLINE void orderedCpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
Definition: stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h:246
ARM_MPU_Region_t::RBAR
uint32_t RBAR
The region base address register value (RBAR)
Definition: imxrt1050/imxrt1050-evkb/CMSIS/mpu_armv7.h:184
ARM_MPU_Disable
__STATIC_INLINE void ARM_MPU_Disable(void)
Definition: stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h:200
ARM_MPU_Load
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
Definition: stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h:259
__STATIC_INLINE
#define __STATIC_INLINE
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:63
SCB_SHCSR_MEMFAULTENA_Msk
#define SCB_SHCSR_MEMFAULTENA_Msk
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:628
ARM_MPU_SetRegion
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
Definition: stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h:223
ARM_MPU_Region_t
Definition: imxrt1050/imxrt1050-evkb/CMSIS/mpu_armv7.h:183
ARM_MPU_Enable
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Definition: stm32f769/stm32f769i-disco/Drivers/CMSIS/Include/mpu_armv7.h:188


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