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21 #ifndef __STM32F4xx_HAL_DMA_H
22 #define __STM32F4xx_HAL_DMA_H
64 uint32_t PeriphDataAlignment;
67 uint32_t MemDataAlignment;
83 uint32_t FIFOThreshold;
186 #define HAL_DMA_ERROR_NONE 0x00000000U
187 #define HAL_DMA_ERROR_TE 0x00000001U
188 #define HAL_DMA_ERROR_FE 0x00000002U
189 #define HAL_DMA_ERROR_DME 0x00000004U
190 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U
191 #define HAL_DMA_ERROR_PARAM 0x00000040U
192 #define HAL_DMA_ERROR_NO_XFER 0x00000080U
193 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
202 #define DMA_CHANNEL_0 0x00000000U
203 #define DMA_CHANNEL_1 0x02000000U
204 #define DMA_CHANNEL_2 0x04000000U
205 #define DMA_CHANNEL_3 0x06000000U
206 #define DMA_CHANNEL_4 0x08000000U
207 #define DMA_CHANNEL_5 0x0A000000U
208 #define DMA_CHANNEL_6 0x0C000000U
209 #define DMA_CHANNEL_7 0x0E000000U
210 #if defined (DMA_SxCR_CHSEL_3)
211 #define DMA_CHANNEL_8 0x10000000U
212 #define DMA_CHANNEL_9 0x12000000U
213 #define DMA_CHANNEL_10 0x14000000U
214 #define DMA_CHANNEL_11 0x16000000U
215 #define DMA_CHANNEL_12 0x18000000U
216 #define DMA_CHANNEL_13 0x1A000000U
217 #define DMA_CHANNEL_14 0x1C000000U
218 #define DMA_CHANNEL_15 0x1E000000U
228 #define DMA_PERIPH_TO_MEMORY 0x00000000U
229 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
230 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
239 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
240 #define DMA_PINC_DISABLE 0x00000000U
249 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
250 #define DMA_MINC_DISABLE 0x00000000U
259 #define DMA_PDATAALIGN_BYTE 0x00000000U
260 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
261 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
270 #define DMA_MDATAALIGN_BYTE 0x00000000U
271 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
272 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
281 #define DMA_NORMAL 0x00000000U
282 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
283 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
292 #define DMA_PRIORITY_LOW 0x00000000U
293 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
294 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
295 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
304 #define DMA_FIFOMODE_DISABLE 0x00000000U
305 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
314 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U
315 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
316 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
317 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
326 #define DMA_MBURST_SINGLE 0x00000000U
327 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
328 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
329 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
338 #define DMA_PBURST_SINGLE 0x00000000U
339 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
340 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
341 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
350 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
351 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
352 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
353 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
354 #define DMA_IT_FE 0x00000080U
363 #define DMA_FLAG_FEIF0_4 0x00000001U
364 #define DMA_FLAG_DMEIF0_4 0x00000004U
365 #define DMA_FLAG_TEIF0_4 0x00000008U
366 #define DMA_FLAG_HTIF0_4 0x00000010U
367 #define DMA_FLAG_TCIF0_4 0x00000020U
368 #define DMA_FLAG_FEIF1_5 0x00000040U
369 #define DMA_FLAG_DMEIF1_5 0x00000100U
370 #define DMA_FLAG_TEIF1_5 0x00000200U
371 #define DMA_FLAG_HTIF1_5 0x00000400U
372 #define DMA_FLAG_TCIF1_5 0x00000800U
373 #define DMA_FLAG_FEIF2_6 0x00010000U
374 #define DMA_FLAG_DMEIF2_6 0x00040000U
375 #define DMA_FLAG_TEIF2_6 0x00080000U
376 #define DMA_FLAG_HTIF2_6 0x00100000U
377 #define DMA_FLAG_TCIF2_6 0x00200000U
378 #define DMA_FLAG_FEIF3_7 0x00400000U
379 #define DMA_FLAG_DMEIF3_7 0x01000000U
380 #define DMA_FLAG_TEIF3_7 0x02000000U
381 #define DMA_FLAG_HTIF3_7 0x04000000U
382 #define DMA_FLAG_TCIF3_7 0x08000000U
397 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
411 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
418 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
425 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
434 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
435 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
454 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
455 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
474 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
475 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
494 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
495 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
514 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
515 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
542 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
543 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
544 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
545 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
560 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
561 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
562 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
563 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
577 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
578 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
592 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
593 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
607 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
608 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
609 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
628 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
636 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
703 #if defined (DMA_SxCR_CHSEL_3)
704 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
705 ((CHANNEL) == DMA_CHANNEL_1) || \
706 ((CHANNEL) == DMA_CHANNEL_2) || \
707 ((CHANNEL) == DMA_CHANNEL_3) || \
708 ((CHANNEL) == DMA_CHANNEL_4) || \
709 ((CHANNEL) == DMA_CHANNEL_5) || \
710 ((CHANNEL) == DMA_CHANNEL_6) || \
711 ((CHANNEL) == DMA_CHANNEL_7) || \
712 ((CHANNEL) == DMA_CHANNEL_8) || \
713 ((CHANNEL) == DMA_CHANNEL_9) || \
714 ((CHANNEL) == DMA_CHANNEL_10)|| \
715 ((CHANNEL) == DMA_CHANNEL_11)|| \
716 ((CHANNEL) == DMA_CHANNEL_12)|| \
717 ((CHANNEL) == DMA_CHANNEL_13)|| \
718 ((CHANNEL) == DMA_CHANNEL_14)|| \
719 ((CHANNEL) == DMA_CHANNEL_15))
721 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
722 ((CHANNEL) == DMA_CHANNEL_1) || \
723 ((CHANNEL) == DMA_CHANNEL_2) || \
724 ((CHANNEL) == DMA_CHANNEL_3) || \
725 ((CHANNEL) == DMA_CHANNEL_4) || \
726 ((CHANNEL) == DMA_CHANNEL_5) || \
727 ((CHANNEL) == DMA_CHANNEL_6) || \
728 ((CHANNEL) == DMA_CHANNEL_7))
731 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
732 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
733 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
735 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
737 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
738 ((STATE) == DMA_PINC_DISABLE))
740 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
741 ((STATE) == DMA_MINC_DISABLE))
743 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
744 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
745 ((SIZE) == DMA_PDATAALIGN_WORD))
747 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
748 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
749 ((SIZE) == DMA_MDATAALIGN_WORD ))
751 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
752 ((MODE) == DMA_CIRCULAR) || \
753 ((MODE) == DMA_PFCTRL))
755 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
756 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
757 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
758 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
760 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
761 ((STATE) == DMA_FIFOMODE_ENABLE))
763 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
764 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
765 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
766 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
768 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
769 ((BURST) == DMA_MBURST_INC4) || \
770 ((BURST) == DMA_MBURST_INC8) || \
771 ((BURST) == DMA_MBURST_INC16))
773 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
774 ((BURST) == DMA_PBURST_INC4) || \
775 ((BURST) == DMA_PBURST_INC8) || \
776 ((BURST) == DMA_PBURST_INC16))
HAL_StatusTypeDef
HAL Status structures definition
@ HAL_DMA_XFER_ERROR_CB_ID
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
DMA handle Structure definition.
uint32_t StreamBaseAddress
DMA Configuration Structure definition.
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
HAL_LockTypeDef
HAL Lock structures definition
__IO HAL_DMA_StateTypeDef State
@ HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
DMA_Stream_TypeDef * Instance
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_DMA_CallbackIDTypeDef
HAL DMA Error Code structure definition.
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ HAL_DMA_XFER_M1CPLT_CB_ID
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
Header file of DMA HAL extension module.
@ HAL_DMA_XFER_CPLT_CB_ID
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma)
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
@ HAL_DMA_XFER_HALFCPLT_CB_ID
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition.
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))