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26 #define PV_OCOTP_FREQ_HZ (CLOCK_GetFreq(kCLOCK_IpgClk))
32 return (
const uint8_t *)
uuid;
47 uint32_t uuid_int32[2] = {0};
void BOARD_InitDebugConsole(void)
@ PV_STATUS_INVALID_STATE
static pv_status_t pv_uart_init(void)
void OCOTP_ReloadShadowRegister(OCOTP_Type *base)
Reload the shadow register. This function will help reload the shadow register without reseting the O...
uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address)
Read the fuse shadow register with the fuse addess.
const uint8_t * pv_get_uuid(void)
void BOARD_InitBootPeripherals(void)
static void OCOTP_ClearErrorStatus(OCOTP_Type *base)
Clear the error bit if this bit is set.
static uint8_t uuid[UUID_SIZE]
void BOARD_InitBootClocks(void)
This function executes default configuration of clocks.
pv_status_t pv_board_init()
const uint32_t pv_get_uuid_size(void)
void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz)
Initializes OCOTP controller.
void BOARD_ConfigMPU(void)
CMSIS Peripheral Access Layer for MIMXRT1052.
void BOARD_InitBootPins(void)
Calls initialization functions.
void BOARD_BootClockRUN(void)
This function executes configuration of clocks.
volatile bool is_new_message
void pv_error_handler(void)
pv_status_t pv_message_init(void)