stm32f30x_tim.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F30x_TIM_H
31 #define __STM32F30x_TIM_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f30x.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
55 typedef struct
56 {
57  uint16_t TIM_Prescaler;
60  uint16_t TIM_CounterMode;
63  uint32_t TIM_Period;
67  uint16_t TIM_ClockDivision;
70  uint16_t TIM_RepetitionCounter;
78 } TIM_TimeBaseInitTypeDef;
79 
84 typedef struct
85 {
86  uint32_t TIM_OCMode;
89  uint16_t TIM_OutputState;
92  uint16_t TIM_OutputNState;
96  uint32_t TIM_Pulse;
99  uint16_t TIM_OCPolarity;
102  uint16_t TIM_OCNPolarity;
106  uint16_t TIM_OCIdleState;
110  uint16_t TIM_OCNIdleState;
113 } TIM_OCInitTypeDef;
114 
119 typedef struct
120 {
121 
122  uint16_t TIM_Channel;
125  uint16_t TIM_ICPolarity;
128  uint16_t TIM_ICSelection;
131  uint16_t TIM_ICPrescaler;
134  uint16_t TIM_ICFilter;
136 } TIM_ICInitTypeDef;
137 
143 typedef struct
144 {
145 
146  uint16_t TIM_OSSRState;
149  uint16_t TIM_OSSIState;
152  uint16_t TIM_LOCKLevel;
155  uint16_t TIM_DeadTime;
159  uint16_t TIM_Break;
162  uint16_t TIM_BreakPolarity;
165  uint16_t TIM_AutomaticOutput;
167 } TIM_BDTRInitTypeDef;
168 
169 /* Exported constants --------------------------------------------------------*/
170 
175 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
176  ((PERIPH) == TIM2) || \
177  ((PERIPH) == TIM3) || \
178  ((PERIPH) == TIM4) || \
179  ((PERIPH) == TIM6) || \
180  ((PERIPH) == TIM7) || \
181  ((PERIPH) == TIM8) || \
182  ((PERIPH) == TIM15) || \
183  ((PERIPH) == TIM16) || \
184  ((PERIPH) == TIM17))
185 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */
186 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
187  ((PERIPH) == TIM2) || \
188  ((PERIPH) == TIM3) || \
189  ((PERIPH) == TIM4) || \
190  ((PERIPH) == TIM8) || \
191  ((PERIPH) == TIM15) || \
192  ((PERIPH) == TIM16) || \
193  ((PERIPH) == TIM17))
194 
195 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */
196 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
197  ((PERIPH) == TIM2) || \
198  ((PERIPH) == TIM3) || \
199  ((PERIPH) == TIM4) || \
200  ((PERIPH) == TIM8) || \
201  ((PERIPH) == TIM15))
202 /* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */
203 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
204  ((PERIPH) == TIM2) || \
205  ((PERIPH) == TIM3) || \
206  ((PERIPH) == TIM4) || \
207  ((PERIPH) == TIM8))
208 /* LIST4: TIM1 and TIM8 */
209 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\
210  ((PERIPH) == TIM8))
211 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
212 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
213  ((PERIPH) == TIM2) || \
214  ((PERIPH) == TIM3) || \
215  ((PERIPH) == TIM4) || \
216  ((PERIPH) == TIM6) || \
217  ((PERIPH) == TIM7) || \
218  ((PERIPH) == TIM8))
219 /* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */
220 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
221  ((PERIPH) == TIM8) || \
222  ((PERIPH) == TIM15) || \
223  ((PERIPH) == TIM16) || \
224  ((PERIPH) == TIM17))
225 
226 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
227 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
228  ((PERIPH) == TIM2) || \
229  ((PERIPH) == TIM3) || \
230  ((PERIPH) == TIM4) || \
231  ((PERIPH) == TIM6) || \
232  ((PERIPH) == TIM7) || \
233  ((PERIPH) == TIM8) || \
234  ((PERIPH) == TIM15))
235 /* LIST8: TIM16 (option register) */
236 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \
237  ((PERIPH) == TIM1)||\
238  ((PERIPH) == TIM8))
239 
244 #define TIM_OCMode_Timing ((uint32_t)0x00000)
245 #define TIM_OCMode_Active ((uint32_t)0x00010)
246 #define TIM_OCMode_Inactive ((uint32_t)0x00020)
247 #define TIM_OCMode_Toggle ((uint32_t)0x00030)
248 #define TIM_OCMode_PWM1 ((uint32_t)0x00060)
249 #define TIM_OCMode_PWM2 ((uint32_t)0x00070)
250 
251 #define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000)
252 #define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010)
253 #define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040)
254 #define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050)
255 #define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060)
256 #define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070)
257 
258 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
259  ((MODE) == TIM_OCMode_Active) || \
260  ((MODE) == TIM_OCMode_Inactive) || \
261  ((MODE) == TIM_OCMode_Toggle)|| \
262  ((MODE) == TIM_OCMode_PWM1) || \
263  ((MODE) == TIM_OCMode_PWM2) || \
264  ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
265  ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
266  ((MODE) == TIM_OCMode_Combined_PWM1) || \
267  ((MODE) == TIM_OCMode_Combined_PWM2) || \
268  ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
269  ((MODE) == TIM_OCMode_Asymmetric_PWM2))
270 
271 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
272  ((MODE) == TIM_OCMode_Active) || \
273  ((MODE) == TIM_OCMode_Inactive) || \
274  ((MODE) == TIM_OCMode_Toggle)|| \
275  ((MODE) == TIM_OCMode_PWM1) || \
276  ((MODE) == TIM_OCMode_PWM2) || \
277  ((MODE) == TIM_ForcedAction_Active) || \
278  ((MODE) == TIM_ForcedAction_InActive) || \
279  ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
280  ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
281  ((MODE) == TIM_OCMode_Combined_PWM1) || \
282  ((MODE) == TIM_OCMode_Combined_PWM2) || \
283  ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
284  ((MODE) == TIM_OCMode_Asymmetric_PWM2))
285 
293 #define TIM_OPMode_Single ((uint16_t)0x0008)
294 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
295 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
296  ((MODE) == TIM_OPMode_Repetitive))
297 
305 #define TIM_Channel_1 ((uint16_t)0x0000)
306 #define TIM_Channel_2 ((uint16_t)0x0004)
307 #define TIM_Channel_3 ((uint16_t)0x0008)
308 #define TIM_Channel_4 ((uint16_t)0x000C)
309 #define TIM_Channel_5 ((uint16_t)0x0010)
310 #define TIM_Channel_6 ((uint16_t)0x0014)
311 
312 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
313  ((CHANNEL) == TIM_Channel_2) || \
314  ((CHANNEL) == TIM_Channel_3) || \
315  ((CHANNEL) == TIM_Channel_4))
316 
317 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
318  ((CHANNEL) == TIM_Channel_2))
319 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
320  ((CHANNEL) == TIM_Channel_2) || \
321  ((CHANNEL) == TIM_Channel_3))
322 
330 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
331 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
332 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
333 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
334  ((DIV) == TIM_CKD_DIV2) || \
335  ((DIV) == TIM_CKD_DIV4))
336 
344 #define TIM_CounterMode_Up ((uint16_t)0x0000)
345 #define TIM_CounterMode_Down ((uint16_t)0x0010)
346 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
347 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
348 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
349 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
350  ((MODE) == TIM_CounterMode_Down) || \
351  ((MODE) == TIM_CounterMode_CenterAligned1) || \
352  ((MODE) == TIM_CounterMode_CenterAligned2) || \
353  ((MODE) == TIM_CounterMode_CenterAligned3))
354 
362 #define TIM_OCPolarity_High ((uint16_t)0x0000)
363 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
364 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
365  ((POLARITY) == TIM_OCPolarity_Low))
366 
374 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
375 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
376 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
377  ((POLARITY) == TIM_OCNPolarity_Low))
378 
386 #define TIM_OutputState_Disable ((uint16_t)0x0000)
387 #define TIM_OutputState_Enable ((uint16_t)0x0001)
388 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
389  ((STATE) == TIM_OutputState_Enable))
390 
398 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
399 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
400 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
401  ((STATE) == TIM_OutputNState_Enable))
402 
410 #define TIM_CCx_Enable ((uint16_t)0x0001)
411 #define TIM_CCx_Disable ((uint16_t)0x0000)
412 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
413  ((CCX) == TIM_CCx_Disable))
414 
422 #define TIM_CCxN_Enable ((uint16_t)0x0004)
423 #define TIM_CCxN_Disable ((uint16_t)0x0000)
424 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
425  ((CCXN) == TIM_CCxN_Disable))
426 
434 #define TIM_Break_Enable ((uint16_t)0x1000)
435 #define TIM_Break_Disable ((uint16_t)0x0000)
436 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
437  ((STATE) == TIM_Break_Disable))
438 
446 #define TIM_Break1_Enable ((uint32_t)0x00001000)
447 #define TIM_Break1_Disable ((uint32_t)0x00000000)
448 #define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \
449  ((STATE) == TIM_Break1_Disable))
450 
458 #define TIM_Break2_Enable ((uint32_t)0x01000000)
459 #define TIM_Break2_Disable ((uint32_t)0x00000000)
460 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \
461  ((STATE) == TIM_Break2_Disable))
462 
470 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
471 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
472 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
473  ((POLARITY) == TIM_BreakPolarity_High))
474 
482 #define TIM_Break1Polarity_Low ((uint32_t)0x00000000)
483 #define TIM_Break1Polarity_High ((uint32_t)0x00002000)
484 #define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \
485  ((POLARITY) == TIM_Break1Polarity_High))
486 
494 #define TIM_Break2Polarity_Low ((uint32_t)0x00000000)
495 #define TIM_Break2Polarity_High ((uint32_t)0x02000000)
496 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \
497  ((POLARITY) == TIM_Break2Polarity_High))
498 
506 #define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF)
507 
515 #define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF)
516 
524 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
525 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
526 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
527  ((STATE) == TIM_AutomaticOutput_Disable))
528 
536 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
537 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
538 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
539 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
540 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
541  ((LEVEL) == TIM_LOCKLevel_1) || \
542  ((LEVEL) == TIM_LOCKLevel_2) || \
543  ((LEVEL) == TIM_LOCKLevel_3))
544 
552 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
553 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
554 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
555  ((STATE) == TIM_OSSIState_Disable))
556 
564 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
565 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
566 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
567  ((STATE) == TIM_OSSRState_Disable))
568 
576 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
577 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
578 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
579  ((STATE) == TIM_OCIdleState_Reset))
580 
588 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
589 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
590 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
591  ((STATE) == TIM_OCNIdleState_Reset))
592 
600 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
601 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
602 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
603 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
604  ((POLARITY) == TIM_ICPolarity_Falling)|| \
605  ((POLARITY) == TIM_ICPolarity_BothEdge))
606 
614 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001)
616 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
618 #define TIM_ICSelection_TRC ((uint16_t)0x0003)
619 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
620  ((SELECTION) == TIM_ICSelection_IndirectTI) || \
621  ((SELECTION) == TIM_ICSelection_TRC))
622 
630 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000)
631 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004)
632 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008)
633 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C)
634 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
635  ((PRESCALER) == TIM_ICPSC_DIV2) || \
636  ((PRESCALER) == TIM_ICPSC_DIV4) || \
637  ((PRESCALER) == TIM_ICPSC_DIV8))
638 
646 #define TIM_IT_Update ((uint16_t)0x0001)
647 #define TIM_IT_CC1 ((uint16_t)0x0002)
648 #define TIM_IT_CC2 ((uint16_t)0x0004)
649 #define TIM_IT_CC3 ((uint16_t)0x0008)
650 #define TIM_IT_CC4 ((uint16_t)0x0010)
651 #define TIM_IT_COM ((uint16_t)0x0020)
652 #define TIM_IT_Trigger ((uint16_t)0x0040)
653 #define TIM_IT_Break ((uint16_t)0x0080)
654 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
655 
656 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
657  ((IT) == TIM_IT_CC1) || \
658  ((IT) == TIM_IT_CC2) || \
659  ((IT) == TIM_IT_CC3) || \
660  ((IT) == TIM_IT_CC4) || \
661  ((IT) == TIM_IT_COM) || \
662  ((IT) == TIM_IT_Trigger) || \
663  ((IT) == TIM_IT_Break))
664 
672 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
673 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
674 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
675 #define TIM_DMABase_DIER ((uint16_t)0x0003)
676 #define TIM_DMABase_SR ((uint16_t)0x0004)
677 #define TIM_DMABase_EGR ((uint16_t)0x0005)
678 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
679 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
680 #define TIM_DMABase_CCER ((uint16_t)0x0008)
681 #define TIM_DMABase_CNT ((uint16_t)0x0009)
682 #define TIM_DMABase_PSC ((uint16_t)0x000A)
683 #define TIM_DMABase_ARR ((uint16_t)0x000B)
684 #define TIM_DMABase_RCR ((uint16_t)0x000C)
685 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
686 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
687 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
688 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
689 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
690 #define TIM_DMABase_DCR ((uint16_t)0x0012)
691 #define TIM_DMABase_OR ((uint16_t)0x0013)
692 #define TIM_DMABase_CCMR3 ((uint16_t)0x0014)
693 #define TIM_DMABase_CCR5 ((uint16_t)0x0015)
694 #define TIM_DMABase_CCR6 ((uint16_t)0x0016)
695 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
696  ((BASE) == TIM_DMABase_CR2) || \
697  ((BASE) == TIM_DMABase_SMCR) || \
698  ((BASE) == TIM_DMABase_DIER) || \
699  ((BASE) == TIM_DMABase_SR) || \
700  ((BASE) == TIM_DMABase_EGR) || \
701  ((BASE) == TIM_DMABase_CCMR1) || \
702  ((BASE) == TIM_DMABase_CCMR2) || \
703  ((BASE) == TIM_DMABase_CCER) || \
704  ((BASE) == TIM_DMABase_CNT) || \
705  ((BASE) == TIM_DMABase_PSC) || \
706  ((BASE) == TIM_DMABase_ARR) || \
707  ((BASE) == TIM_DMABase_RCR) || \
708  ((BASE) == TIM_DMABase_CCR1) || \
709  ((BASE) == TIM_DMABase_CCR2) || \
710  ((BASE) == TIM_DMABase_CCR3) || \
711  ((BASE) == TIM_DMABase_CCR4) || \
712  ((BASE) == TIM_DMABase_BDTR) || \
713  ((BASE) == TIM_DMABase_DCR) || \
714  ((BASE) == TIM_DMABase_OR) || \
715  ((BASE) == TIM_DMABase_CCMR3) || \
716  ((BASE) == TIM_DMABase_CCR5) || \
717  ((BASE) == TIM_DMABase_CCR6))
718 
726 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
727 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
728 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
729 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
730 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
731 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
732 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
733 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
734 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
735 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
736 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
737 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
738 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
739 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
740 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
741 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
742 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
743 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
744 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
745  ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
746  ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
747  ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
748  ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
749  ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
750  ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
751  ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
752  ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
753  ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
754  ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
755  ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
756  ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
757  ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
758  ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
759  ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
760  ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
761  ((LENGTH) == TIM_DMABurstLength_18Transfers))
762 
770 #define TIM_DMA_Update ((uint16_t)0x0100)
771 #define TIM_DMA_CC1 ((uint16_t)0x0200)
772 #define TIM_DMA_CC2 ((uint16_t)0x0400)
773 #define TIM_DMA_CC3 ((uint16_t)0x0800)
774 #define TIM_DMA_CC4 ((uint16_t)0x1000)
775 #define TIM_DMA_COM ((uint16_t)0x2000)
776 #define TIM_DMA_Trigger ((uint16_t)0x4000)
777 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
778 
787 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
788 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
789 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
790 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
791 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
792  ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
793  ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
794  ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
795 
803 #define TIM_TS_ITR0 ((uint16_t)0x0000)
804 #define TIM_TS_ITR1 ((uint16_t)0x0010)
805 #define TIM_TS_ITR2 ((uint16_t)0x0020)
806 #define TIM_TS_ITR3 ((uint16_t)0x0030)
807 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
808 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
809 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
810 #define TIM_TS_ETRF ((uint16_t)0x0070)
811 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
812  ((SELECTION) == TIM_TS_ITR1) || \
813  ((SELECTION) == TIM_TS_ITR2) || \
814  ((SELECTION) == TIM_TS_ITR3) || \
815  ((SELECTION) == TIM_TS_TI1F_ED) || \
816  ((SELECTION) == TIM_TS_TI1FP1) || \
817  ((SELECTION) == TIM_TS_TI2FP2) || \
818  ((SELECTION) == TIM_TS_ETRF))
819 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
820  ((SELECTION) == TIM_TS_ITR1) || \
821  ((SELECTION) == TIM_TS_ITR2) || \
822  ((SELECTION) == TIM_TS_ITR3))
823 
831 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
832 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
833 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
834 
842 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
843 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
844 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
845  ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
846 
854 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
855 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
856 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
857  ((RELOAD) == TIM_PSCReloadMode_Immediate))
858 
866 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
867 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
868 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
869  ((ACTION) == TIM_ForcedAction_InActive))
870 
878 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
879 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
880 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
881 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
882  ((MODE) == TIM_EncoderMode_TI2) || \
883  ((MODE) == TIM_EncoderMode_TI12))
884 
893 #define TIM_EventSource_Update ((uint16_t)0x0001)
894 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
895 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
896 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
897 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
898 #define TIM_EventSource_COM ((uint16_t)0x0020)
899 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
900 #define TIM_EventSource_Break ((uint16_t)0x0080)
901 #define TIM_EventSource_Break2 ((uint16_t)0x0100)
902 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000))
903 
912 #define TIM_UpdateSource_Global ((uint16_t)0x0000)
915 #define TIM_UpdateSource_Regular ((uint16_t)0x0001)
916 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
917  ((SOURCE) == TIM_UpdateSource_Regular))
918 
926 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
927 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
928 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
929  ((STATE) == TIM_OCPreload_Disable))
930 
938 #define TIM_OCFast_Enable ((uint16_t)0x0004)
939 #define TIM_OCFast_Disable ((uint16_t)0x0000)
940 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
941  ((STATE) == TIM_OCFast_Disable))
942 
951 #define TIM_OCClear_Enable ((uint16_t)0x0080)
952 #define TIM_OCClear_Disable ((uint16_t)0x0000)
953 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
954  ((STATE) == TIM_OCClear_Disable))
955 
963 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
964 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
965 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
966 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
967 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
968 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
969 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
970 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
971 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
972  ((SOURCE) == TIM_TRGOSource_Enable) || \
973  ((SOURCE) == TIM_TRGOSource_Update) || \
974  ((SOURCE) == TIM_TRGOSource_OC1) || \
975  ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
976  ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
977  ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
978  ((SOURCE) == TIM_TRGOSource_OC4Ref))
979 
980 
981 #define TIM_TRGO2Source_Reset ((uint32_t)0x00000000)
982 #define TIM_TRGO2Source_Enable ((uint32_t)0x00100000)
983 #define TIM_TRGO2Source_Update ((uint32_t)0x00200000)
984 #define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000)
985 #define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000)
986 #define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000)
987 #define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000)
988 #define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000)
989 #define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000)
990 #define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000)
991 #define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000)
992 #define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000)
993 #define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000)
994 #define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000)
995 #define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000)
996 #define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000)
997 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \
998  ((SOURCE) == TIM_TRGO2Source_Enable) || \
999  ((SOURCE) == TIM_TRGO2Source_Update) || \
1000  ((SOURCE) == TIM_TRGO2Source_OC1) || \
1001  ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \
1002  ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \
1003  ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \
1004  ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \
1005  ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \
1006  ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \
1007  ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \
1008  ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \
1009  ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \
1010  ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \
1011  ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \
1012  ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling))
1013 
1021 #define TIM_SlaveMode_Reset ((uint32_t)0x00004)
1022 #define TIM_SlaveMode_Gated ((uint32_t)0x00005)
1023 #define TIM_SlaveMode_Trigger ((uint32_t)0x00006)
1024 #define TIM_SlaveMode_External1 ((uint32_t)0x00007)
1025 #define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000)
1026 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
1027  ((MODE) == TIM_SlaveMode_Gated) || \
1028  ((MODE) == TIM_SlaveMode_Trigger) || \
1029  ((MODE) == TIM_SlaveMode_External1) || \
1030  ((MODE) == TIM_SlaveMode_Combined_ResetTrigger))
1031 
1039 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
1040 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
1041 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
1042  ((STATE) == TIM_MasterSlaveMode_Disable))
1043 
1049 #define TIM16_GPIO ((uint16_t)0x0000)
1050 #define TIM16_RTC_CLK ((uint16_t)0x0001)
1051 #define TIM16_HSEDiv32 ((uint16_t)0x0002)
1052 #define TIM16_MCO ((uint16_t)0x0003)
1053 
1054 #define TIM1_ADC1_AWDG1 ((uint16_t)0x0001)
1055 #define TIM1_ADC1_AWDG2 ((uint16_t)0x0002)
1056 #define TIM1_ADC1_AWDG3 ((uint16_t)0x0003)
1057 #define TIM1_ADC4_AWDG1 ((uint16_t)0x0004)
1058 #define TIM1_ADC4_AWDG2 ((uint16_t)0x0008)
1059 #define TIM1_ADC4_AWDG3 ((uint16_t)0x000C)
1060 
1061 #define TIM8_ADC2_AWDG1 ((uint16_t)0x0001)
1062 #define TIM8_ADC2_AWDG2 ((uint16_t)0x0002)
1063 #define TIM8_ADC2_AWDG3 ((uint16_t)0x0003)
1064 #define TIM8_ADC3_AWDG1 ((uint16_t)0x0004)
1065 #define TIM8_ADC3_AWDG2 ((uint16_t)0x0008)
1066 #define TIM8_ADC3_AWDG3 ((uint16_t)0x000C)
1067 
1068 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \
1069  ((TIM_REMAP) == TIM16_RTC_CLK) || \
1070  ((TIM_REMAP) == TIM16_HSEDiv32) || \
1071  ((TIM_REMAP) == TIM16_MCO) ||\
1072  ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\
1073  ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\
1074  ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\
1075  ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\
1076  ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\
1077  ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\
1078  ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\
1079  ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\
1080  ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\
1081  ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\
1082  ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\
1083  ((TIM_REMAP) == TIM8_ADC3_AWDG3))
1084 
1092 #define TIM_FLAG_Update ((uint32_t)0x00001)
1093 #define TIM_FLAG_CC1 ((uint32_t)0x00002)
1094 #define TIM_FLAG_CC2 ((uint32_t)0x00004)
1095 #define TIM_FLAG_CC3 ((uint32_t)0x00008)
1096 #define TIM_FLAG_CC4 ((uint32_t)0x00010)
1097 #define TIM_FLAG_COM ((uint32_t)0x00020)
1098 #define TIM_FLAG_Trigger ((uint32_t)0x00040)
1099 #define TIM_FLAG_Break ((uint32_t)0x00080)
1100 #define TIM_FLAG_Break2 ((uint32_t)0x00100)
1101 #define TIM_FLAG_CC1OF ((uint32_t)0x00200)
1102 #define TIM_FLAG_CC2OF ((uint32_t)0x00400)
1103 #define TIM_FLAG_CC3OF ((uint32_t)0x00800)
1104 #define TIM_FLAG_CC4OF ((uint32_t)0x01000)
1105 #define TIM_FLAG_CC5 ((uint32_t)0x10000)
1106 #define TIM_FLAG_CC6 ((uint32_t)0x20000)
1107 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
1108  ((FLAG) == TIM_FLAG_CC1) || \
1109  ((FLAG) == TIM_FLAG_CC2) || \
1110  ((FLAG) == TIM_FLAG_CC3) || \
1111  ((FLAG) == TIM_FLAG_CC4) || \
1112  ((FLAG) == TIM_FLAG_COM) || \
1113  ((FLAG) == TIM_FLAG_Trigger) || \
1114  ((FLAG) == TIM_FLAG_Break) || \
1115  ((FLAG) == TIM_FLAG_Break2) || \
1116  ((FLAG) == TIM_FLAG_CC1OF) || \
1117  ((FLAG) == TIM_FLAG_CC2OF) || \
1118  ((FLAG) == TIM_FLAG_CC3OF) || \
1119  ((FLAG) == TIM_FLAG_CC4OF) ||\
1120  ((FLAG) == TIM_FLAG_CC5) ||\
1121  ((FLAG) == TIM_FLAG_CC6))
1122 
1123 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000))
1124 
1131 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
1132 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
1133 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
1134  ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
1135 
1140 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
1141 
1149 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
1150 
1158 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
1159 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
1160 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
1161 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
1162 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
1163 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
1164 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
1165 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
1166 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
1167 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
1168 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
1169 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
1170 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
1171 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
1172 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
1173 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
1174 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
1175 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
1176 
1184 /* Exported macro ------------------------------------------------------------*/
1185 /* Exported functions --------------------------------------------------------*/
1186 
1187 /* TimeBase management ********************************************************/
1188 void TIM_DeInit(TIM_TypeDef* TIMx);
1189 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1190 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1191 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
1192 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
1193 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
1194 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
1195 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
1196 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
1197 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1198 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
1199 void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState);
1200 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1201 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
1202 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
1203 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1204 
1205 /* Output Compare management **************************************************/
1206 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1207 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1208 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1209 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1210 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1211 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1212 void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState);
1213 void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState);
1214 void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState);
1215 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
1216 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode);
1217 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
1218 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
1219 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
1220 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
1221 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5);
1222 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6);
1223 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1224 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1225 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1226 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1227 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1228 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1229 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1230 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1231 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1232 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1233 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1234 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1235 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1236 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1237 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1238 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1239 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1240 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1241 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1242 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1243 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1244 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1245 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
1246 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1247 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1248 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1249 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1250 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1251 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1252 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1253 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1254 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1255 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
1256 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
1257 
1258 /* Input Capture management ***************************************************/
1259 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1260 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
1261 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1262 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
1263 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
1264 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
1265 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
1266 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1267 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1268 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1269 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1270 
1271 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/
1272 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
1273 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter);
1274 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter);
1275 void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1276 void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1277 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
1278 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
1279 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
1280 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
1281 
1282 /* Interrupts, DMA and flags management ***************************************/
1283 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
1284 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
1285 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG);
1286 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1287 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1288 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1289 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
1290 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
1291 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
1292 
1293 /* Clocks management **********************************************************/
1294 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
1295 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1296 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1297  uint16_t TIM_ICPolarity, uint16_t ICFilter);
1298 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1299  uint16_t ExtTRGFilter);
1300 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1301  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
1302 
1303 /* Synchronization management *************************************************/
1304 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1305 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
1306 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source);
1307 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
1308 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
1309 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1310  uint16_t ExtTRGFilter);
1311 
1312 /* Specific interface management **********************************************/
1313 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1314  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
1315 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
1316 
1317 /* Specific remapping management **********************************************/
1318 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
1319 
1320 #ifdef __cplusplus
1321 }
1322 #endif
1323 
1324 #endif /*__STM32F30x_TIM_H */
1325 
1334 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
TIM_ETRClockMode1Config
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
Definition: stm32f4xx_tim.c:2774
TIM_CCPreloadControl
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
Definition: stm32f4xx_tim.c:2315
FlagStatus
FlagStatus
Definition: stm32f4xx.h:706
TIM_ForcedOC6Config
void TIM_ForcedOC6Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 6 waveform to active or inactive level.
Definition: stm32f30x_tim.c:1511
TIM_SetIC4Prescaler
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
Definition: stm32f4xx_tim.c:2168
TIM_ClearOC1Ref
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
Definition: stm32f4xx_tim.c:1476
TIM_UpdateRequestConfig
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
Definition: stm32f4xx_tim.c:497
TIM_CCxNCmd
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
Definition: stm32f4xx_tim.c:1816
FunctionalState
FunctionalState
Definition: stm32f4xx.h:708
TIM_OC5PreloadConfig
void TIM_OC5PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR5.
Definition: stm32f30x_tim.c:1656
TIM_GetCapture4
uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
Definition: stm32f4xx_tim.c:2075
TIM_DeInit
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
Definition: stm32f4xx_tim.c:200
TIM_TimeBaseStructInit
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
Definition: stm32f4xx_tim.c:340
TIM_SetIC3Prescaler
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
Definition: stm32f4xx_tim.c:2144
TIM_Break2Config
void TIM_Break2Config(TIM_TypeDef *TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
Configures the Break2 feature.
Definition: stm32f30x_tim.c:2761
TIM_SetCompare3
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
Definition: stm32f4xx_tim.c:1091
TIM_OC1PreloadConfig
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
Definition: stm32f4xx_tim.c:1238
TIM_ForcedOC1Config
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1124
TIM_ClearOC3Ref
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
Definition: stm32f4xx_tim.c:1535
TIM_SelectOutputTrigger
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
Definition: stm32f4xx_tim.c:2935
TIM_OC2PreloadConfig
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
Definition: stm32f4xx_tim.c:1268
TIM_OC5Init
void TIM_OC5Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel5 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f30x_tim.c:982
TIM_OC1FastConfig
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
Definition: stm32f4xx_tim.c:1355
TIM_BDTRStructInit
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
Definition: stm32f4xx_tim.c:2246
TIM_SelectCCDMA
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
Definition: stm32f4xx_tim.c:2644
TIM_ClearITPendingBit
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx&#39;s interrupt pending bits.
Definition: stm32f4xx_tim.c:2554
TIM_SetCompare4
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
Definition: stm32f4xx_tim.c:1106
TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter
uint16_t TIM_RepetitionCounter
Definition: stm32f30x_tim.h:70
TIM_SelectCOM
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
Definition: stm32f4xx_tim.c:2290
TIM_SelectOCREFClear
void TIM_SelectOCREFClear(TIM_TypeDef *TIMx, uint16_t TIM_OCReferenceClear)
Selects the OCReference Clear source.
Definition: stm32f30x_tim.c:2010
TIM_SelectGC5C2
void TIM_SelectGC5C2(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM Group Channel 5 and Channel 2, OC2REFC is the logical AND of OC2REFC and OC5REF...
Definition: stm32f30x_tim.c:1136
TIM_SetCompare5
void TIM_SetCompare5(TIM_TypeDef *TIMx, uint32_t Compare5)
Sets the TIMx Capture Compare5 Register value.
Definition: stm32f30x_tim.c:1336
TIM_OC1PolarityConfig
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
Definition: stm32f4xx_tim.c:1593
TIM_RemapConfig
void TIM_RemapConfig(TIM_TypeDef *TIMx, uint16_t TIM_Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
Definition: stm32f4xx_tim.c:3173
TIM_TIxExternalClockConfig
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
Definition: stm32f4xx_tim.c:2734
TIM_SelectGC5C3
void TIM_SelectGC5C3(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM Group Channel 5 and Channel 3, OC3REFC is the logical AND of OC3REFC and OC5REF...
Definition: stm32f30x_tim.c:1163
TIM_SelectHallSensor
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx&#39;s Hall sensor interface.
Definition: stm32f4xx_tim.c:3122
TIM_EncoderInterfaceConfig
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
Definition: stm32f4xx_tim.c:3070
TIM_GetCapture3
uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
Definition: stm32f4xx_tim.c:2061
TIM_BDTRConfig
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output ena...
Definition: stm32f4xx_tim.c:2221
TIM_OC1NPolarityConfig
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
Definition: stm32f4xx_tim.c:1620
ITStatus
enum FlagStatus ITStatus
TIM_Break2Cmd
void TIM_Break2Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM Break2 input.
Definition: stm32f30x_tim.c:2806
TIM_PrescalerConfig
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
Definition: stm32f4xx_tim.c:360
TIM_SetCompare6
void TIM_SetCompare6(TIM_TypeDef *TIMx, uint32_t Compare6)
Sets the TIMx Capture Compare6 Register value.
Definition: stm32f30x_tim.c:1351
TIM_SetAutoreload
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
Definition: stm32f4xx_tim.c:424
TIM_GetPrescaler
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
Definition: stm32f4xx_tim.c:452
TIM_OC1Init
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:673
TIM_OC4Init
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:915
TIM_OC2PolarityConfig
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
Definition: stm32f4xx_tim.c:1647
TIM_SetCounter
void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
Definition: stm32f4xx_tim.c:409
TIM_SelectSlaveMode
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint32_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
Definition: stm32f30x_tim.c:3584
TIM_ITRxExternalClockConfig
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
Definition: stm32f4xx_tim.c:2704
TIM_OC6PolarityConfig
void TIM_OC6PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 6 polarity.
Definition: stm32f30x_tim.c:2246
TIM_GetCapture2
uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
Definition: stm32f4xx_tim.c:2047
TIM_CounterModeConfig
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
Definition: stm32f4xx_tim.c:383
TIM_UpdateDisableConfig
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
Definition: stm32f4xx_tim.c:468
TIM_ForcedOC5Config
void TIM_ForcedOC5Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 5 waveform to active or inactive level.
Definition: stm32f30x_tim.c:1483
TIM_OC3PreloadConfig
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
Definition: stm32f4xx_tim.c:1297
TIM_ETRConfig
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
Definition: stm32f4xx_tim.c:3012
TIM_InternalClockConfig
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
Definition: stm32f4xx_tim.c:2683
TIM_OCStructInit
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
Definition: stm32f4xx_tim.c:978
TIM_SetClockDivision
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
Definition: stm32f4xx_tim.c:572
TIM_ClearOC6Ref
void TIM_ClearOC6Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF6 signal on an external event.
Definition: stm32f30x_tim.c:1981
TIM_ForcedOC2Config
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1153
TIM_ClearOC4Ref
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
Definition: stm32f4xx_tim.c:1564
TIM_OC6PreloadConfig
void TIM_OC6PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR6.
Definition: stm32f30x_tim.c:1685
TIM_GetCounter
uint32_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
Definition: stm32f4xx_tim.c:438
TIM_SetIC2Prescaler
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
Definition: stm32f4xx_tim.c:2120
TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition.
Definition: stm32f4xx_tim.h:55
TIM_SetIC1Prescaler
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
Definition: stm32f4xx_tim.c:2095
TIM_SelectGC5C1
void TIM_SelectGC5C1(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM Group Channel 5 and Channel 1, OC1REFC is the logical AND of OC1REFC and OC5REF...
Definition: stm32f30x_tim.c:1110
TIM_Break1Config
void TIM_Break1Config(TIM_TypeDef *TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
Configures the Break1 feature.
Definition: stm32f30x_tim.c:2739
TIM_OCInitTypeDef::TIM_OCMode
uint32_t TIM_OCMode
Definition: stm32f30x_tim.h:86
TIM_ICInitTypeDef
TIM Input Capture Init structure definition.
Definition: stm32f4xx_tim.h:119
TIM_SetCompare2
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
Definition: stm32f4xx_tim.c:1076
TIM_ARRPreloadConfig
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
Definition: stm32f4xx_tim.c:522
TIM_OC3NPolarityConfig
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
Definition: stm32f4xx_tim.c:1728
TIM_ClearOC2Ref
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
Definition: stm32f4xx_tim.c:1506
TIM_SelectOCxM
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode)
Selects the TIM Output Compare Mode.
Definition: stm32f30x_tim.c:1229
TIM_TypeDef
TIM.
Definition: stm32f4xx.h:1666
TIM_OC4FastConfig
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
Definition: stm32f4xx_tim.c:1446
TIM_OC4PreloadConfig
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
Definition: stm32f4xx_tim.c:1326
TIM_DMAConfig
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx&#39;s DMA interface.
Definition: stm32f4xx_tim.c:2591
TIM_OC5PolarityConfig
void TIM_OC5PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 5 polarity.
Definition: stm32f30x_tim.c:2219
TIM_OC3Init
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:835
TIM_OC2Init
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:754
TIM_OC3FastConfig
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
Definition: stm32f4xx_tim.c:1416
TIM_ForcedOC3Config
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1181
TIM_GetFlagStatus
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint32_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
Definition: stm32f30x_tim.c:3029
TIM_SelectMasterSlaveMode
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
Definition: stm32f4xx_tim.c:2982
TIM_TimeBaseInit
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
Definition: stm32f4xx_tim.c:288
TIM_SelectOnePulseMode
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx&#39;s One Pulse Mode.
Definition: stm32f4xx_tim.c:549
TIM_GetCapture1
uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
Definition: stm32f4xx_tim.c:2032
TIM_ForcedOC4Config
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1210
TIM_UIFRemap
void TIM_UIFRemap(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or resets the update interrupt flag (UIF)status bit Remapping. when sets, reading TIMx_CNT regis...
Definition: stm32f30x_tim.c:502
TIM_SelectInputTrigger
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
Definition: stm32f4xx_tim.c:2892
TIM_OC6Init
void TIM_OC6Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel6 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f30x_tim.c:1046
TIM_OCInitTypeDef
TIM Output Compare Init structure definition.
Definition: stm32f4xx_tim.h:84
TIM_ICInit
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
Definition: stm32f4xx_tim.c:1900
TIM_GetITStatus
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
Definition: stm32f4xx_tim.c:2513
TIM_GenerateEvent
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
Definition: stm32f4xx_tim.c:2410
TIM_CtrlPWMOutputs
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
Definition: stm32f4xx_tim.c:2265
TIM_SetCompare1
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
Definition: stm32f4xx_tim.c:1060
TIM_Break1Cmd
void TIM_Break1Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM Break1 input.
Definition: stm32f30x_tim.c:2781
TIM_PWMIConfig
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
Definition: stm32f4xx_tim.c:1975
TIM_BDTRInitTypeDef
BDTR structure definition.
Definition: stm32f4xx_tim.h:143
TIM_SelectOutputTrigger2
void TIM_SelectOutputTrigger2(TIM_TypeDef *TIMx, uint32_t TIM_TRGO2Source)
Selects the TIMx Trigger Output Mode2 (TRGO2).
Definition: stm32f30x_tim.c:3557
TIM_ClearFlag
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx&#39;s pending flags.
Definition: stm32f4xx_tim.c:2485
TIM_CCxCmd
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
Definition: stm32f4xx_tim.c:1786
TIM_OC3PolarityConfig
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
Definition: stm32f4xx_tim.c:1701
TIM_OC2NPolarityConfig
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
Definition: stm32f4xx_tim.c:1674
TIM_ITConfig
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
Definition: stm32f4xx_tim.c:2372
TIM_DMACmd
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx&#39;s DMA Requests.
Definition: stm32f4xx_tim.c:2618
TIM_ClearOC5Ref
void TIM_ClearOC5Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF5 signal on an external event.
Definition: stm32f30x_tim.c:1952
TIM_ETRClockMode2Config
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
Definition: stm32f4xx_tim.c:2821
TIM_Cmd
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
Definition: stm32f4xx_tim.c:592
TIM_OC4PolarityConfig
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
Definition: stm32f4xx_tim.c:1755
TIM_ICStructInit
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
Definition: stm32f4xx_tim.c:1956
TIM_OC2FastConfig
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
Definition: stm32f4xx_tim.c:1386

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:48