Functions
Double Buffer mode functions
STM32F4xx_StdPeriph_Driver | STM32F10x_StdPeriph_Driver | STM32F30x_StdPeriph_Driver » DMA » DMA_Private_Functions

Double Buffer mode functions. More...

Collaboration diagram for Double Buffer mode functions:

Functions

void DMA_ClearFlag (uint32_t DMAy_FLAG)
 Clears the DMAy Channelx's pending flags. More...
 
void DMA_ClearITPendingBit (uint32_t DMAy_IT)
 Clears the DMAy Channelx's interrupt pending bits. More...
 
void DMA_DoubleBufferModeCmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the double buffer mode for the selected DMA stream. More...
 
void DMA_DoubleBufferModeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory)
 Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target. More...
 
uint32_t DMA_GetCurrentMemoryTarget (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current memory target used by double buffer transfer. More...
 
FlagStatus DMA_GetFlagStatus (uint32_t DMAy_FLAG)
 Checks whether the specified DMAy Channelx flag is set or not. More...
 
ITStatus DMA_GetITStatus (uint32_t DMAy_IT)
 Checks whether the specified DMAy Channelx interrupt has occurred or not. More...
 
void DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
 Enables or disables the specified DMAy Channelx interrupts. More...
 
void DMA_MemoryTargetConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget)
 Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing. More...
 

Detailed Description

Double Buffer mode functions.

Interrupts and flags management functions.

 ===============================================================================
                    ##### Double Buffer mode functions #####
 ===============================================================================  
    [..]
    This subsection provides function allowing to configure and control the double 
    buffer mode parameters.
    
    [..]
    The Double Buffer mode can be used only when Circular mode is enabled.
    The Double Buffer mode cannot be used when transferring data from Memory to Memory.
    
    [..]
    The Double Buffer mode allows to set two different Memory addresses from/to which
    the DMA controller will access alternatively (after completing transfer to/from 
    target memory 0, it will start transfer to/from target memory 1).
    This allows to reduce software overhead for double buffering and reduce the CPU
    access time.
    
    [..]
    Two functions must be called before calling the DMA_Init() function:
      (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, 
          uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
      (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
      
    [..]
    DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address 
    and the first Memory target from/to which the transfer will start after 
    enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called 
    to enable the Double Buffer mode (or disable it when it should not be used).
  
    [..]
    Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is 
    stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
    used:
      (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, 
                uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
      (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
      
    [..]
    DMA_MemoryTargetConfig() can be called to modify the base address of one of 
    the two target Memories.
    The Memory of which the base address will be modified must not be currently 
    be used by the DMA Stream (ie. if the DMA Stream is currently transferring 
    from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
    To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
    returns the index of the Memory target currently in use by the DMA Stream.
 ===============================================================================
          ##### Interrupts and flags management functions #####
 ===============================================================================
    [..] This subsection provides functions allowing to configure the DMA Interrupt 
         sources and check or clear the flags or pending bits status.
         The user should identify which mode will be used in his application to manage 
         the DMA controller events: Polling mode or Interrupt mode. 
  
  *** Polling Mode ***
  ====================
    [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller 
         number, x : DMA channel number):
         (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
         (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
         (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
         (#) DMAy_FLAG_GLx : to indicate that at least one of the events described 
             above occurred.
    [..]         
    (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the 
        same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
    [..] In this Mode it is advised to use the following functions:
         (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
         (+) void DMA_ClearFlag(uint32_t DMA_FLAG);

  *** Interrupt Mode ***
  ======================
    [..] Each DMA channel can be managed through 4 Interrupts:
    (+) Interrupt Source
       (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete 
            event.
       (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete 
            event.
       (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
       (##) DMA_IT_GL: to indicate that at least one of the interrupts described 
            above occurred.
    -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of 
         the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
    [..] In this Mode it is advised to use the following functions:
         (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
         (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
         (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);

Function Documentation

void DMA_ClearFlag ( uint32_t  DMAy_FLAG)

Clears the DMAy Channelx's pending flags.

Parameters
DMAy_FLAGspecifies the flag to clear. This parameter can be any combination (for the same DMA) of the following values:
  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Note
Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags relative to the same channel (Transfer Complete, Half-transfer Complete and Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
Return values
None

Definition at line 657 of file stm32f30x_dma.c.

void DMA_ClearITPendingBit ( uint32_t  DMAy_IT)

Clears the DMAy Channelx's interrupt pending bits.

Parameters
DMAy_ITspecifies the DMAy interrupt pending bit to clear. This parameter can be any combination (for the same DMA) of the following values:
  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Note
Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other interrupts relative to the same channel (Transfer Complete, Half-transfer Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and DMAy_IT_TEx).
Return values
None

Definition at line 832 of file stm32f30x_dma.c.

void DMA_DoubleBufferModeCmd ( DMA_Stream_TypeDef *  DMAy_Streamx,
FunctionalState  NewState 
)

Enables or disables the double buffer mode for the selected DMA stream.

Note
This function can be called only when the DMA Stream is disabled.
Parameters
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
NewStatenew state of the DMAy Streamx double buffer mode. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 761 of file stm32f4xx_dma.c.

void DMA_DoubleBufferModeConfig ( DMA_Stream_TypeDef *  DMAy_Streamx,
uint32_t  Memory1BaseAddr,
uint32_t  DMA_CurrentMemory 
)

Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target.

Parameters
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
Memory1BaseAddrthe base address of the second buffer (Memory 1)
DMA_CurrentMemoryspecifies which memory will be first buffer for the transactions when the Stream will be enabled. This parameter can be one of the following values:
  • DMA_Memory_0: Memory 0 is the current buffer.
  • DMA_Memory_1: Memory 1 is the current buffer.
Note
Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
Return values
None

Definition at line 730 of file stm32f4xx_dma.c.

uint32_t DMA_GetCurrentMemoryTarget ( DMA_Stream_TypeDef *  DMAy_Streamx)

Returns the current memory target used by double buffer transfer.

Parameters
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
Return values
Thememory target number: 0 for Memory0 or 1 for Memory1.

Definition at line 828 of file stm32f4xx_dma.c.

FlagStatus DMA_GetFlagStatus ( uint32_t  DMAy_FLAG)

Checks whether the specified DMAy Channelx flag is set or not.

Parameters
DMAy_FLAGspecifies the flag to check. This parameter can be one of the following values:
  • DMA1_FLAG_GL1: DMA1 Channel1 global flag.
  • DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
  • DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
  • DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
  • DMA1_FLAG_GL2: DMA1 Channel2 global flag.
  • DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
  • DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
  • DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
  • DMA1_FLAG_GL3: DMA1 Channel3 global flag.
  • DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
  • DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
  • DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
  • DMA1_FLAG_GL4: DMA1 Channel4 global flag.
  • DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
  • DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
  • DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
  • DMA1_FLAG_GL5: DMA1 Channel5 global flag.
  • DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
  • DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
  • DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
  • DMA1_FLAG_GL6: DMA1 Channel6 global flag.
  • DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
  • DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
  • DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
  • DMA1_FLAG_GL7: DMA1 Channel7 global flag.
  • DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
  • DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
  • DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
  • DMA2_FLAG_GL1: DMA2 Channel1 global flag.
  • DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
  • DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
  • DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
  • DMA2_FLAG_GL2: DMA2 Channel2 global flag.
  • DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
  • DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
  • DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
  • DMA2_FLAG_GL3: DMA2 Channel3 global flag.
  • DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
  • DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
  • DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
  • DMA2_FLAG_GL4: DMA2 Channel4 global flag.
  • DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
  • DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
  • DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
  • DMA2_FLAG_GL5: DMA2 Channel5 global flag.
  • DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
  • DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
  • DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
Note
The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags relative to the same channel is set (Transfer Complete, Half-transfer Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or DMAy_FLAG_TEx).
Return values
Thenew state of DMAy_FLAG (SET or RESET).

Definition at line 561 of file stm32f30x_dma.c.

ITStatus DMA_GetITStatus ( uint32_t  DMAy_IT)

Checks whether the specified DMAy Channelx interrupt has occurred or not.

Parameters
DMAy_ITspecifies the DMAy interrupt source to check. This parameter can be one of the following values:
  • DMA1_IT_GL1: DMA1 Channel1 global interrupt.
  • DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
  • DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
  • DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
  • DMA1_IT_GL2: DMA1 Channel2 global interrupt.
  • DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
  • DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
  • DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
  • DMA1_IT_GL3: DMA1 Channel3 global interrupt.
  • DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
  • DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
  • DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
  • DMA1_IT_GL4: DMA1 Channel4 global interrupt.
  • DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
  • DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
  • DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
  • DMA1_IT_GL5: DMA1 Channel5 global interrupt.
  • DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
  • DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
  • DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
  • DMA1_IT_GL6: DMA1 Channel6 global interrupt.
  • DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
  • DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
  • DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
  • DMA1_IT_GL7: DMA1 Channel7 global interrupt.
  • DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
  • DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
  • DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
  • DMA2_IT_GL1: DMA2 Channel1 global interrupt.
  • DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
  • DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
  • DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
  • DMA2_IT_GL2: DMA2 Channel2 global interrupt.
  • DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
  • DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
  • DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
  • DMA2_IT_GL3: DMA2 Channel3 global interrupt.
  • DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
  • DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
  • DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
  • DMA2_IT_GL4: DMA2 Channel4 global interrupt.
  • DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
  • DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
  • DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
  • DMA2_IT_GL5: DMA2 Channel5 global interrupt.
  • DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
  • DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
  • DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
Note
The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other interrupts relative to the same channel is set (Transfer Complete, Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx or DMAy_IT_TEx).
Return values
Thenew state of DMAy_IT (SET or RESET).

Definition at line 736 of file stm32f30x_dma.c.

void DMA_ITConfig ( DMA_Channel_TypeDef *  DMAy_Channelx,
uint32_t  DMA_IT,
FunctionalState  NewState 
)

Enables or disables the specified DMAy Channelx interrupts.

Parameters
DMAy_Channelxwhere y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
DMA_ITspecifies the DMA interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
NewStatenew state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.
Return values
None

Definition at line 481 of file stm32f30x_dma.c.

void DMA_MemoryTargetConfig ( DMA_Stream_TypeDef *  DMAy_Streamx,
uint32_t  MemoryBaseAddr,
uint32_t  DMA_MemoryTarget 
)

Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing.

Parameters
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
MemoryBaseAddrThe base address of the target memory buffer
DMA_MemoryTargetNext memory target to be used. This parameter can be one of the following values:
  • DMA_Memory_0: To use the memory address 0
  • DMA_Memory_1: To use the memory address 1
Note
It is not allowed to modify the Base Address of a target Memory when this target is involved in the current transfer. ie. If the DMA Stream is currently transferring to/from Memory 1, then it not possible to modify Base address of Memory 1, but it is possible to modify Base address of Memory 0. To know which Memory is currently used, you can use the function DMA_GetCurrentMemoryTarget().
Return values
None

Definition at line 802 of file stm32f4xx_dma.c.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:55