STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
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1 
28 /* Define to prevent recursive inclusion -------------------------------------*/
29 #ifndef __STM32F4xx_RCC_H
30 #define __STM32F4xx_RCC_H
31 
32 #ifdef __cplusplus
33  extern "C" {
34 #endif
35 
36 /* Includes ------------------------------------------------------------------*/
37 #include "stm32f4xx.h"
38 
47 /* Exported types ------------------------------------------------------------*/
48 typedef struct
49 {
50  uint32_t SYSCLK_Frequency;
51  uint32_t HCLK_Frequency;
52  uint32_t PCLK1_Frequency;
53  uint32_t PCLK2_Frequency;
54 }RCC_ClocksTypeDef;
55 
56 /* Exported constants --------------------------------------------------------*/
57 
65 #define RCC_HSE_OFF ((uint8_t)0x00)
66 #define RCC_HSE_ON ((uint8_t)0x01)
67 #define RCC_HSE_Bypass ((uint8_t)0x05)
68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
69  ((HSE) == RCC_HSE_Bypass))
70 
77 #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
78 #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
80  ((SOURCE) == RCC_PLLSource_HSE))
81 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
82 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
83 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
84 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
85 
86 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
87 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
88 
96 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
97 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
98 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
99 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
100  ((SOURCE) == RCC_SYSCLKSource_HSE) || \
101  ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
102 
109 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
110 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
111 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
112 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
113 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
114 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
115 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
116 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
117 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
118 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
119  ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
120  ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
121  ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
122  ((HCLK) == RCC_SYSCLK_Div512))
123 
130 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
131 #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
132 #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
133 #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
134 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
135 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
136  ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
137  ((PCLK) == RCC_HCLK_Div16))
138 
145 #define RCC_IT_LSIRDY ((uint8_t)0x01)
146 #define RCC_IT_LSERDY ((uint8_t)0x02)
147 #define RCC_IT_HSIRDY ((uint8_t)0x04)
148 #define RCC_IT_HSERDY ((uint8_t)0x08)
149 #define RCC_IT_PLLRDY ((uint8_t)0x10)
150 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
151 #define RCC_IT_CSS ((uint8_t)0x80)
152 
153 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
154 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
155  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
156  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
157  ((IT) == RCC_IT_PLLI2SRDY))
158 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
159 
167 #define RCC_LSE_OFF ((uint8_t)0x00)
168 #define RCC_LSE_ON ((uint8_t)0x01)
169 #define RCC_LSE_Bypass ((uint8_t)0x04)
170 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
171  ((LSE) == RCC_LSE_Bypass))
172 
179 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
180 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
181 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
182 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
183 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
184 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
185 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
186 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
187 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
188 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
189 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
190 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
191 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
192 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
193 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
194 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
195 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
196 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
197 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
198 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
199 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
200 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
201 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
202 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
203 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
204 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
205 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
206 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
207 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
208 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
209 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
210 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
211 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
212  ((SOURCE) == RCC_RTCCLKSource_LSI) || \
213  ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
214  ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
215  ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
216  ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
217  ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
218  ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
219  ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
220  ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
221  ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
222  ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
223  ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
224  ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
225  ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
226  ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
227  ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
228  ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
229  ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
230  ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
231  ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
232  ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
233  ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
234  ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
235  ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
236  ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
237  ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
238  ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
239  ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
240  ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
241  ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
242  ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
243 
250 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
251 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
252 
253 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
254 
261 #define RCC_TIMPrescDesactivated ((uint8_t)0x00)
262 #define RCC_TIMPrescActivated ((uint8_t)0x01)
263 
264 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
265 
272 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
273 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
274 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
275 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
276 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
277 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
278 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
279 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
280 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
281 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
282 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
283 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
284 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
285 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
286 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
287 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
288 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
289 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
290 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
291 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
292 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
293 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
294 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
295 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
296 
297 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
298 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
299 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81906E00) == 0x00) && ((PERIPH) != 0x00))
300 
301 
309 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
310 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
311 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
312 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
313 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
314 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
315 
322 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
323 
324 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
325 
332 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
333 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
334 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
335 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
336 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
337 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
338 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
339 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
340 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
341 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
342 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
343 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
344 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
345 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
346 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
347 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
348 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
349 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
350 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
351 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
352 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
353 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
354 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
355 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
356 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
357 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
358 
365 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
366 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
367 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
368 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
369 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
370 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
371 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
372 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
373 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
374 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
375 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
376 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
377 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
378 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
379 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
380 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
381 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
382 
383 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC880CC) == 0x00) && ((PERIPH) != 0x00))
384 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFC886CC) == 0x00) && ((PERIPH) != 0x00))
385 
386 
394 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
395 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
396 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
397 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
398 #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
399 #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
400 #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
401 #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
402 #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
403 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
404  ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
405 
406 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
407  ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
408  ((DIV) == RCC_MCO1Div_5))
409 
416 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
417 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
418 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
419 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
420 #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
421 #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
422 #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
423 #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
424 #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
425 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
426  ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
427 
428 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
429  ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
430  ((DIV) == RCC_MCO2Div_5))
431 
438 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
439 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
440 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
441 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
442 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
443 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
444 #define RCC_FLAG_BORRST ((uint8_t)0x79)
445 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
446 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
447 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
448 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
449 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
450 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
451 
452 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
453  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
454  ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
455  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
456  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
457  ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
458  ((FLAG) == RCC_FLAG_PLLI2SRDY))
459 
460 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
461 
469 /* Exported macro ------------------------------------------------------------*/
470 /* Exported functions --------------------------------------------------------*/
471 
472 /* Function used to set the RCC clock configuration to the default reset state */
473 void RCC_DeInit(void);
474 
475 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
476 void RCC_HSEConfig(uint8_t RCC_HSE);
477 ErrorStatus RCC_WaitForHSEStartUp(void);
478 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
479 void RCC_HSICmd(FunctionalState NewState);
480 void RCC_LSEConfig(uint8_t RCC_LSE);
481 void RCC_LSICmd(FunctionalState NewState);
482 
483 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
484 void RCC_PLLCmd(FunctionalState NewState);
485 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
486 void RCC_PLLI2SCmd(FunctionalState NewState);
487 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
488 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
489 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
490 
491 /* System, AHB and APB busses clocks configuration functions ******************/
492 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
493 uint8_t RCC_GetSYSCLKSource(void);
494 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
495 void RCC_PCLK1Config(uint32_t RCC_HCLK);
496 void RCC_PCLK2Config(uint32_t RCC_HCLK);
497 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
498 
499 /* Peripheral clocks configuration functions **********************************/
500 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
501 void RCC_RTCCLKCmd(FunctionalState NewState);
502 void RCC_BackupResetCmd(FunctionalState NewState);
503 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
504 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
505 
506 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
507 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
508 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
509 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
510 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
511 
512 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
513 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
514 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
515 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
516 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
517 
518 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
519 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
520 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
521 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
522 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
523 
524 /* Interrupts and flags management functions **********************************/
525 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
526 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
527 void RCC_ClearFlag(void);
528 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
529 void RCC_ClearITPendingBit(uint8_t RCC_IT);
530 
531 #ifdef __cplusplus
532 }
533 #endif
534 
535 #endif /* __STM32F4xx_RCC_H */
536 
545 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_AHB1PeriphClockLPModeCmd
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2296
RCC_AHB3PeriphClockLPModeCmd
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
Definition: STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c:1572
FlagStatus
FlagStatus
Definition: stm32f4xx.h:706
RCC_MCO2Config
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
Selects the clock source to output on MCO2 pin(PC9).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:949
RCC_APB1PeriphClockCmd
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2004
RCC_WaitForHSEStartUp
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:308
FunctionalState
FunctionalState
Definition: stm32f4xx.h:708
RCC_RTCCLKConfig
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1470
RCC_PLLConfig
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
Definition: STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c:454
RCC_AHB1PeriphResetCmd
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Forces or releases AHB1 peripheral reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2094
RCC_SYSCLKConfig
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1149
RCC_AHB1PeriphClockCmd
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1885
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
RCC_APB2PeriphClockCmd
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2051
RCC_BackupResetCmd
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1519
RCC_APB1PeriphClockLPModeCmd
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2415
RCC_PLLCmd
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:563
RCC_GetITStatus
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2890
ITStatus
enum FlagStatus ITStatus
RCC_APB1PeriphResetCmd
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2204
RCC_AHB2PeriphClockCmd
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1917
RCC_LSEConfig
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:400
RCC_RTCCLKCmd
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1502
RCC_PCLK1Config
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1234
RCC_I2SCLKConfig
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
Definition: stm32f30x_rcc.c:1480
RCC_PLLI2SConfig
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
Configures the PLLI2S clock multiplication and division factors.
Definition: STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c:503
RCC_LSICmd
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:440
RCC_DeInit
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:225
RCC_HSICmd
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:375
RCC_AHB3PeriphResetCmd
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Forces or releases AHB3 peripheral reset.
Definition: STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c:1378
RCC_PCLK2Config
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1265
ErrorStatus
ErrorStatus
Definition: stm32f4xx.h:711
RCC_APB2PeriphResetCmd
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2247
RCC_ClearFlag
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2870
RCC_ClockSecuritySystemCmd
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:879
RCC_PLLI2SCmd
void RCC_PLLI2SCmd(FunctionalState NewState)
Enables or disables the PLLI2S.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:732
RCC_AHB3PeriphClockCmd
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock.
Definition: STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c:1190
RCC_HSEConfig
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:284
RCC_AHB2PeriphClockLPModeCmd
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2328
RCC_ClearITPendingBit
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC&#39;s interrupt pending bits.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2924
RCC_ClocksTypeDef
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.h:48
RCC_GetFlagStatus
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2825
RCC_ITConfig
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2788
RCC_APB2PeriphClockLPModeCmd
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2462
RCC_MCO1Config
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
Selects the clock source to output on MCO1 pin(PA8).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:904
RCC_GetClocksFreq
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1317
RCC_GetSYSCLKSource
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1178
RCC_AHB2PeriphResetCmd
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Forces or releases AHB2 peripheral reset.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:2123
RCC_HCLKConfig
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1203
RCC_AdjustHSICalibrationValue
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:339
RCC_TIMCLKPresConfig
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
Configures the Timers clocks prescalers selection.
Definition: CMSIS/CM4/DeviceSupport/ST/STM32F4xx/stm32f4xx_rcc.c:1843

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:49