efc.cpp

Go to the documentation of this file.

#include "efc.h"


#ifdef __cplusplus
extern "C" {
#endif



/* Address definition for read operation */
# define READ_BUFF_ADDR0    IFLASH0_ADDR
# define READ_BUFF_ADDR1    IFLASH1_ADDR

/* Flash Writing Protection Key */
#define FWP_KEY    0x5Au

#if (SAM4S || SAM4E)
#define EEFC_FCR_FCMD(value) \
        ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
#define EEFC_ERROR_FLAGS  (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR)
#else
#define EEFC_ERROR_FLAGS  (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)
#endif



/*
 * Local function declaration.
 * Because they are RAM functions, they need 'extern' declaration.
 */
extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr);
extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr);

uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws)
{
        efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws));
        return EFC_RC_OK;
}

void efc_enable_frdy_interrupt(Efc *p_efc)
{
        uint32_t ul_fmr = p_efc->EEFC_FMR;

        efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY);
}

void efc_disable_frdy_interrupt(Efc *p_efc)
{
        uint32_t ul_fmr = p_efc->EEFC_FMR;

        efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY));
}

void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode)
{
        uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM);

        efc_write_fmr(p_efc, ul_fmr | ul_mode);
}

uint32_t efc_get_flash_access_mode(Efc *p_efc)
{
        return (p_efc->EEFC_FMR & EEFC_FMR_FAM);
}

void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws)
{
        uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk);

        efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws));
}

uint32_t efc_get_wait_state(Efc *p_efc)
{
        return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos);
}

uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command,
                uint32_t ul_argument)
{
        /* Unique ID commands are not supported. */
        if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) {
                return EFC_RC_NOT_SUPPORT;
        }

        /* Use IAP function with 2 parameters in ROM. */
        static uint32_t(*iap_perform_command) (uint32_t, uint32_t);
        uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1;

        iap_perform_command =
                        (uint32_t(*)(uint32_t, uint32_t))
                        *((uint32_t *) CHIP_FLASH_IAP_ADDRESS);
        iap_perform_command(ul_efc_nb,
                        EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) |
                        EEFC_FCR_FCMD(ul_command));
        return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS);
}

uint32_t efc_get_status(Efc *p_efc)
{
        return p_efc->EEFC_FSR;
}

uint32_t efc_get_result(Efc *p_efc)
{
        return p_efc->EEFC_FRR;
}

RAMFUNC
uint32_t efc_perform_read_sequence(Efc *p_efc,
                uint32_t ul_cmd_st, uint32_t ul_cmd_sp,
                uint32_t *p_ul_buf, uint32_t ul_size)
{
        volatile uint32_t ul_status;
        uint32_t ul_cnt;

        uint32_t *p_ul_data =
                        (uint32_t *) ((p_efc == EFC0) ?
                        READ_BUFF_ADDR0 : READ_BUFF_ADDR1);

        if (p_ul_buf == NULL) {
                return EFC_RC_INVALID;
        }

        p_efc->EEFC_FMR |= (0x1u << 16);

        /* Send the Start Read command */

        p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0)
                        | EEFC_FCR_FCMD(ul_cmd_st);
        /* Wait for the FRDY bit in the Flash Programming Status Register
         * (EEFC_FSR) falls.
         */
        do {
                ul_status = p_efc->EEFC_FSR;
        } while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY);

        /* The data is located in the first address of the Flash
         * memory mapping.
         */
        for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) {
                p_ul_buf[ul_cnt] = p_ul_data[ul_cnt];
        }

        /* To stop the read mode */
        p_efc->EEFC_FCR =
                        EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) |
                        EEFC_FCR_FCMD(ul_cmd_sp);
        /* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR)
         * rises.
         */
        do {
                ul_status = p_efc->EEFC_FSR;
        } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);

        p_efc->EEFC_FMR &= ~(0x1u << 16);

        return EFC_RC_OK;
}

RAMFUNC
void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr)
{
        p_efc->EEFC_FMR = ul_fmr;
}

RAMFUNC
uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr)
{
        volatile uint32_t ul_status;

        p_efc->EEFC_FCR = ul_fcr;
        do {
                ul_status = p_efc->EEFC_FSR;
        } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);

        return (ul_status & EEFC_ERROR_FLAGS);
}



#ifdef __cplusplus
}
#endif