Classes | Defines | Enumerations
eeprom.h File Reference
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Classes

struct  ath5k_chan_pcal_info
struct  ath5k_chan_pcal_info_rf2413
struct  ath5k_chan_pcal_info_rf5111
struct  ath5k_chan_pcal_info_rf5112
struct  ath5k_edge_power
struct  ath5k_eeprom_info
struct  ath5k_pdgain_info
struct  ath5k_rate_pcal_info

Defines

#define AR5K_CTL_CUSTOM   0x20
#define AR5K_CTL_ETSI   0x30
#define AR5K_CTL_FCC   0x10
#define AR5K_CTL_MKK   0x40
#define AR5K_CTL_NO_CTL   0xff
#define AR5K_CTL_NO_REGDOMAIN   0xf0
#define AR5K_EEPROM_5413_SPUR_CHAN_1   1640
#define AR5K_EEPROM_5413_SPUR_CHAN_2   1200
#define AR5K_EEPROM_AES_DIS(_v)   (((_v) >> 1) & 0x1)
#define AR5K_EEPROM_ANT_GAIN(_v)   AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
#define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)   ((s8)((_v) & 0xff))
#define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)   ((s8)(((_v) >> 8) & 0xff))
#define AR5K_EEPROM_ART_BUILD_NUM(_v)   (((_v) >> 10) & 0x3f)
#define AR5K_EEPROM_BURST_DIS(_v)   (((_v) >> 3) & 0x1)
#define AR5K_EEPROM_CAL_DATA_START(_v)   (((_v) >> 4) & 0xfff)
#define AR5K_EEPROM_CCK_OFDM_DELTA   15
#define AR5K_EEPROM_CHANNEL_DIS   0xff
#define AR5K_EEPROM_CHANNEL_POWER   8
#define AR5K_EEPROM_CHECKSUM   0x00c0 /* EEPROM checksum */
#define AR5K_EEPROM_COMP_DIS(_v)   ((_v) & 0x1)
#define AR5K_EEPROM_CTL(_v)   AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */
#define AR5K_EEPROM_EAR_FILE_ID(_v)   ((_v) & 0xff)
#define AR5K_EEPROM_EAR_FILE_VERSION(_v)   ((_v) & 0xff)
#define AR5K_EEPROM_EARSTART(_v)   ((_v) & 0xfff)
#define AR5K_EEPROM_EEMAP(_v)   (((_v) >> 14) & 0x3)
#define AR5K_EEPROM_EEP_DELTA   10
#define AR5K_EEPROM_EEP_FILE_VERSION(_v)   (((_v) >> 8) & 0xff)
#define AR5K_EEPROM_EEP_SCALE   100
#define AR5K_EEPROM_FCC_MID_EN   (((_v) >> 6) & 0x1)
#define AR5K_EEPROM_FF_DIS(_v)   (((_v) >> 2) & 0x1)
#define AR5K_EEPROM_FREQ_M(_v)   AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
#define AR5K_EEPROM_GROUP1_OFFSET   0x0
#define AR5K_EEPROM_GROUP2_OFFSET   0x5
#define AR5K_EEPROM_GROUP3_OFFSET   0x37
#define AR5K_EEPROM_GROUP4_OFFSET   0x46
#define AR5K_EEPROM_GROUP5_OFFSET   0x55
#define AR5K_EEPROM_GROUP6_OFFSET   0x65
#define AR5K_EEPROM_GROUP7_OFFSET   0x69
#define AR5K_EEPROM_GROUP8_OFFSET   0x6f
#define AR5K_EEPROM_GROUPS_START(_v)   AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */
#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v)   (((_v) >> 14) & 0x1)
#define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v)   (((_v) >> 15) & 0x1)
#define AR5K_EEPROM_HDR   AR5K_EEPROM_INFO(2) /* Header that contains the device caps */
#define AR5K_EEPROM_HDR_11A(_v)   (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
#define AR5K_EEPROM_HDR_11B(_v)   (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
#define AR5K_EEPROM_HDR_11G(_v)   (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
#define AR5K_EEPROM_HDR_DEVICE(_v)   (((_v) >> 11) & 0x7)
#define AR5K_EEPROM_HDR_RFKILL(_v)   (((_v) >> 14) & 0x1) /* Device has RFKill support */
#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)   (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */
#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)   (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */
#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)   (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */
#define AR5K_EEPROM_HDR_XR2_DIS(_v)   (((_v) >> 12) & 0x1)
#define AR5K_EEPROM_HDR_XR5_DIS(_v)   (((_v) >> 13) & 0x1)
#define AR5K_EEPROM_HEAVY_CLIP_EN(_v)   (((_v) >> 8) & 0x1)
#define AR5K_EEPROM_I_GAIN   10
#define AR5K_EEPROM_INFO(_n)   (AR5K_EEPROM_INFO_BASE + (_n))
#define AR5K_EEPROM_INFO_BASE   0x00c0 /* EEPROM header */
#define AR5K_EEPROM_INFO_CKSUM   0xffff
#define AR5K_EEPROM_INFO_MAX   (0x400 - AR5K_EEPROM_INFO_BASE)
#define AR5K_EEPROM_IS_HB63   0x000b /* Talon detect */
#define AR5K_EEPROM_JAP_11A_NEW_EN   (((_v) >> 10) & 0x1)
#define AR5K_EEPROM_JAP_U1EVEN_EN   (((_v) >> 7) & 0x1)
#define AR5K_EEPROM_JAP_U1ODD_EN   (((_v) >> 9) & 0x1)
#define AR5K_EEPROM_JAP_U2_EN   (((_v) >> 8) & 0x1)
#define AR5K_EEPROM_KEY_CACHE_SIZE(_v)   (((_v) >> 12) & 0xf)
#define AR5K_EEPROM_MAGIC   0x003d /* EEPROM Magic number */
#define AR5K_EEPROM_MAGIC_5210   0x0000145a /* 5210 */
#define AR5K_EEPROM_MAGIC_5211   0x0000145b /* 5211 */
#define AR5K_EEPROM_MAGIC_5212   0x0000145c /* 5212 */
#define AR5K_EEPROM_MAGIC_VALUE   0x5aa5 /* Default - found on EEPROM */
#define AR5K_EEPROM_MASK_R0(_v)   (((_v) >> 2) & 0x3)
#define AR5K_EEPROM_MASK_R1(_v)   ((_v) & 0x3)
#define AR5K_EEPROM_MAX_CHAN   10
#define AR5K_EEPROM_MAX_CTLS   32
#define AR5K_EEPROM_MAX_QCU(_v)   (((_v) >> 4) & 0xf)
#define AR5K_EEPROM_MISC0   AR5K_EEPROM_INFO(4)
#define AR5K_EEPROM_MISC1   AR5K_EEPROM_INFO(5)
#define AR5K_EEPROM_MISC2   AR5K_EEPROM_INFO(6)
#define AR5K_EEPROM_MISC3   AR5K_EEPROM_INFO(7)
#define AR5K_EEPROM_MISC4   AR5K_EEPROM_INFO(8)
#define AR5K_EEPROM_MISC5   AR5K_EEPROM_INFO(9)
#define AR5K_EEPROM_MISC6   AR5K_EEPROM_INFO(10)
#define AR5K_EEPROM_MODE_11A   0
#define AR5K_EEPROM_MODE_11B   1
#define AR5K_EEPROM_MODE_11G   2
#define AR5K_EEPROM_MODES_11A(_v)   AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
#define AR5K_EEPROM_MODES_11B(_v)   AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
#define AR5K_EEPROM_MODES_11G(_v)   AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
#define AR5K_EEPROM_N_2GHZ_CHAN   3
#define AR5K_EEPROM_N_2GHZ_CHAN_2413   4
#define AR5K_EEPROM_N_2GHZ_CHAN_MAX   4
#define AR5K_EEPROM_N_5GHZ_CHAN   10
#define AR5K_EEPROM_N_CTLS(_v)   AR5K_EEPROM_OFF(_v, 16, 32)
#define AR5K_EEPROM_N_EDGES   8
#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ   35
#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ   55
#define AR5K_EEPROM_N_INTERCEPTS   11
#define AR5K_EEPROM_N_IQ_CAL   2
#define AR5K_EEPROM_N_MODES   3
#define AR5K_EEPROM_N_OBDB   4
#define AR5K_EEPROM_N_PCDAC   11
#define AR5K_EEPROM_N_PD_CURVES   4
#define AR5K_EEPROM_N_PD_GAINS   4
#define AR5K_EEPROM_N_PD_POINTS   5
#define AR5K_EEPROM_N_PHASE_CAL   5
#define AR5K_EEPROM_N_POWER_LOC_11B   4
#define AR5K_EEPROM_N_POWER_LOC_11G   6
#define AR5K_EEPROM_N_PWR_POINTS_5111   11
#define AR5K_EEPROM_N_SPUR_CHANS   5
#define AR5K_EEPROM_N_TEST_FREQ   8
#define AR5K_EEPROM_N_XPD0_POINTS   4
#define AR5K_EEPROM_N_XPD3_POINTS   3
#define AR5K_EEPROM_NO_SPUR   0x8000
#define AR5K_EEPROM_NON_EDGE_M   0x40
#define AR5K_EEPROM_OBDB0_2GHZ   0x00ec
#define AR5K_EEPROM_OBDB1_2GHZ   0x00ed
#define AR5K_EEPROM_OBDB_DIS   0xffff
#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3)   (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
#define AR5K_EEPROM_PCDAC_M   0x3f
#define AR5K_EEPROM_PCDAC_START   1
#define AR5K_EEPROM_PCDAC_STEP   1
#define AR5K_EEPROM_PCDAC_STOP   63
#define AR5K_EEPROM_PCIE_OFFSET   0x02 /* Contains offset to PCI-E infos */
#define AR5K_EEPROM_PCIE_SERDES_SECTION
#define AR5K_EEPROM_POWER_M   0x3f
#define AR5K_EEPROM_POWER_MAX   3150
#define AR5K_EEPROM_POWER_MIN   0
#define AR5K_EEPROM_POWER_STEP   50
#define AR5K_EEPROM_POWER_TABLE_SIZE   64
#define AR5K_EEPROM_PROTECT   0x003f /* EEPROM protect status */
#define AR5K_EEPROM_PROTECT_RD_0_31   0x0001 /* Read protection bit for offsets 0x0 - 0x1f */
#define AR5K_EEPROM_PROTECT_RD_128_191   0x0040 /* 0x80 - 0xbf (regdom) */
#define AR5K_EEPROM_PROTECT_RD_192_207   0x0100 /* 0xc0 - 0xcf */
#define AR5K_EEPROM_PROTECT_RD_208_223   0x0400 /* 0xd0 - 0xdf */
#define AR5K_EEPROM_PROTECT_RD_224_239   0x1000 /* 0xe0 - 0xef */
#define AR5K_EEPROM_PROTECT_RD_240_255   0x4000 /* 0xf0 - 0xff */
#define AR5K_EEPROM_PROTECT_RD_32_63   0x0004 /* 0x20 - 0x3f */
#define AR5K_EEPROM_PROTECT_RD_64_127   0x0010 /* 0x40 - 0x7f */
#define AR5K_EEPROM_PROTECT_WR_0_31   0x0002 /* Write protection bit for offsets 0x0 - 0x1f */
#define AR5K_EEPROM_PROTECT_WR_128_191   0x0080
#define AR5K_EEPROM_PROTECT_WR_192_207   0x0200
#define AR5K_EEPROM_PROTECT_WR_208_223   0x0800
#define AR5K_EEPROM_PROTECT_WR_224_239   0x2000
#define AR5K_EEPROM_PROTECT_WR_240_255   0x8000
#define AR5K_EEPROM_PROTECT_WR_32_63   0x0008
#define AR5K_EEPROM_PROTECT_WR_64_127   0x0020
#define AR5K_EEPROM_READ(_o, _v)
#define AR5K_EEPROM_READ_HDR(_o, _v)   AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
#define AR5K_EEPROM_REG_DOMAIN   0x00bf /* EEPROM regdom */
#define AR5K_EEPROM_RFKILL   0x0f
#define AR5K_EEPROM_RFKILL_GPIO_SEL   0x0000001c
#define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
#define AR5K_EEPROM_RFKILL_POLARITY   0x00000002
#define AR5K_EEPROM_RFKILL_POLARITY_S   1
#define AR5K_EEPROM_RX_CHAIN_DIS   (((_v) >> 3) & 0x8)
#define AR5K_EEPROM_SCALE_OC_DELTA(_x)   (((_x) * 2) / 10)
#define AR5K_EEPROM_SPUR_CHAN_MASK   0x3FFF
#define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)
#define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)
#define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)
#define AR5K_EEPROM_TARGET_PWRSTART(_v)   ((_v) & 0xfff)
#define AR5K_EEPROM_TX_CHAIN_DIS   ((_v) & 0x8)
#define AR5K_EEPROM_VERSION   AR5K_EEPROM_INFO(1) /* EEPROM Version */
#define AR5K_EEPROM_VERSION_3_0   0x3000 /* No idea what's going on before this version */
#define AR5K_EEPROM_VERSION_3_1   0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */
#define AR5K_EEPROM_VERSION_3_2   0x3002 /* different frequency representation (eeprom_bin2freq) */
#define AR5K_EEPROM_VERSION_3_3   0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
#define AR5K_EEPROM_VERSION_3_4   0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
#define AR5K_EEPROM_VERSION_4_0   0x4000 /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
#define AR5K_EEPROM_VERSION_4_1   0x4001 /* has ee_margin_tx_rx (eeprom_init) */
#define AR5K_EEPROM_VERSION_4_2   0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */
#define AR5K_EEPROM_VERSION_4_3   0x4003 /* power calibration changes */
#define AR5K_EEPROM_VERSION_4_4   0x4004
#define AR5K_EEPROM_VERSION_4_5   0x4005
#define AR5K_EEPROM_VERSION_4_6   0x4006 /* has ee_scaled_cck_delta */
#define AR5K_EEPROM_VERSION_4_7   0x3007 /* 4007 ? */
#define AR5K_EEPROM_VERSION_4_9   0x4009 /* EAR futureproofing */
#define AR5K_EEPROM_VERSION_5_0   0x5000 /* Has 2413 PDADC calibration etc */
#define AR5K_EEPROM_VERSION_5_1   0x5001 /* Has capability values */
#define AR5K_EEPROM_VERSION_5_3   0x5003 /* Has spur mitigation tables */
#define AR5K_SPUR_CHAN_WIDTH   87
#define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz   3125
#define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz   6250

Enumerations

enum  ath5k_ant_table {
  AR5K_ANT_CTL = 0, AR5K_ANT_SWTABLE_A = 1, AR5K_ANT_SWTABLE_B = 2, AR5K_ANT_MAX,
  AR5K_ANT_CTL = 0, AR5K_ANT_SWTABLE_A = 1, AR5K_ANT_SWTABLE_B = 2, AR5K_ANT_MAX,
  AR5K_ANT_CTL = 0, AR5K_ANT_SWTABLE_A = 1, AR5K_ANT_SWTABLE_B = 2, AR5K_ANT_MAX
}
enum  ath5k_ctl_mode {
  AR5K_CTL_11A = 0, AR5K_CTL_11B = 1, AR5K_CTL_11G = 2, AR5K_CTL_TURBO = 3,
  AR5K_CTL_TURBOG = 4, AR5K_CTL_2GHT20 = 5, AR5K_CTL_5GHT20 = 6, AR5K_CTL_2GHT40 = 7,
  AR5K_CTL_5GHT40 = 8, AR5K_CTL_MODE_M = 15, AR5K_CTL_11A = 0, AR5K_CTL_11B = 1,
  AR5K_CTL_11G = 2, AR5K_CTL_TURBO = 3, AR5K_CTL_TURBOG = 4, AR5K_CTL_2GHT20 = 5,
  AR5K_CTL_5GHT20 = 6, AR5K_CTL_2GHT40 = 7, AR5K_CTL_5GHT40 = 8, AR5K_CTL_MODE_M = 15,
  AR5K_CTL_11A = 0, AR5K_CTL_11B = 1, AR5K_CTL_11G = 2, AR5K_CTL_TURBO = 3,
  AR5K_CTL_TURBOG = 4, AR5K_CTL_2GHT20 = 5, AR5K_CTL_5GHT20 = 6, AR5K_CTL_2GHT40 = 7,
  AR5K_CTL_5GHT40 = 8, AR5K_CTL_MODE_M = 15
}
enum  ath5k_eeprom_freq_bands {
  AR5K_EEPROM_BAND_5GHZ = 0, AR5K_EEPROM_BAND_2GHZ = 1, AR5K_EEPROM_N_FREQ_BANDS, AR5K_EEPROM_BAND_5GHZ = 0,
  AR5K_EEPROM_BAND_2GHZ = 1, AR5K_EEPROM_N_FREQ_BANDS, AR5K_EEPROM_BAND_5GHZ = 0, AR5K_EEPROM_BAND_2GHZ = 1,
  AR5K_EEPROM_N_FREQ_BANDS
}
enum  ath5k_powertable_type {
  AR5K_PWRTABLE_PWR_TO_PCDAC = 0, AR5K_PWRTABLE_LINEAR_PCDAC = 1, AR5K_PWRTABLE_PWR_TO_PDADC = 2, AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
  AR5K_PWRTABLE_LINEAR_PCDAC = 1, AR5K_PWRTABLE_PWR_TO_PDADC = 2, AR5K_PWRTABLE_PWR_TO_PCDAC = 0, AR5K_PWRTABLE_LINEAR_PCDAC = 1,
  AR5K_PWRTABLE_PWR_TO_PDADC = 2
}

Define Documentation

#define AR5K_CTL_CUSTOM   0x20

Definition at line 306 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_CTL_ETSI   0x30

Definition at line 307 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_CTL_FCC   0x10

Definition at line 305 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_CTL_MKK   0x40

Definition at line 308 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_CTL_NO_CTL   0xff

Definition at line 317 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_CTL_NO_REGDOMAIN   0xf0

Definition at line 314 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_5413_SPUR_CHAN_1   1640

Definition at line 258 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_5413_SPUR_CHAN_2   1200

Definition at line 260 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_AES_DIS (   _v)    (((_v) >> 1) & 0x1)

Definition at line 144 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_ANT_GAIN (   _v)    AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)

Definition at line 113 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_ANT_GAIN_2GHZ (   _v)    ((s8)((_v) & 0xff))

Definition at line 115 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_ANT_GAIN_5GHZ (   _v)    ((s8)(((_v) >> 8) & 0xff))

Definition at line 114 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_ART_BUILD_NUM (   _v)    (((_v) >> 10) & 0x3f)

Definition at line 134 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_BURST_DIS (   _v)    (((_v) >> 3) & 0x1)

Definition at line 146 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_CAL_DATA_START (   _v)    (((_v) >> 4) & 0xfff)

Definition at line 138 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_CCK_OFDM_DELTA   15

Definition at line 247 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_CHANNEL_DIS   0xff

Definition at line 228 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_CHANNEL_POWER   8

Definition at line 225 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_CHECKSUM   0x00c0 /* EEPROM checksum */

Definition at line 70 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_COMP_DIS (   _v)    ((_v) & 0x1)

Definition at line 143 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_CTL (   _v)    AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */

Definition at line 164 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_EAR_FILE_ID (   _v)    ((_v) & 0xff)

Definition at line 135 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_EAR_FILE_VERSION (   _v)    ((_v) & 0xff)

Definition at line 131 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_EARSTART (   _v)    ((_v) & 0xfff)

Definition at line 119 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_EEMAP (   _v)    (((_v) >> 14) & 0x3)

Definition at line 122 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_EEP_DELTA   10

Definition at line 206 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_EEP_FILE_VERSION (   _v)    (((_v) >> 8) & 0xff)

Definition at line 130 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_EEP_SCALE   100

Definition at line 205 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_FCC_MID_EN   (((_v) >> 6) & 0x1)

Definition at line 154 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_FF_DIS (   _v)    (((_v) >> 2) & 0x1)

Definition at line 145 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_FREQ_M (   _v)    AR5K_EEPROM_OFF(_v, 0x7f, 0xff)

Definition at line 219 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP1_OFFSET   0x0

Definition at line 166 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP2_OFFSET   0x5

Definition at line 167 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP3_OFFSET   0x37

Definition at line 168 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP4_OFFSET   0x46

Definition at line 169 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP5_OFFSET   0x55

Definition at line 170 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP6_OFFSET   0x65

Definition at line 171 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP7_OFFSET   0x69

Definition at line 172 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUP8_OFFSET   0x6f

Definition at line 173 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_GROUPS_START (   _v)    AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */

Definition at line 165 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HAS32KHZCRYSTAL (   _v)    (((_v) >> 14) & 0x1)

Definition at line 126 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD (   _v)    (((_v) >> 15) & 0x1)

Definition at line 127 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR   AR5K_EEPROM_INFO(2) /* Header that contains the device caps */

Definition at line 99 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_11A (   _v)    (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)

Definition at line 100 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_11B (   _v)    (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)

Definition at line 101 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_11G (   _v)    (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)

Definition at line 102 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_DEVICE (   _v)    (((_v) >> 11) & 0x7)

Definition at line 105 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_RFKILL (   _v)    (((_v) >> 14) & 0x1) /* Device has RFKill support */

Definition at line 106 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_T_2GHZ_DIS (   _v)    (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */

Definition at line 103 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_T_5GHZ_DBM (   _v)    (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */

Definition at line 104 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_T_5GHZ_DIS (   _v)    (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */

Definition at line 107 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_XR2_DIS (   _v)    (((_v) >> 12) & 0x1)

Definition at line 120 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HDR_XR5_DIS (   _v)    (((_v) >> 13) & 0x1)

Definition at line 121 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_HEAVY_CLIP_EN (   _v)    (((_v) >> 8) & 0x1)

Definition at line 148 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_I_GAIN   10

Definition at line 246 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_INFO (   _n)    (AR5K_EEPROM_INFO_BASE + (_n))

Definition at line 74 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_INFO_BASE   0x00c0 /* EEPROM header */

Definition at line 71 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_INFO_CKSUM   0xffff

Definition at line 73 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_INFO_MAX   (0x400 - AR5K_EEPROM_INFO_BASE)

Definition at line 72 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_IS_HB63   0x000b /* Talon detect */

Definition at line 61 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_JAP_11A_NEW_EN   (((_v) >> 10) & 0x1)

Definition at line 158 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_JAP_U1EVEN_EN   (((_v) >> 7) & 0x1)

Definition at line 155 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_JAP_U1ODD_EN   (((_v) >> 9) & 0x1)

Definition at line 157 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_JAP_U2_EN   (((_v) >> 8) & 0x1)

Definition at line 156 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_KEY_CACHE_SIZE (   _v)    (((_v) >> 12) & 0xf)

Definition at line 149 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAGIC   0x003d /* EEPROM Magic number */

Definition at line 55 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAGIC_5210   0x0000145a /* 5210 */

Definition at line 59 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAGIC_5211   0x0000145b /* 5211 */

Definition at line 58 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAGIC_5212   0x0000145c /* 5212 */

Definition at line 57 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAGIC_VALUE   0x5aa5 /* Default - found on EEPROM */

Definition at line 56 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MASK_R0 (   _v)    (((_v) >> 2) & 0x3)

Definition at line 139 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MASK_R1 (   _v)    ((_v) & 0x3)

Definition at line 140 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAX_CHAN   10

Definition at line 212 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAX_CTLS   32

Definition at line 231 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MAX_QCU (   _v)    (((_v) >> 4) & 0xf)

Definition at line 147 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MISC0   AR5K_EEPROM_INFO(4)

Definition at line 118 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MISC1   AR5K_EEPROM_INFO(5)

Definition at line 124 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MISC2   AR5K_EEPROM_INFO(6)

Definition at line 129 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MISC3   AR5K_EEPROM_INFO(7)

Definition at line 133 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MISC4   AR5K_EEPROM_INFO(8)

Definition at line 137 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MISC5   AR5K_EEPROM_INFO(9)

Definition at line 142 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MISC6   AR5K_EEPROM_INFO(10)

Definition at line 151 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MODE_11A   0

Definition at line 95 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MODE_11B   1

Definition at line 96 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MODE_11G   2

Definition at line 97 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MODES_11A (   _v)    AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)

Definition at line 161 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MODES_11B (   _v)    AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)

Definition at line 162 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_MODES_11G (   _v)    AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)

Definition at line 163 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_2GHZ_CHAN   3

Definition at line 209 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_2GHZ_CHAN_2413   4

Definition at line 210 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_2GHZ_CHAN_MAX   4

Definition at line 211 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_5GHZ_CHAN   10

Definition at line 208 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_CTLS (   _v)    AR5K_EEPROM_OFF(_v, 16, 32)

Definition at line 230 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_EDGES   8

Definition at line 217 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ   35

Definition at line 237 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ   55

Definition at line 238 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_INTERCEPTS   11

Definition at line 218 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_IQ_CAL   2

Definition at line 248 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_MODES   3

Definition at line 207 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_OBDB   4

Definition at line 226 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_PCDAC   11

Definition at line 214 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_PD_CURVES   4

Definition at line 232 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_PD_GAINS   4

Definition at line 235 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_PD_POINTS   5

Definition at line 236 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_PHASE_CAL   5

Definition at line 215 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_POWER_LOC_11B   4

Definition at line 244 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_POWER_LOC_11G   6

Definition at line 245 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_PWR_POINTS_5111   11

Definition at line 213 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_SPUR_CHANS   5

Definition at line 256 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_TEST_FREQ   8

Definition at line 216 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_XPD0_POINTS   4

Definition at line 233 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_N_XPD3_POINTS   3

Definition at line 234 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_NO_SPUR   0x8000

Definition at line 262 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_NON_EDGE_M   0x40

Definition at line 224 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_OBDB0_2GHZ   0x00ec

Definition at line 183 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_OBDB1_2GHZ   0x00ed

Definition at line 184 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_OBDB_DIS   0xffff

Definition at line 227 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_OFF (   _v,
  _v3_0,
  _v3_3 
)    (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)

Definition at line 110 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PCDAC_M   0x3f

Definition at line 220 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PCDAC_START   1

Definition at line 221 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PCDAC_STEP   1

Definition at line 223 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PCDAC_STOP   63

Definition at line 222 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PCIE_OFFSET   0x02 /* Contains offset to PCI-E infos */

Definition at line 53 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PCIE_SERDES_SECTION
Value:
0x40    /* PCIE_OFFSET points here when
                                                 * SERDES infos are present */

Definition at line 54 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_POWER_M   0x3f

Definition at line 239 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_POWER_MAX   3150

Definition at line 241 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_POWER_MIN   0

Definition at line 240 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_POWER_STEP   50

Definition at line 242 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_POWER_TABLE_SIZE   64

Definition at line 243 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT   0x003f /* EEPROM protect status */

Definition at line 186 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_0_31   0x0001 /* Read protection bit for offsets 0x0 - 0x1f */

Definition at line 187 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_128_191   0x0040 /* 0x80 - 0xbf (regdom) */

Definition at line 193 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_192_207   0x0100 /* 0xc0 - 0xcf */

Definition at line 195 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_208_223   0x0400 /* 0xd0 - 0xdf */

Definition at line 197 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_224_239   0x1000 /* 0xe0 - 0xef */

Definition at line 199 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_240_255   0x4000 /* 0xf0 - 0xff */

Definition at line 201 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_32_63   0x0004 /* 0x20 - 0x3f */

Definition at line 189 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_RD_64_127   0x0010 /* 0x40 - 0x7f */

Definition at line 191 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_0_31   0x0002 /* Write protection bit for offsets 0x0 - 0x1f */

Definition at line 188 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_128_191   0x0080

Definition at line 194 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_192_207   0x0200

Definition at line 196 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_208_223   0x0800

Definition at line 198 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_224_239   0x2000

Definition at line 200 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_240_255   0x8000

Definition at line 202 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_32_63   0x0008

Definition at line 190 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_PROTECT_WR_64_127   0x0020

Definition at line 192 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_READ (   _o,
  _v 
)
Value:
do {                    \
        ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
        if (ret)                                        \
                return ret;                             \
} while (0)

Definition at line 267 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_READ_HDR (   _o,
  _v 
)    AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \

Definition at line 273 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_REG_DOMAIN   0x00bf /* EEPROM regdom */

Definition at line 69 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_RFKILL   0x0f

Definition at line 63 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_RFKILL_GPIO_SEL   0x0000001c

Definition at line 64 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2

Definition at line 65 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_RFKILL_POLARITY   0x00000002

Definition at line 66 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_RFKILL_POLARITY_S   1

Definition at line 67 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_RX_CHAIN_DIS   (((_v) >> 3) & 0x8)

Definition at line 153 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_SCALE_OC_DELTA (   _x)    (((_x) * 2) / 10)

Definition at line 229 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_SPUR_CHAN_MASK   0x3FFF

Definition at line 261 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_TARGET_PWR_OFF_11A (   _v)
Value:
AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
                                                                AR5K_EEPROM_GROUP5_OFFSET, 0x0000)

Definition at line 175 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_TARGET_PWR_OFF_11B (   _v)
Value:
AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
                                                                AR5K_EEPROM_GROUP6_OFFSET, 0x0010)

Definition at line 177 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_TARGET_PWR_OFF_11G (   _v)
Value:
AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
                                                                AR5K_EEPROM_GROUP7_OFFSET, 0x0014)

Definition at line 179 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_TARGET_PWRSTART (   _v)    ((_v) & 0xfff)

Definition at line 125 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_TX_CHAIN_DIS   ((_v) & 0x8)

Definition at line 152 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION   AR5K_EEPROM_INFO(1) /* EEPROM Version */

Definition at line 76 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_3_0   0x3000 /* No idea what's going on before this version */

Definition at line 77 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_3_1   0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */

Definition at line 78 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_3_2   0x3002 /* different frequency representation (eeprom_bin2freq) */

Definition at line 79 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_3_3   0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */

Definition at line 80 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_3_4   0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */

Definition at line 81 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_0   0x4000 /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */

Definition at line 82 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_1   0x4001 /* has ee_margin_tx_rx (eeprom_init) */

Definition at line 83 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_2   0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */

Definition at line 84 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_3   0x4003 /* power calibration changes */

Definition at line 85 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_4   0x4004

Definition at line 86 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_5   0x4005

Definition at line 87 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_6   0x4006 /* has ee_scaled_cck_delta */

Definition at line 88 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_7   0x3007 /* 4007 ? */

Definition at line 89 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_4_9   0x4009 /* EAR futureproofing */

Definition at line 90 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_5_0   0x5000 /* Has 2413 PDADC calibration etc */

Definition at line 91 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_5_1   0x5001 /* Has capability values */

Definition at line 92 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_EEPROM_VERSION_5_3   0x5003 /* Has spur mitigation tables */

Definition at line 93 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_SPUR_CHAN_WIDTH   87

Definition at line 263 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz   3125

Definition at line 264 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

#define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz   6250

Definition at line 265 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

Enumeration Type Documentation

enum ath5k_ant_table
Enumerator:
AR5K_ANT_CTL 
AR5K_ANT_SWTABLE_A 
AR5K_ANT_SWTABLE_B 
AR5K_ANT_MAX 
AR5K_ANT_CTL 
AR5K_ANT_SWTABLE_A 
AR5K_ANT_SWTABLE_B 
AR5K_ANT_MAX 
AR5K_ANT_CTL 
AR5K_ANT_SWTABLE_A 
AR5K_ANT_SWTABLE_B 
AR5K_ANT_MAX 

Definition at line 276 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

enum ath5k_ctl_mode
Enumerator:
AR5K_CTL_11A 
AR5K_CTL_11B 
AR5K_CTL_11G 
AR5K_CTL_TURBO 
AR5K_CTL_TURBOG 
AR5K_CTL_2GHT20 
AR5K_CTL_5GHT20 
AR5K_CTL_2GHT40 
AR5K_CTL_5GHT40 
AR5K_CTL_MODE_M 
AR5K_CTL_11A 
AR5K_CTL_11B 
AR5K_CTL_11G 
AR5K_CTL_TURBO 
AR5K_CTL_TURBOG 
AR5K_CTL_2GHT20 
AR5K_CTL_5GHT20 
AR5K_CTL_2GHT40 
AR5K_CTL_5GHT40 
AR5K_CTL_MODE_M 
AR5K_CTL_11A 
AR5K_CTL_11B 
AR5K_CTL_11G 
AR5K_CTL_TURBO 
AR5K_CTL_TURBOG 
AR5K_CTL_2GHT20 
AR5K_CTL_5GHT20 
AR5K_CTL_2GHT40 
AR5K_CTL_5GHT40 
AR5K_CTL_MODE_M 

Definition at line 283 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

enum ath5k_eeprom_freq_bands
Enumerator:
AR5K_EEPROM_BAND_5GHZ 
AR5K_EEPROM_BAND_2GHZ 
AR5K_EEPROM_N_FREQ_BANDS 
AR5K_EEPROM_BAND_5GHZ 
AR5K_EEPROM_BAND_2GHZ 
AR5K_EEPROM_N_FREQ_BANDS 
AR5K_EEPROM_BAND_5GHZ 
AR5K_EEPROM_BAND_2GHZ 
AR5K_EEPROM_N_FREQ_BANDS 

Definition at line 250 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.

enum ath5k_powertable_type
Enumerator:
AR5K_PWRTABLE_PWR_TO_PCDAC 
AR5K_PWRTABLE_LINEAR_PCDAC 
AR5K_PWRTABLE_PWR_TO_PDADC 
AR5K_PWRTABLE_PWR_TO_PCDAC 
AR5K_PWRTABLE_LINEAR_PCDAC 
AR5K_PWRTABLE_PWR_TO_PDADC 
AR5K_PWRTABLE_PWR_TO_PCDAC 
AR5K_PWRTABLE_LINEAR_PCDAC 
AR5K_PWRTABLE_PWR_TO_PDADC 

Definition at line 357 of file MaRTE_OS/hwi/ath5k_raw/module/eeprom.h.


ros_rt_wmp
Author(s): Danilo Tardioli, dantard@unizar.es
autogenerated on Mon Oct 6 2014 08:27:12