00001 /* 00002 00003 Copyright (c) 2011, Ascending Technologies GmbH 00004 All rights reserved. 00005 00006 Redistribution and use in source and binary forms, with or without 00007 modification, are permitted provided that the following conditions are met: 00008 00009 * Redistributions of source code must retain the above copyright notice, 00010 this list of conditions and the following disclaimer. 00011 * Redistributions in binary form must reproduce the above copyright 00012 notice, this list of conditions and the following disclaimer in the 00013 documentation and/or other materials provided with the distribution. 00014 00015 THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 00016 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00017 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00018 DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY 00019 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00020 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00021 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00022 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00023 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00024 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 00025 DAMAGE. 00026 00027 */ 00028 00029 00030 #ifndef __SSP_H__ 00031 #define __SSP_H__ 00032 00033 volatile unsigned int SSP_trans_cnt; 00034 00035 /* SPI read and write buffer size */ 00036 #define FIFOSIZE 8 00037 00038 /* SPI Status register */ 00039 #define SSPSR_TFE 1 << 0 00040 #define SSPSR_TNF 1 << 1 00041 #define SSPSR_RNE 1 << 2 00042 #define SSPSR_RFF 1 << 3 00043 #define SSPSR_BSY 1 << 4 00044 00045 /* SPI 1 CR0 register */ 00046 #define SSPCR0_DSS 1 << 0 00047 #define SSPCR0_FRF 1 << 4 00048 #define SSPCR0_CPOL 1 << 6 00049 #define SSPCR0_CPHA 1 << 7 00050 #define SSPCR0_SCR 1 << 8 00051 00052 /* SPI 1 CR1 register */ 00053 #define SSPCR1_LBM 1 << 0 00054 #define SSPCR1_SSE 1 << 1 00055 #define SSPCR1_MS 1 << 2 00056 #define SSPCR1_SOD 1 << 3 00057 00058 /* SPI 1 Interrupt Mask Set/Clear register */ 00059 #define SSPIMSC_RORIM 1 << 0 00060 #define SSPIMSC_RTIM 1 << 1 00061 #define SSPIMSC_RXIM 1 << 2 00062 #define SSPIMSC_TXIM 1 << 3 00063 00064 /* SPI 1 Interrupt Status register */ 00065 #define SSPRIS_RORRIS 1 << 0 00066 #define SSPRIS_RTRIS 1 << 1 00067 #define SSPRIS_RXRIS 1 << 2 00068 #define SSPRIS_TXRIS 1 << 3 00069 00070 /* SPI 1 Masked Interrupt register */ 00071 #define SSPMIS_RORMIS 1 << 0 00072 #define SSPMIS_RTMIS 1 << 1 00073 #define SSPMIS_RXMIS 1 << 2 00074 #define SSPMIS_TXMIS 1 << 3 00075 00076 /* SPI 1 Interrupt clear register */ 00077 #define SSPICR_RORIC 1 << 0 00078 #define SSPICR_RTIC 1 << 1 00079 00080 extern void SSPHandler (void) __irq; 00081 int LL_write(unsigned char *, unsigned short, unsigned char); 00082 void LL_write_init(void); 00083 00084 extern unsigned char IMU_CalcData_updated; 00085 00086 #endif /* __SSP_H__ */ 00087 /***************************************************************************** 00088 ** End Of File 00089 ******************************************************************************/ 00090