Reset and Clock Control. More...
#include <stm32f407xx.h>
Public Attributes | |
| __IO uint32_t | AHB1ENR |
| __IO uint32_t | AHB1LPENR |
| __IO uint32_t | AHB1RSTR |
| __IO uint32_t | AHB2ENR |
| __IO uint32_t | AHB2LPENR |
| __IO uint32_t | AHB2RSTR |
| __IO uint32_t | AHB3ENR |
| __IO uint32_t | AHB3LPENR |
| __IO uint32_t | AHB3RSTR |
| __IO uint32_t | AHB4ENR |
| __IO uint32_t | AHB4LPENR |
| __IO uint32_t | AHB4RSTR |
| __IO uint32_t | APB1ENR |
| __IO uint32_t | APB1HENR |
| __IO uint32_t | APB1HLPENR |
| __IO uint32_t | APB1HRSTR |
| __IO uint32_t | APB1LENR |
| __IO uint32_t | APB1LLPENR |
| __IO uint32_t | APB1LPENR |
| __IO uint32_t | APB1LRSTR |
| __IO uint32_t | APB1RSTR |
| __IO uint32_t | APB2ENR |
| __IO uint32_t | APB2LPENR |
| __IO uint32_t | APB2RSTR |
| __IO uint32_t | APB3ENR |
| __IO uint32_t | APB3LPENR |
| __IO uint32_t | APB3RSTR |
| __IO uint32_t | APB4ENR |
| __IO uint32_t | APB4LPENR |
| __IO uint32_t | APB4RSTR |
| __IO uint32_t | BDCR |
| __IO uint32_t | CFGR |
| __IO uint32_t | CICR |
| __IO uint32_t | CIER |
| __IO uint32_t | CIFR |
| __IO uint32_t | CIR |
| __IO uint32_t | CR |
| __IO uint32_t | CRRCR |
| __IO uint32_t | CSICFGR |
| __IO uint32_t | CSR |
| __IO uint32_t | D1CCIPR |
| __IO uint32_t | D1CFGR |
| __IO uint32_t | D2CCIP1R |
| __IO uint32_t | D2CCIP2R |
| __IO uint32_t | D2CFGR |
| __IO uint32_t | D3AMR |
| __IO uint32_t | D3CCIPR |
| __IO uint32_t | D3CFGR |
| __IO uint32_t | DCKCFGR |
| __IO uint32_t | DCKCFGR1 |
| __IO uint32_t | DCKCFGR2 |
| __IO uint32_t | GCR |
| __IO uint32_t | HSICFGR |
| __IO uint32_t | PLL1DIVR |
| __IO uint32_t | PLL1FRACR |
| __IO uint32_t | PLL2DIVR |
| __IO uint32_t | PLL2FRACR |
| __IO uint32_t | PLL3DIVR |
| __IO uint32_t | PLL3FRACR |
| __IO uint32_t | PLLCFGR |
| __IO uint32_t | PLLCKSELR |
| __IO uint32_t | PLLI2SCFGR |
| __IO uint32_t | PLLSAICFGR |
| uint32_t | RESERVED0 |
| uint32_t | RESERVED1 [2] |
| uint32_t | RESERVED11 [9] |
| uint32_t | RESERVED12 |
| uint32_t | RESERVED13 [4] |
| uint32_t | RESERVED2 |
| uint32_t | RESERVED3 [2] |
| uint32_t | RESERVED4 |
| uint32_t | RESERVED5 [2] |
| uint32_t | RESERVED6 [2] |
| uint32_t | RESERVED7 [1] |
| uint32_t | RESERVED8 |
| __IO uint32_t | RSR |
| __IO uint32_t | SSCGR |
Reset and Clock Control.
Definition at line 597 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB1ENR |
RCC AHB1 peripheral clock register, Address offset: 0x30
RCC AHB1 peripheral clock register, Address offset: 0xD8
Definition at line 610 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB1LPENR |
RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50
RCC AHB1 peripheral sleep clock register, Address offset: 0x100
Definition at line 617 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB1RSTR |
RCC AHB1 peripheral reset register, Address offset: 0x10
RCC AHB1 peripheral reset register, Address offset: 0x80
Definition at line 603 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB2ENR |
RCC AHB2 peripheral clock register, Address offset: 0x34
RCC AHB2 peripheral clock register, Address offset: 0xDC
Definition at line 611 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB2LPENR |
RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54
RCC AHB2 peripheral sleep clock register, Address offset: 0x104
Definition at line 618 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB2RSTR |
RCC AHB2 peripheral reset register, Address offset: 0x14
RCC AHB2 peripheral reset register, Address offset: 0x84
Definition at line 604 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB3ENR |
RCC AHB3 peripheral clock register, Address offset: 0x38
RCC AHB3 peripheral clock register, Address offset: 0xD4
Definition at line 612 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB3LPENR |
RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58
RCC AHB3 peripheral sleep clock register, Address offset: 0xFC
Definition at line 619 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB3RSTR |
RCC AHB3 peripheral reset register, Address offset: 0x18
RCC AHB3 peripheral reset register, Address offset: 0x7C
Definition at line 605 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::AHB4ENR |
RCC AHB4 peripheral clock register, Address offset: 0xE0
Definition at line 1287 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::AHB4LPENR |
RCC AHB4 peripheral sleep clock register, Address offset: 0x108
Definition at line 1297 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::AHB4RSTR |
RCC AHB4 peripheral reset register, Address offset: 0x88
Definition at line 1273 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB1ENR |
RCC APB1 peripheral clock enable register, Address offset: 0x40
Definition at line 614 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::APB1HENR |
RCC APB1 peripheral clock High Word register, Address offset: 0xEC
Definition at line 1290 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB1HLPENR |
RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114
Definition at line 1300 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB1HRSTR |
RCC APB1 peripheral reset High Word register, Address offset: 0x94
Definition at line 1276 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB1LENR |
RCC APB1 peripheral clock Low Word register, Address offset: 0xE8
Definition at line 1289 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB1LLPENR |
RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110
Definition at line 1299 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB1LPENR |
RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60
Definition at line 621 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::APB1LRSTR |
RCC APB1 peripheral reset Low Word register, Address offset: 0x90
Definition at line 1275 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB1RSTR |
RCC APB1 peripheral reset register, Address offset: 0x20
Definition at line 607 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::APB2ENR |
RCC APB2 peripheral clock enable register, Address offset: 0x44
RCC APB2 peripheral clock register, Address offset: 0xF0
Definition at line 615 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::APB2LPENR |
RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64
RCC APB2 peripheral sleep clock register, Address offset: 0x118
Definition at line 622 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::APB2RSTR |
RCC APB2 peripheral reset register, Address offset: 0x24
RCC APB2 peripheral reset register, Address offset: 0x98
Definition at line 608 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::APB3ENR |
RCC APB3 peripheral clock register, Address offset: 0xE4
Definition at line 1288 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB3LPENR |
RCC APB3 peripheral sleep clock register, Address offset: 0x10C
Definition at line 1298 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB3RSTR |
RCC APB3 peripheral reset register, Address offset: 0x8C
Definition at line 1274 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB4ENR |
RCC APB4 peripheral clock register, Address offset: 0xF4
Definition at line 1292 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB4LPENR |
RCC APB4 peripheral sleep clock register, Address offset: 0x11C
Definition at line 1302 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::APB4RSTR |
RCC APB4 peripheral reset register, Address offset: 0x9C
Definition at line 1278 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::BDCR |
RCC Backup domain control register, Address offset: 0x70
RCC Vswitch Backup Domain Control Register, Address offset: 0x70
Definition at line 624 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::CFGR |
RCC clock configuration register, Address offset: 0x08
RCC clock configuration register, Address offset: 0x10
Definition at line 601 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::CICR |
RCC Clock Source Interrupt Clear Register Address offset: 0x68
Definition at line 1265 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::CIER |
RCC Clock Source Interrupt Enable Register Address offset: 0x60
Definition at line 1263 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::CIFR |
RCC Clock Source Interrupt Flag Register Address offset: 0x64
Definition at line 1264 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::CIR |
RCC clock interrupt register, Address offset: 0x0C
Definition at line 602 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::CR |
RCC clock control register, Address offset: 0x00
RCC clock control register, Address offset: 0x00
Definition at line 599 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::CRRCR |
Clock Recovery RC Register, Address offset: 0x08
Definition at line 1241 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::CSICFGR |
CSI Clock Calibration Register, Address offset: 0x0C
Definition at line 1242 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::CSR |
RCC clock control & status register, Address offset: 0x74
RCC clock control & status register, Address offset: 0x74
Definition at line 625 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::D1CCIPR |
RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C
Definition at line 1258 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::D1CFGR |
RCC Domain 1 configuration register, Address offset: 0x18
Definition at line 1245 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::D2CCIP1R |
RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50
Definition at line 1259 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::D2CCIP2R |
RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54
Definition at line 1260 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::D2CFGR |
RCC Domain 2 configuration register, Address offset: 0x1C
Definition at line 1246 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::D3AMR |
RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8
Definition at line 1281 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::D3CCIPR |
RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58
Definition at line 1261 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::D3CFGR |
RCC Domain 3 configuration register, Address offset: 0x20
Definition at line 1247 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::DCKCFGR |
RCC Dedicated Clocks configuration register, Address offset: 0x8C
Definition at line 370 of file stm32f411xe.h.
| __IO uint32_t RCC_TypeDef::DCKCFGR1 |
RCC Dedicated Clocks configuration register1, Address offset: 0x8C
Definition at line 783 of file stm32f769xx.h.
| __IO uint32_t RCC_TypeDef::DCKCFGR2 |
RCC Dedicated Clocks configuration register 2, Address offset: 0x90
Definition at line 784 of file stm32f769xx.h.
| __IO uint32_t RCC_TypeDef::GCR |
RCC RCC Global Control Register, Address offset: 0xA0
Definition at line 1279 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::HSICFGR |
HSI Clock Calibration Register, Address offset: 0x04
Definition at line 1240 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLL1DIVR |
RCC PLL1 Dividers Configuration Register, Address offset: 0x30
Definition at line 1251 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLL1FRACR |
RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34
Definition at line 1252 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLL2DIVR |
RCC PLL2 Dividers Configuration Register, Address offset: 0x38
Definition at line 1253 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLL2FRACR |
RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C
Definition at line 1254 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLL3DIVR |
RCC PLL3 Dividers Configuration Register, Address offset: 0x40
Definition at line 1255 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLL3FRACR |
RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44
Definition at line 1256 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLLCFGR |
RCC PLL configuration register, Address offset: 0x04
RCC PLLs Configuration Register, Address offset: 0x2C
Definition at line 600 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::PLLCKSELR |
RCC PLLs Clock Source Selection Register, Address offset: 0x28
Definition at line 1249 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::PLLI2SCFGR |
RCC PLLI2S configuration register, Address offset: 0x84
Definition at line 628 of file stm32f407xx.h.
| __IO uint32_t RCC_TypeDef::PLLSAICFGR |
RCC PLLSAI configuration register, Address offset: 0x88
Definition at line 787 of file stm32f469xx.h.
| uint32_t RCC_TypeDef::RESERVED0 |
Reserved, 0x1C
Definition at line 606 of file stm32f407xx.h.
| uint32_t RCC_TypeDef::RESERVED1 |
| uint32_t RCC_TypeDef::RESERVED11 |
Reserved, 0xAC-0xCC Address offset: 0xAC
Definition at line 1282 of file stm32h735xx.h.
| uint32_t RCC_TypeDef::RESERVED12 |
Reserved, Address offset: 0xF8
Definition at line 1293 of file stm32h735xx.h.
| uint32_t RCC_TypeDef::RESERVED13 |
Reserved, 0x120-0x12C Address offset: 0x120
Definition at line 1303 of file stm32h735xx.h.
| uint32_t RCC_TypeDef::RESERVED2 |
| uint32_t RCC_TypeDef::RESERVED3 |
| uint32_t RCC_TypeDef::RESERVED4 |
| uint32_t RCC_TypeDef::RESERVED5 |
| uint32_t RCC_TypeDef::RESERVED6 |
| uint32_t RCC_TypeDef::RESERVED7[1] |
Reserved, 0x88
Definition at line 369 of file stm32f411xe.h.
| uint32_t RCC_TypeDef::RESERVED8 |
Reserved, Address offset: 0xA4
Definition at line 1280 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::RSR |
RCC Reset status register, Address offset: 0xD0
Definition at line 1283 of file stm32h735xx.h.
| __IO uint32_t RCC_TypeDef::SSCGR |
RCC spread spectrum clock generation register, Address offset: 0x80
Definition at line 627 of file stm32f407xx.h.