Digital to Analog Converter. More...
#include <stm32f407xx.h>
Public Attributes | |
| __IO uint32_t | CCR |
| __IO uint32_t | CR |
| __IO uint32_t | DHR12L1 |
| __IO uint32_t | DHR12L2 |
| __IO uint32_t | DHR12LD |
| __IO uint32_t | DHR12R1 |
| __IO uint32_t | DHR12R2 |
| __IO uint32_t | DHR12RD |
| __IO uint32_t | DHR8R1 |
| __IO uint32_t | DHR8R2 |
| __IO uint32_t | DHR8RD |
| __IO uint32_t | DOR1 |
| __IO uint32_t | DOR2 |
| __IO uint32_t | MCR |
| __IO uint32_t | SHHR |
| __IO uint32_t | SHRR |
| __IO uint32_t | SHSR1 |
| __IO uint32_t | SHSR2 |
| __IO uint32_t | SR |
| __IO uint32_t | SWTRIGR |
Digital to Analog Converter.
Definition at line 293 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::CCR |
DAC calibration control register, Address offset: 0x38
Definition at line 489 of file stm32h735xx.h.
| __IO uint32_t DAC_TypeDef::CR |
DAC control register, Address offset: 0x00
Definition at line 295 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR12L1 |
DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C
Definition at line 298 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR12L2 |
DAC channel2 12-bit left aligned data holding register, Address offset: 0x18
Definition at line 301 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR12LD |
DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24
Definition at line 304 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR12R1 |
DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08
Definition at line 297 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR12R2 |
DAC channel2 12-bit right aligned data holding register, Address offset: 0x14
Definition at line 300 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR12RD |
Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20
Definition at line 303 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR8R1 |
DAC channel1 8-bit right aligned data holding register, Address offset: 0x10
Definition at line 299 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR8R2 |
DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C
Definition at line 302 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DHR8RD |
DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28
Definition at line 305 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DOR1 |
DAC channel1 data output register, Address offset: 0x2C
Definition at line 306 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::DOR2 |
DAC channel2 data output register, Address offset: 0x30
Definition at line 307 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::MCR |
DAC mode control register, Address offset: 0x3C
Definition at line 490 of file stm32h735xx.h.
| __IO uint32_t DAC_TypeDef::SHHR |
DAC Sample and Hold hold time register, Address offset: 0x48
Definition at line 493 of file stm32h735xx.h.
| __IO uint32_t DAC_TypeDef::SHRR |
DAC Sample and Hold refresh time register, Address offset: 0x4C
Definition at line 494 of file stm32h735xx.h.
| __IO uint32_t DAC_TypeDef::SHSR1 |
DAC Sample and Hold sample time register 1, Address offset: 0x40
Definition at line 491 of file stm32h735xx.h.
| __IO uint32_t DAC_TypeDef::SHSR2 |
DAC Sample and Hold sample time register 2, Address offset: 0x44
Definition at line 492 of file stm32h735xx.h.
| __IO uint32_t DAC_TypeDef::SR |
DAC status register, Address offset: 0x34
Definition at line 308 of file stm32f407xx.h.
| __IO uint32_t DAC_TypeDef::SWTRIGR |
DAC software trigger register, Address offset: 0x04
Definition at line 296 of file stm32f407xx.h.