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25 #include "stm32h7xx_hal.h"
36 #ifdef HAL_RCC_MODULE_ENABLED
43 #define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE
44 #define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE
46 #define DIVIDER_P_UPDATE 0U
47 #define DIVIDER_Q_UPDATE 1U
48 #define DIVIDER_R_UPDATE 2U
130 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_R_UPDATE);
136 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE);
177 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
183 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_P_UPDATE);
219 switch(PeriphClkInit->Sai23ClockSelection)
221 case RCC_SAI23CLKSOURCE_PLL:
228 case RCC_SAI23CLKSOURCE_PLL2:
230 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
235 case RCC_SAI23CLKSOURCE_PLL3:
236 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_P_UPDATE);
241 case RCC_SAI23CLKSOURCE_PIN:
246 case RCC_SAI23CLKSOURCE_CLKP:
259 __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
270 #if defined(RCC_CDCCIP1R_SAI2ASEL)
274 switch(PeriphClkInit->Sai2AClockSelection)
276 case RCC_SAI2ACLKSOURCE_PLL:
283 case RCC_SAI2ACLKSOURCE_PLL2:
285 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
290 case RCC_SAI2ACLKSOURCE_PLL3:
291 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_P_UPDATE);
296 case RCC_SAI2ACLKSOURCE_PIN:
301 case RCC_SAI2ACLKSOURCE_CLKP:
306 case RCC_SAI2ACLKSOURCE_SPDIF:
319 __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
329 #if defined(RCC_CDCCIP1R_SAI2BSEL)
334 switch(PeriphClkInit->Sai2BClockSelection)
336 case RCC_SAI2BCLKSOURCE_PLL:
343 case RCC_SAI2BCLKSOURCE_PLL2:
345 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
350 case RCC_SAI2BCLKSOURCE_PLL3:
351 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_P_UPDATE);
356 case RCC_SAI2BCLKSOURCE_PIN:
361 case RCC_SAI2BCLKSOURCE_CLKP:
366 case RCC_SAI2BCLKSOURCE_SPDIF:
379 __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
393 switch(PeriphClkInit->Sai4AClockSelection)
395 case RCC_SAI4ACLKSOURCE_PLL:
402 case RCC_SAI4ACLKSOURCE_PLL2:
404 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
409 case RCC_SAI4ACLKSOURCE_PLL3:
410 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_P_UPDATE);
415 case RCC_SAI4ACLKSOURCE_PIN:
420 case RCC_SAI4ACLKSOURCE_CLKP:
425 #if defined(RCC_VER_3_0)
426 case RCC_SAI4ACLKSOURCE_SPDIF:
440 __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
451 switch(PeriphClkInit->Sai4BClockSelection)
453 case RCC_SAI4BCLKSOURCE_PLL:
460 case RCC_SAI4BCLKSOURCE_PLL2:
462 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
467 case RCC_SAI4BCLKSOURCE_PLL3:
468 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3), DIVIDER_P_UPDATE);
473 case RCC_SAI4BCLKSOURCE_PIN:
478 case RCC_SAI4BCLKSOURCE_CLKP:
483 #if defined(RCC_VER_3_0)
484 case RCC_SAI4BCLKSOURCE_SPDIF:
498 __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
512 switch(PeriphClkInit->QspiClockSelection)
514 case RCC_QSPICLKSOURCE_PLL:
521 case RCC_QSPICLKSOURCE_PLL2:
523 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_R_UPDATE);
529 case RCC_QSPICLKSOURCE_CLKP:
534 case RCC_QSPICLKSOURCE_D1HCLK:
546 __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
556 #if defined(OCTOSPI1) || defined(OCTOSPI2)
560 switch(PeriphClkInit->OspiClockSelection)
562 case RCC_OSPICLKSOURCE_PLL:
569 case RCC_OSPICLKSOURCE_PLL2:
571 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_R_UPDATE);
577 case RCC_OSPICLKSOURCE_CLKP:
582 case RCC_OSPICLKSOURCE_HCLK:
594 __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
617 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
623 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_P_UPDATE);
666 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_Q_UPDATE);
671 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_Q_UPDATE);
718 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_Q_UPDATE);
723 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_Q_UPDATE);
741 #if defined(RCC_SPI6CLKSOURCE_PIN)
769 switch(PeriphClkInit->DsiClockSelection)
772 case RCC_DSICLKSOURCE_PLL2:
774 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_Q_UPDATE);
779 case RCC_DSICLKSOURCE_PHY:
792 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
802 #if defined(FDCAN1) || defined(FDCAN2)
806 switch(PeriphClkInit->FdcanClockSelection)
808 case RCC_FDCANCLKSOURCE_PLL:
815 case RCC_FDCANCLKSOURCE_PLL2:
817 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_Q_UPDATE);
822 case RCC_FDCANCLKSOURCE_HSE:
835 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
859 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_R_UPDATE);
971 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_Q_UPDATE);
976 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_Q_UPDATE);
1022 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_Q_UPDATE);
1027 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_Q_UPDATE);
1073 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_Q_UPDATE);
1078 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_Q_UPDATE);
1125 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
1131 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE);
1178 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
1184 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE);
1231 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
1237 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE);
1278 assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
1280 if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 )
1282 if(RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE)!=
HAL_OK)
1299 if(RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE)!=
HAL_OK)
1318 if(RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE)!=
HAL_OK)
1336 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_P_UPDATE);
1342 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE);
1384 ret = RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_Q_UPDATE);
1429 ret = RCCEx_PLL2_Config(&(PeriphClkInit->
PLL2),DIVIDER_R_UPDATE);
1455 if(RCCEx_PLL3_Config(&(PeriphClkInit->
PLL3),DIVIDER_R_UPDATE)!=
HAL_OK)
1521 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
1524 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
1537 #if defined(DFSDM2_BASE)
1542 assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
1545 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
1614 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1617 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1627 #if defined(DFSDM2_BASE)
1630 #if defined(QUADSPI)
1633 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1687 PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE();
1689 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
1691 PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE();
1693 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
1695 PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE();
1699 PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE();
1701 PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE();
1713 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
1721 #if defined(DFSDM2_BASE)
1723 PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
1734 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
1739 #if defined(QUADSPI)
1741 PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
1743 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1745 PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1750 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1795 uint32_t saiclocksource;
1796 uint32_t ckpclocksource;
1804 switch (saiclocksource)
1893 else if (PeriphClk == RCC_PERIPHCLK_SAI23)
1896 saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
1898 switch (saiclocksource)
1900 case RCC_SAI23CLKSOURCE_PLL:
1913 case RCC_SAI23CLKSOURCE_PLL2:
1927 case RCC_SAI23CLKSOURCE_PLL3:
1941 case RCC_SAI23CLKSOURCE_CLKP:
1973 case (RCC_SAI23CLKSOURCE_PIN):
1987 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1989 else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
1991 saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
1993 switch (saiclocksource)
1995 case RCC_SAI2ACLKSOURCE_PLL:
2008 case RCC_SAI2ACLKSOURCE_PLL2:
2022 case RCC_SAI2ACLKSOURCE_PLL3:
2036 case RCC_SAI2ACLKSOURCE_CLKP:
2068 case (RCC_SAI2ACLKSOURCE_PIN):
2084 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
2085 else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
2088 saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
2090 switch (saiclocksource)
2092 case RCC_SAI2BCLKSOURCE_PLL:
2105 case RCC_SAI2BCLKSOURCE_PLL2:
2119 case RCC_SAI2BCLKSOURCE_PLL3:
2133 case RCC_SAI2BCLKSOURCE_CLKP:
2164 case (RCC_SAI2BCLKSOURCE_PIN):
2180 else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
2183 saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
2185 switch (saiclocksource)
2187 case RCC_SAI4ACLKSOURCE_PLL:
2200 case RCC_SAI4ACLKSOURCE_PLL2:
2214 case RCC_SAI4ACLKSOURCE_PLL3:
2228 case RCC_SAI4ACLKSOURCE_CLKP:
2260 case RCC_SAI4ACLKSOURCE_PIN:
2274 else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
2277 saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
2279 switch (saiclocksource)
2281 case RCC_SAI4BCLKSOURCE_PLL:
2294 case RCC_SAI4BCLKSOURCE_PLL2:
2308 case RCC_SAI4BCLKSOURCE_PLL3:
2322 case RCC_SAI4BCLKSOURCE_CLKP:
2354 case RCC_SAI4BCLKSOURCE_PIN:
2648 #if defined(RCC_SPI6CLKSOURCE_PIN)
2665 srcclk= __HAL_RCC_GET_FDCAN_SOURCE();
2669 case RCC_FDCANCLKSOURCE_HSE:
2681 case RCC_FDCANCLKSOURCE_PLL:
2694 case RCC_FDCANCLKSOURCE_PLL2:
2731 #if defined(RCC_D1CFGR_D1PPRE)
2748 #if defined(RCC_D3CFGR_D3PPRE)
2772 uint32_t pllsource, pll2m, pll2fracen, hsivalue;
2773 float_t fracn2, pll2vco;
2793 pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(
RCC->PLL2DIVR &
RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2797 pll2vco = ((float_t)
HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(
RCC->PLL2DIVR &
RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2802 pll2vco = ((float_t)
CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(
RCC->PLL2DIVR &
RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2806 pll2vco = ((float_t)
HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(
RCC->PLL2DIVR &
RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2810 pll2vco = ((float_t)
CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(
RCC->PLL2DIVR &
RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
2841 uint32_t pllsource, pll3m, pll3fracen, hsivalue;
2842 float_t fracn3, pll3vco;
2861 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(
RCC->PLL3DIVR &
RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2865 pll3vco = ((float_t)
HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(
RCC->PLL3DIVR &
RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2869 pll3vco = ((float_t)
CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(
RCC->PLL3DIVR &
RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2873 pll3vco = ((float_t)
HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(
RCC->PLL3DIVR &
RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2877 pll3vco = ((float_t)
CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(
RCC->PLL3DIVR &
RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
2909 uint32_t pllsource, pll1m, pll1fracen, hsivalue;
2910 float_t fracn1, pll1vco;
2927 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(
RCC->PLL1DIVR &
RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2931 pll1vco = ((float_t)
HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(
RCC->PLL1DIVR &
RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2935 pll1vco = ((float_t)
CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(
RCC->PLL1DIVR &
RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2939 pll1vco = ((float_t)
HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(
RCC->PLL1DIVR &
RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2943 pll1vco = ((float_t)
HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(
RCC->PLL1DIVR &
RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
2970 uint32_t common_system_clock;
2972 #if defined(RCC_D1CFGR_D1CPRE)
2979 #if defined(RCC_D1CFGR_HPRE)
2985 #if defined(DUAL_CORE) && defined(CORE_CM4)
2991 return common_system_clock;
3039 #if defined(DUAL_CORE) && defined(CORE_CM4)
3040 __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
3079 #if defined(DUAL_CORE)
3090 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
3098 #if defined(DUAL_CORE)
3109 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3116 #if defined(RCC_GCR_WW1RSC)
3126 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3313 if(((
HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3549 if( (
HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
3578 if(Divider == DIVIDER_P_UPDATE)
3582 else if(Divider == DIVIDER_Q_UPDATE)
3600 if( (
HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
3652 if( (
HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
3681 if(Divider == DIVIDER_P_UPDATE)
3685 else if(Divider == DIVIDER_Q_UPDATE)
3703 if( (
HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
#define RCC_SPI123CLKSOURCE_PIN
#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__)
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define assert_param(expr)
Include module's header file.
#define RCC_SDMMCCLKSOURCE_PLL2
#define RCC_SPI123CLKSOURCE_PLL
void HAL_RCCEx_EnableLSECSS(void)
#define RCC_PLL3DIVR_R3_Pos
#define RCC_PERIPHCLK_SPI123
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
#define RCC_D1CFGR_HPRE_Pos
#define RCC_FMCCLKSOURCE_CLKP
#define IS_RCC_PLL2RGE_VALUE(VALUE)
#define __HAL_RCC_GET_LPTIM345_SOURCE()
macro to get the LPTIM3/4/5 clock source.
uint32_t HSI48CalibrationValue
HAL_StatusTypeDef
HAL Status structures definition
#define RCC_LPTIM345CLKSOURCE_PCLK4
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()
Enable the RCC LSE CSS Extended Interrupt Line.
#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__)
Macro to configure the CEC clock (CECCLK).
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__)
Macro to configure the ADC clock.
#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__)
macro to configure the RNG clock (RNGCLK).
#define RCC_D1CFGR_D1CPRE_Pos
#define RCC_PLLSOURCE_HSI
#define __HAL_RCC_PLL3FRACN_ENABLE()
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
#define RCC_SPI45CLKSOURCE_PLL2
#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__)
Macro to select the PLL3 reference frequency range.
#define __HAL_RCC_PLL2FRACN_ENABLE()
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)
Macro to configure SAI1 clock source selection.
#define __HAL_RCC_USB_CONFIG(__USBCLKSource__)
Macro to configure the USB clock (USBCLK).
#define RCC_LPTIM1CLKSOURCE_LSI
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
#define RCC_LPUART1CLKSOURCE_PCLK4
#define RCC_PERIPHCLK_RNG
uint32_t PLL3_Q_Frequency
#define RCC_PERIPHCLK_LPUART1
#define IS_RCC_SCOPE_WWDG(WWDG)
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
#define RCC_RTCCLKSOURCE_LSE
#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__)
Macro to configure the SWPMI1 clock.
#define RCC_PLLCKSELR_DIVM3
#define RCC_PERIPHCLK_SPI6
#define IS_RCC_PLL2R_VALUE(VALUE)
PLL3 Clock structure definition.
#define RCC_LPTIM345CLKSOURCE_LSI
uint32_t Spi123ClockSelection
#define RCC_PLL2FRACR_FRACN2
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__)
Macro to configure the I2C4 clock (I2C4CLK).
#define RCC_LPUART1CLKSOURCE_LSE
#define RCC_CRS_IT_SYNCWARN
#define RCC_LPTIM2CLKSOURCE_LSI
#define RCC_SPI123CLKSOURCE_CLKP
#define RCC_D1CFGR_D1PPRE
#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__)
macro to configure the USART234578 clock (USART234578CLK).
#define RCC_PERIPHCLK_DSI
#define RCC_SPDIFRXCLKSOURCE_PLL
#define RCC_PERIPHCLK_SPDIFRX
#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__)
Macro to Configure the SPI4/5 clock source.
RCC_CRS Init structure definition.
#define IS_RCC_TIMPRES(VALUE)
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__)
macro to configure the LPTIM2 clock source.
#define RCC_PLLSOURCE_NONE
#define __HAL_RCC_GET_RNG_SOURCE()
macro to get the RNG clock source.
#define __HAL_RCC_GET_SPI45_SOURCE()
Macro to get the SPI4/5 clock source.
#define RCC_PERIPHCLK_USART16
#define IS_RCC_PLL2P_VALUE(VALUE)
uint32_t Swpmi1ClockSelection
#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__)
Macro to configure the Kernel wake up from stop clock.
#define RCC_PERIPHCLK_DFSDM1
#define RCC_LPTIM345CLKSOURCE_PLL2
#define RCC_USART16CLKSOURCE_PLL2
uint32_t PeriphClockSelection
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
#define RCC_USBCLKSOURCE_PLL
#define IS_RCC_CECCLKSOURCE(SOURCE)
#define IS_RCC_PLL3P_VALUE(VALUE)
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
#define __HAL_RCC_GET_DFSDM1_SOURCE()
Macro to get the DFSDM1 clock source.
#define RCC_I2C4CLKSOURCE_PLL3
#define __HAL_RCC_GET_LPUART1_SOURCE()
macro to get the LPUART1 clock source.
uint32_t PLL2_P_Frequency
#define RCC_PLLCFGR_PLL2FRACEN
void HAL_RCCEx_CRS_SyncOkCallback(void)
#define IS_RCC_PLL2VCO_VALUE(VALUE)
#define RCC_LPTIM1CLKSOURCE_LSE
#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__)
Macro to Configure the SPDIFRX clock source.
#define RCC_SPI6CLKSOURCE_HSI
#define RCC_CRS_FLAG_ESYNC
#define RCC_ADCCLKSOURCE_PLL3
#define CLEAR_BIT(REG, BIT)
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
#define RCC_D3CFGR_D3PPRE_Pos
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
#define RCC_ADCCLKSOURCE_PLL2
#define RCC_PERIPHCLK_LPTIM2
uint32_t TIMPresSelection
uint32_t PLL1_Q_Frequency
#define RCC_PERIPHCLK_FMC
#define RCC_SPI123CLKSOURCE_PLL3
#define RCC_PLLCFGR_PLL1FRACEN
#define RCC_LPUART1CLKSOURCE_PLL2
#define RCC_CRS_FLAG_SYNCERR
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)
Check whether the specified CRS flag is set or not.
#define __HAL_RCC_GET_PLL_OSCSOURCE()
Macro to get the oscillator used as PLL clock source.
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__)
macro to configure the FMC clock source.
#define RCC_CLKPSOURCE_HSI
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__)
#define RCC_LPTIM345CLKSOURCE_CLKP
#define RCC_PLL3DIVR_N3_Pos
#define __HAL_RCC_GET_SPDIFRX_SOURCE()
Macro to get the SPDIFRX clock source.
uint32_t Lptim345ClockSelection
#define RCC_SPDIFRXCLKSOURCE_HSI
#define RCC_CRS_IT_SYNCOK
#define RCC_PLL3DIVR_Q3_Pos
#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__)
Macro to Configure the SPI1/2/3 clock source.
#define RCC_PERIPHCLK_SWPMI1
void HAL_RCCEx_CRS_SyncWarnCallback(void)
#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__)
Macro to select the PLL2 reference frequency range.
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
#define IS_RCC_CRS_RELOADVALUE(__VALUE__)
#define RCC_LPTIM1CLKSOURCE_PLL3
#define CRS_ISR_FECAP_Pos
#define RCC_SAI1CLKSOURCE_PLL2
#define RCC_LPTIM2CLKSOURCE_PLL3
uint32_t PLL1_R_Frequency
#define RCC_LPUART1CLKSOURCE_CSI
#define RCC_PERIPHCLK_I2C123
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
uint32_t Spi6ClockSelection
#define __HAL_RCC_GET_SAI1_SOURCE()
Macro to get the SAI1 clock source.
#define RCC_PERIPHCLK_FDCAN
#define RCC_PLLCFGR_PLL3VCOSEL_Pos
#define RCC_PLLCFGR_PLL3FRACEN
#define RCC_LPTIM2CLKSOURCE_CLKP
#define RCC_LPTIM345CLKSOURCE_LSE
#define IS_RCC_PLL2M_VALUE(VALUE)
#define RCC_PERIPHCLK_USART234578
#define RCC_PLLCFGR_PLL3RGE
#define __HAL_RCC_GET_RTC_SOURCE()
Macro to get the RTC clock source.
#define __HAL_RCC_GET_IT(__INTERRUPT__)
Check the RCC's interrupt has occurred or not.
#define RCC_PLLCKSELR_DIVM1
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
uint32_t PLL3_P_Frequency
uint32_t Usart234578ClockSelection
#define HSI_VALUE
Internal High Speed oscillator (HSI) value. This value is used by the RCC HAL module to compute the s...
#define CRS_ICR_SYNCWARNC
uint32_t SdmmcClockSelection
#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)
Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
#define RCC_LPUART1CLKSOURCE_PLL3
#define IS_RCC_SWPMI1CLKSOURCE(SOURCE)
#define RCC_PLL3DIVR_P3_Pos
uint32_t Lptim1ClockSelection
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
#define IS_RCC_PLL3VCO_VALUE(VALUE)
#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__)
Macro to select the PLL3 reference frequency range.
#define RCC_SPI45CLKSOURCE_PCLK1
#define RCC_USART16CLKSOURCE_PLL3
#define RCC_SPI45CLKSOURCE_PLL3
#define __HAL_RCC_GET_CEC_SOURCE()
macro to get the CEC clock source.
#define CSI_VALUE
Internal oscillator (CSI) default value. This value is the default CSI value after Reset.
#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__)
macro to configure the I2C1/2/3/5* clock (I2C123CLK).
uint32_t PLL2_R_Frequency
#define RCC_PLLCFGR_PLL2VCOSEL_Pos
uint32_t HAL_GetREVID(void)
Returns the device revision identifier.
#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
#define RCC_TIMPRES_ACTIVATED
#define RCC_PLL2DIVR_P2_Pos
#define RCC_LPTIM2CLKSOURCE_LSE
#define IS_RCC_CLKPSOURCE(SOURCE)
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__)
Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] bits to clear the selec...
#define RCC_SPDIFRXCLKSOURCE_PLL2
#define CRS_CFGR_FELIM_Pos
#define RCC_USART234578CLKSOURCE_PLL2
#define RCC_PLLCFGR_PLL2RGE
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
#define __HAL_RCC_BACKUPRESET_RELEASE()
uint32_t Dfsdm1ClockSelection
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__)
Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts).
#define __HAL_RCC_PLL3FRACN_DISABLE()
#define __HAL_RCC_GET_SPI123_SOURCE()
Macro to get the SPI1/2/3 clock source.
#define RCC_SAI1CLKSOURCE_CLKP
#define __HAL_RCC_GET_SDMMC_SOURCE()
Macro to get the SDMMC clock.
#define RCC_LPTIM2CLKSOURCE_PCLK4
#define RCC_SAI1CLKSOURCE_PLL3
#define RCC_SPI6CLKSOURCE_PCLK4
#define RCC_SPI6CLKSOURCE_PLL2
#define __HAL_RCC_CRS_RELEASE_RESET()
#define RCC_LPUART1CLKSOURCE_HSI
#define RCC_PLLCKSELR_DIVM2_Pos
#define RCC_USART16CLKSOURCE_HSI
#define EXTERNAL_CLOCK_VALUE
External clock source for I2S peripheral This value is used by the I2S HAL module to compute the I2S ...
uint32_t Lptim2ClockSelection
#define RCC_LPTIM2CLKSOURCE_PLL2
#define __HAL_RCC_GET_LPTIM2_SOURCE()
macro to get the LPTIM2 clock source.
#define RCC_SPI45CLKSOURCE_CSI
#define __HAL_RCC_USART16_CONFIG
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__)
Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts).
#define RCC_PLLSOURCE_CSI
#define RCC_TIMPRES_DESACTIVATED
#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
Macro to configures the PLL2 multiplication and division factors.
RCC PLL2 Clocks structure definition.
#define __HAL_RCC_PLL3_DISABLE()
#define __HAL_RCC_PLL3_ENABLE()
Macros to enable or disable the main PLL3.
#define IS_RCC_PLL3R_VALUE(VALUE)
#define __HAL_RCC_GET_CLKP_SOURCE()
Macro to get the Oscillator clock for peripheral source.
#define __HAL_RCC_GET_FMC_SOURCE()
macro to get the FMC clock source.
#define RCC_CRS_FLAG_SYNCMISS
uint32_t Usart16ClockSelection
#define __HAL_RCC_GET_I2C1_SOURCE()
Macro to get the I2C1 clock source.
#define RCC_CLKPSOURCE_HSE
#define RCC_RNGCLKSOURCE_HSI48
#define IS_RCC_I2C4CLKSOURCE(SOURCE)
#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__)
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
#define IS_RCC_PLL3M_VALUE(VALUE)
void HAL_RCCEx_EnableLSECSS_IT(void)
#define __HAL_RCC_GET_ADC_SOURCE()
Macro to get the ADC clock source.
#define READ_BIT(REG, BIT)
#define RCC_PERIPHCLK_I2C4
#define RCC_SPI45CLKSOURCE_HSI
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__)
macro to configure the LPUART1 clock (LPUART1CLK).
uint32_t SpdifrxClockSelection
#define RCC_PLLSOURCE_HSE
#define RCC_D1CFGR_D1CPRE
#define CRS_CR_AUTOTRIMEN
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define RCC_LPTIM345CLKSOURCE_PLL3
#define RCC_CRS_SYNC_SOURCE_PIN
#define RCC_CRS_FLAG_SYNCWARN
#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__)
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
uint32_t CkperClockSelection
#define RCC_PLLCFGR_PLL3RGE_Pos
#define __HAL_RCC_GET_USART16_SOURCE
uint32_t CecClockSelection
#define IS_RCC_PLL2Q_VALUE(VALUE)
#define RCC_LSE_TIMEOUT_VALUE
#define RCC_SPI6CLKSOURCE_PLL3
#define RCC_FMCCLKSOURCE_PLL2
uint32_t UsbClockSelection
uint32_t HAL_RCC_GetHCLKFreq(void)
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
#define RCC_USART234578CLKSOURCE_CSI
#define RCC_D3CFGR_D3PPRE
#define RCC_SPI6CLKSOURCE_PIN
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
#define IS_RCC_PLLFRACN_VALUE(VALUE)
#define RCC_RNGCLKSOURCE_LSI
#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__)
Macro to configure the CLKP : Oscillator clock for peripheral.
#define RCC_PLLCKSELR_DIVM2
#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__)
macro to configure the LPTIM3/4/5 clock source.
RCC PLL1 Clocks structure definition.
#define RCC_PERIPHCLK_CEC
uint32_t PLL2_Q_Frequency
#define RCC_USART16CLKSOURCE_PCLK2
#define RCC_PLLCKSELR_DIVM3_Pos
#define __HAL_RCC_GET_SPI6_SOURCE()
Macro to get the SPI6 clock source.
#define RCC_FMCCLKSOURCE_PLL
uint32_t Spi45ClockSelection
#define RCC_PLLCFGR_PLL3VCOSEL
#define RCC_PLLCFGR_PLL2VCOSEL
uint32_t I2c4ClockSelection
#define RCC_PLLCFGR_PLL2RGE_Pos
#define RCC_USART16CLKSOURCE_LSE
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define RCC_PERIPHCLK_USB
#define RCC_PERIPHCLK_SAI1
#define RCC_USART234578CLKSOURCE_PLL3
#define IS_RCC_PLL3Q_VALUE(VALUE)
#define RCC_PERIPHCLK_SDMMC
void HAL_RCCEx_LSECSS_Callback(void)
#define RCC_RNGCLKSOURCE_LSE
#define __HAL_RCC_PLL2_ENABLE()
Macros to enable or disable PLL2.
RCC PLL3 Clocks structure definition.
#define RCC_PERIPHCLK_LPTIM345
#define RCC_SPI45CLKSOURCE_HSE
#define RCC_USART234578CLKSOURCE_PCLK1
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
#define RCC_SPDIFRXCLKSOURCE_PLL3
#define __HAL_RCC_GET_FLAG(__FLAG__)
#define RCC_SAI1CLKSOURCE_PIN
#define RCC_PLLCKSELR_PLLSRC
#define RCC_PERIPHCLK_TIM
#define RCC_SDMMCCLKSOURCE_PLL
#define RCC_BDCR_LSECSSON
uint32_t HAL_RCC_GetSysClockFreq(void)
#define RCC_USART16CLKSOURCE_CSI
uint32_t Sai1ClockSelection
#define __HAL_RCC_GET_SWPMI1_SOURCE()
Macro to get the SWPMI1 clock source.
#define RCC_RNGCLKSOURCE_PLL
PLL2 Clock structure definition.
#define __HAL_RCC_PLL2FRACN_DISABLE()
uint32_t FmcClockSelection
uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
#define RCC_CRS_FLAG_TRIMOVF
#define RCC_FMCCLKSOURCE_HCLK
#define RCC_SPI123CLKSOURCE_PLL2
#define RCC_DBP_TIMEOUT_VALUE
#define __HAL_RCC_BACKUPRESET_FORCE()
Macros to force or release the Backup domain reset.
uint32_t Lpuart1ClockSelection
uint32_t PLL3_R_Frequency
void HAL_RCCEx_CRS_IRQHandler(void)
#define RCC_PERIPHCLK_LPTIM1
uint32_t I2c123ClockSelection
#define RCC_PERIPHCLK_RTC
#define HSE_VALUE
Adjust the value of External High Speed oscillator (HSE) used in your application....
#define RCC_CRS_SYNC_SOURCE_USB2
#define IS_RCC_I2C123CLKSOURCE(SOURCE)
#define HAL_IS_BIT_SET(REG, BIT)
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
#define WRITE_REG(REG, VAL)
uint32_t PLL1_P_Frequency
RCC extended clocks structure definition.
#define RCC_SAI1CLKSOURCE_PLL
#define RCC_LPTIM1CLKSOURCE_PCLK1
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
uint32_t AdcClockSelection
#define IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define __HAL_RCC_GET_LPTIM1_SOURCE()
macro to get the LPTIM1 clock source.
#define RCC_ADCCLKSOURCE_CLKP
#define RCC_USART234578CLKSOURCE_LSE
uint32_t RngClockSelection
#define RCC_LPTIM1CLKSOURCE_PLL2
#define RCC_PLL1FRACR_FRACN1
#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__)
Macro to configure the wake up from stop clock.
#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__)
Macro to configure the SDMMC clock.
#define RCC_SPI6CLKSOURCE_CSI
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
#define RCC_PLLCFGR_PLL2FRACEN_Pos
#define RCC_SPI6CLKSOURCE_D3PCLK1
#define SET_BIT(REG, BIT)
#define RCC_D1CFGR_D1PPRE_Pos
#define __HAL_RCC_GET_USART234578_SOURCE()
macro to get the USART2/3/4/5/7/8 clock source.
void HAL_RCCEx_LSECSS_IRQHandler(void)
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)
#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)
#define IS_RCC_PLL3N_VALUE(VALUE)
#define RCC_PERIPHCLK_ADC
#define __HAL_RCC_PLL2_DISABLE()
#define IS_RCC_PLL2N_VALUE(VALUE)
void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__)
Macro to configure the DFSDM1 clock.
#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__)
Macro to Configure the SPI6 clock source.
#define RCC_PLL3FRACR_FRACN3
void HAL_RCCEx_DisableLSECSS(void)
#define __HAL_RCC_GET_HSI_DIVIDER()
Macro to get the HSI divider.
#define RCC_USBCLKSOURCE_HSI48
#define RCC_PLL2DIVR_Q2_Pos
#define RCC_USART234578CLKSOURCE_HSI
#define RCC_PLLCFGR_PLL3FRACEN_Pos
#define __HAL_RCC_I2C123_CONFIG
#define IS_RCC_SDMMC(__SOURCE__)
#define RCC_PLL2DIVR_N2_Pos
#define RCC_PERIPHCLK_CKPER
#define RCC_SPI6CLKSOURCE_HSE
#define __HAL_RCC_GET_USB_SOURCE()
Macro to get the USB clock source.
#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)
#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__)
Macro to select the PLL2 reference frequency range.
#define RCC_LPTIM1CLKSOURCE_CLKP
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t RTCClockSelection
#define RCC_PERIPHCLK_SPI45
#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
Macro to configures the PLL3 multiplication and division factors.
#define RCC_CLKPSOURCE_CSI
#define RCC_USBCLKSOURCE_PLL3
const uint8_t D1CorePrescTable[16]
#define IS_RCC_CRS_SYNC_DIV(__DIV__)
#define RCC_PLL2DIVR_R2_Pos
#define __HAL_RCC_CRS_FORCE_RESET()
#define RCC_CRS_FLAG_SYNCOK
#define IS_RCC_PLL3RGE_VALUE(VALUE)