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21 #ifndef STM32H7xx_HAL_FLASH_EX_H
22 #define STM32H7xx_HAL_FLASH_EX_H
61 uint32_t VoltageRange;
114 #if defined(DUAL_CORE)
115 uint32_t CM4BootConfig;
119 uint32_t CM4BootAddr0;
122 uint32_t CM4BootAddr1;
136 #if defined (FLASH_OTPBL_LOCKBL)
137 uint32_t OTPBlockLock;
141 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
142 uint32_t SharedRamConfig;
146 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
147 uint32_t FreqBoostState;
193 #define FLASH_TYPEERASE_SECTORS 0x00U
194 #define FLASH_TYPEERASE_MASSERASE 0x01U
199 #if defined (FLASH_CR_PSIZE)
203 #define FLASH_VOLTAGE_RANGE_1 0x00000000U
204 #define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0
205 #define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1
206 #define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE
215 #define OB_WRPSTATE_DISABLE 0x00000000U
216 #define OB_WRPSTATE_ENABLE 0x00000001U
224 #define OPTIONBYTE_WRP 0x01U
225 #define OPTIONBYTE_RDP 0x02U
226 #define OPTIONBYTE_USER 0x04U
227 #define OPTIONBYTE_PCROP 0x08U
228 #define OPTIONBYTE_BOR 0x10U
229 #define OPTIONBYTE_SECURE_AREA 0x20U
230 #if defined (DUAL_CORE)
231 #define OPTIONBYTE_CM7_BOOTADD 0x40U
232 #define OPTIONBYTE_CM4_BOOTADD 0x80U
233 #define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD
235 #define OPTIONBYTE_BOOTADD 0x40U
237 #if defined (FLASH_OTPBL_LOCKBL)
238 #define OPTIONBYTE_OTP_LOCK 0x80U
240 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
241 #define OPTIONBYTE_SHARED_RAM 0x100U
243 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
244 #define OPTIONBYTE_FREQ_BOOST 0x200U
247 #if defined (DUAL_CORE)
248 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
249 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
250 OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD)
251 #elif defined (FLASH_OTPBL_LOCKBL)
252 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
253 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
254 OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK)
255 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
256 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
257 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
258 OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST)
260 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
261 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
271 #define OB_RDP_LEVEL_0 0xAA00U
272 #define OB_RDP_LEVEL_1 0x5500U
273 #define OB_RDP_LEVEL_2 0xCC00U
282 #define OB_IWDG_SW OB_IWDG1_SW
283 #define OB_IWDG_HW OB_IWDG1_HW
291 #define OB_STOP_NO_RST 0x40U
292 #define OB_STOP_RST 0x00U
300 #define OB_STDBY_NO_RST 0x80U
301 #define OB_STDBY_RST 0x00U
309 #define OB_IWDG_STOP_FREEZE 0x00000000U
310 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP
318 #define OB_IWDG_STDBY_FREEZE 0x00000000U
319 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY
327 #define OB_BOR_LEVEL0 0x00000000U
328 #define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0
329 #define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1
330 #define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0)
340 #define OB_BOOTADDR_ITCM_RAM 0x0000U
341 #define OB_BOOTADDR_SYSTEM 0x0040U
342 #define OB_BOOTADDR_ITCM_FLASH 0x0080U
343 #define OB_BOOTADDR_AXIM_FLASH 0x2000U
344 #define OB_BOOTADDR_DTCM_RAM 0x8000U
345 #define OB_BOOTADDR_SRAM1 0x8004U
346 #define OB_BOOTADDR_SRAM2 0x8013U
354 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
355 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
356 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
357 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
358 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
359 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
360 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
361 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
362 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
363 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
364 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
365 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
366 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
367 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
368 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
369 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
377 #define FLASH_BANK_1 0x01U
378 #if defined (DUAL_BANK)
379 #define FLASH_BANK_2 0x02U
380 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2)
389 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U
391 #define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP
401 #if (FLASH_SECTOR_TOTAL == 128)
402 #define OB_WRP_SECTOR_0TO3 0x00000001U
403 #define OB_WRP_SECTOR_4TO7 0x00000002U
404 #define OB_WRP_SECTOR_8TO11 0x00000004U
405 #define OB_WRP_SECTOR_12TO15 0x00000008U
406 #define OB_WRP_SECTOR_16TO19 0x00000010U
407 #define OB_WRP_SECTOR_20TO23 0x00000020U
408 #define OB_WRP_SECTOR_24TO27 0x00000040U
409 #define OB_WRP_SECTOR_28TO31 0x00000080U
410 #define OB_WRP_SECTOR_32TO35 0x00000100U
411 #define OB_WRP_SECTOR_36TO39 0x00000200U
412 #define OB_WRP_SECTOR_40TO43 0x00000400U
413 #define OB_WRP_SECTOR_44TO47 0x00000800U
414 #define OB_WRP_SECTOR_48TO51 0x00001000U
415 #define OB_WRP_SECTOR_52TO55 0x00002000U
416 #define OB_WRP_SECTOR_56TO59 0x00004000U
417 #define OB_WRP_SECTOR_60TO63 0x00008000U
418 #define OB_WRP_SECTOR_64TO67 0x00010000U
419 #define OB_WRP_SECTOR_68TO71 0x00020000U
420 #define OB_WRP_SECTOR_72TO75 0x00040000U
421 #define OB_WRP_SECTOR_76TO79 0x00080000U
422 #define OB_WRP_SECTOR_80TO83 0x00100000U
423 #define OB_WRP_SECTOR_84TO87 0x00200000U
424 #define OB_WRP_SECTOR_88TO91 0x00400000U
425 #define OB_WRP_SECTOR_92TO95 0x00800000U
426 #define OB_WRP_SECTOR_96TO99 0x01000000U
427 #define OB_WRP_SECTOR_100TO103 0x02000000U
428 #define OB_WRP_SECTOR_104TO107 0x04000000U
429 #define OB_WRP_SECTOR_108TO111 0x08000000U
430 #define OB_WRP_SECTOR_112TO115 0x10000000U
431 #define OB_WRP_SECTOR_116TO119 0x20000000U
432 #define OB_WRP_SECTOR_120TO123 0x40000000U
433 #define OB_WRP_SECTOR_124TO127 0x80000000U
434 #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU
436 #define OB_WRP_SECTOR_0 0x00000001U
437 #define OB_WRP_SECTOR_1 0x00000002U
438 #define OB_WRP_SECTOR_2 0x00000004U
439 #define OB_WRP_SECTOR_3 0x00000008U
440 #define OB_WRP_SECTOR_4 0x00000010U
441 #define OB_WRP_SECTOR_5 0x00000020U
442 #define OB_WRP_SECTOR_6 0x00000040U
443 #define OB_WRP_SECTOR_7 0x00000080U
444 #define OB_WRP_SECTOR_ALL 0x000000FFU
453 #define OB_SECURITY_DISABLE 0x00000000U
454 #define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY
462 #define OB_ST_RAM_SIZE_2KB 0x00000000U
463 #define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0
464 #define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1
465 #define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE
470 #if defined(DUAL_CORE)
474 #define OB_BCM7_DISABLE 0x00000000U
475 #define OB_BCM7_ENABLE FLASH_OPTSR_BCM7
484 #define OB_BCM4_DISABLE 0x00000000U
485 #define OB_BCM4_ENABLE FLASH_OPTSR_BCM4
494 #define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW
495 #define OB_IWDG1_HW 0x00000000U
500 #if defined(DUAL_CORE)
504 #define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW
505 #define OB_IWDG2_HW 0x00000000U
514 #define OB_STOP_RST_D1 0x00000000U
515 #define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1
523 #define OB_STDBY_RST_D1 0x00000000U
524 #define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1
529 #if defined (FLASH_OPTSR_NRST_STOP_D2)
533 #define OB_STOP_RST_D2 0x00000000U
534 #define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2
542 #define OB_STDBY_RST_D2 0x00000000U
543 #define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2
549 #if defined (DUAL_BANK)
553 #define OB_SWAP_BANK_DISABLE 0x00000000U
554 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT
563 #define OB_IOHSLV_DISABLE 0x00000000U
564 #define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV
569 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
573 #define OB_VDDMMC_HSLV_DISABLE 0x00000000U
574 #define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV
580 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
584 #define OB_CPUFREQ_BOOST_DISABLE 0x00000000U
585 #define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST
591 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
595 #define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U
596 #define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0
597 #define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1
598 #define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED
607 #define OB_USER_IWDG1_SW 0x0001U
608 #define OB_USER_NRST_STOP_D1 0x0002U
609 #define OB_USER_NRST_STDBY_D1 0x0004U
610 #define OB_USER_IWDG_STOP 0x0008U
611 #define OB_USER_IWDG_STDBY 0x0010U
612 #define OB_USER_ST_RAM_SIZE 0x0020U
613 #define OB_USER_SECURITY 0x0040U
614 #define OB_USER_IOHSLV 0x0080U
615 #if defined (DUAL_BANK)
616 #define OB_USER_SWAP_BANK 0x0100U
618 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
619 #define OB_USER_VDDMMC_HSLV 0x0200U
621 #if defined (DUAL_CORE)
622 #define OB_USER_IWDG2_SW 0x0200U
623 #define OB_USER_BCM4 0x0400U
624 #define OB_USER_BCM7 0x0800U
626 #if defined (FLASH_OPTSR_NRST_STOP_D2)
627 #define OB_USER_NRST_STOP_D2 0x1000U
628 #define OB_USER_NRST_STDBY_D2 0x2000U
631 #if defined (DUAL_CORE)
632 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
633 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
634 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
635 OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
636 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
637 #elif defined (FLASH_OPTSR_VDDMMC_HSLV)
638 #if defined (DUAL_BANK)
639 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
640 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
641 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
644 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
645 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
646 OB_USER_SECURITY | OB_USER_IOHSLV |\
649 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
650 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
651 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
652 OB_USER_SECURITY | OB_USER_IOHSLV |\
653 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
655 #if defined (DUAL_BANK)
656 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
657 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
658 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
660 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
661 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
662 OB_USER_SECURITY | OB_USER_IOHSLV )
672 #define OB_BOOT_ADD0 0x01U
673 #define OB_BOOT_ADD1 0x02U
674 #define OB_BOOT_ADD_BOTH 0x03U
682 #define OB_SECURE_RDP_NOT_ERASE 0x00000000U
684 #define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES
693 #define FLASH_CRC_ADDR 0x00000000U
694 #define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT
695 #define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT)
703 #define FLASH_CRC_BURST_SIZE_4 0x00000000U
704 #define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0
705 #define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1
706 #define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST
714 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U
715 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0
716 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1
717 #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ
722 #if defined (FLASH_OTPBL_LOCKBL)
726 #define FLASH_OTP_BLOCK_0 0x00000001U
727 #define FLASH_OTP_BLOCK_1 0x00000002U
728 #define FLASH_OTP_BLOCK_2 0x00000004U
729 #define FLASH_OTP_BLOCK_3 0x00000008U
730 #define FLASH_OTP_BLOCK_4 0x00000010U
731 #define FLASH_OTP_BLOCK_5 0x00000020U
732 #define FLASH_OTP_BLOCK_6 0x00000040U
733 #define FLASH_OTP_BLOCK_7 0x00000080U
734 #define FLASH_OTP_BLOCK_8 0x00000100U
735 #define FLASH_OTP_BLOCK_9 0x00000200U
736 #define FLASH_OTP_BLOCK_10 0x00000400U
737 #define FLASH_OTP_BLOCK_11 0x00000800U
738 #define FLASH_OTP_BLOCK_12 0x00001000U
739 #define FLASH_OTP_BLOCK_13 0x00002000U
740 #define FLASH_OTP_BLOCK_14 0x00004000U
741 #define FLASH_OTP_BLOCK_15 0x00008000U
742 #define FLASH_OTP_BLOCK_ALL 0x0000FFFFU
758 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
763 #if defined (FLASH_CR_PSIZE)
771 #if defined (DUAL_BANK)
772 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
773 MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
774 MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
776 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__))
785 #if defined (DUAL_BANK)
786 #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
787 READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
788 READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
790 #define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)
801 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
808 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
826 #if defined (DUAL_BANK)
852 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
853 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
855 #if defined (FLASH_CR_PSIZE)
856 #define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
857 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
858 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
859 ((RANGE) == FLASH_VOLTAGE_RANGE_4))
862 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
863 ((VALUE) == OB_WRPSTATE_ENABLE))
865 #define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
866 (((VALUE) & ~OPTIONBYTE_ALL) == 0U))
868 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
870 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
871 ((LEVEL) == OB_RDP_LEVEL_1) ||\
872 ((LEVEL) == OB_RDP_LEVEL_2))
874 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
876 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
878 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
880 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
882 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
884 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
885 ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
887 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
888 ((LATENCY) == FLASH_LATENCY_1) || \
889 ((LATENCY) == FLASH_LATENCY_2) || \
890 ((LATENCY) == FLASH_LATENCY_3) || \
891 ((LATENCY) == FLASH_LATENCY_4) || \
892 ((LATENCY) == FLASH_LATENCY_5) || \
893 ((LATENCY) == FLASH_LATENCY_6) || \
894 ((LATENCY) == FLASH_LATENCY_7) || \
895 ((LATENCY) == FLASH_LATENCY_8) || \
896 ((LATENCY) == FLASH_LATENCY_9) || \
897 ((LATENCY) == FLASH_LATENCY_10) || \
898 ((LATENCY) == FLASH_LATENCY_11) || \
899 ((LATENCY) == FLASH_LATENCY_12) || \
900 ((LATENCY) == FLASH_LATENCY_13) || \
901 ((LATENCY) == FLASH_LATENCY_14) || \
902 ((LATENCY) == FLASH_LATENCY_15))
904 #define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
906 #if (FLASH_SECTOR_TOTAL == 8U)
907 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
909 #define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
912 #define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
913 ((CONFIG) == OB_PCROP_RDP_ERASE))
915 #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
916 ((CONFIG) == OB_SECURE_RDP_ERASE))
918 #if defined (DUAL_BANK)
919 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
922 #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
924 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
925 #define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
928 #define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
929 #if defined (DUAL_CORE)
930 #define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
932 #define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
934 #define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
936 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
938 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
940 #define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
941 ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
943 #define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
945 #if defined (DUAL_CORE)
946 #define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
948 #define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
951 #if defined (FLASH_OPTSR_NRST_STOP_D2)
952 #define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
954 #define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
957 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
958 #define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \
959 ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB))
962 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
963 #define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE))
966 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
967 (((TYPE) & ~OB_USER_ALL) == 0U))
969 #define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
970 ((VALUE) == OB_BOOT_ADD1) || \
971 ((VALUE) == OB_BOOT_ADD_BOTH))
973 #define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
974 ((VALUE) == FLASH_CRC_SECTORS) || \
975 ((VALUE) == FLASH_CRC_BANK))
977 #if defined (FLASH_OTPBL_LOCKBL)
978 #define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
uint32_t SecureAreaConfig
HAL_StatusTypeDef
HAL Status structures definition
uint32_t SecureAreaEndAddr
This file contains HAL common defines, enumeration, macros and structures definitions.
FLASH Erase structure definition.
FLASH Option Bytes Program structure definition.
uint32_t SecureAreaStartAddr
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
FLASH Erase structure definition.