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25 #if defined ( __ICCARM__ )
26 #pragma system_include
27 #elif defined (__clang__)
28 #pragma clang system_header
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
66 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
69 __CM4_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (4U)
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
100 #elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
109 #define __FPU_USED 0U
112 #elif defined ( __ICCARM__ )
113 #if defined __ARMVFP__
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
121 #define __FPU_USED 0U
124 #elif defined ( __TI_ARM__ )
125 #if defined __TI_VFP_SUPPORT__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
133 #define __FPU_USED 0U
136 #elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
145 #define __FPU_USED 0U
148 #elif defined ( __CSMC__ )
149 #if ( __CSMC__ & 0x400U)
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
157 #define __FPU_USED 0U
171 #ifndef __CMSIS_GENERIC
173 #ifndef __CORE_CM4_H_DEPENDANT
174 #define __CORE_CM4_H_DEPENDANT
181 #if defined __CHECK_DEVICE_DEFINES
183 #define __CM4_REV 0x0000U
184 #warning "__CM4_REV not defined in device header file; using default!"
187 #ifndef __FPU_PRESENT
188 #define __FPU_PRESENT 0U
189 #warning "__FPU_PRESENT not defined in device header file; using default!"
192 #ifndef __MPU_PRESENT
193 #define __MPU_PRESENT 0U
194 #warning "__MPU_PRESENT not defined in device header file; using default!"
197 #ifndef __NVIC_PRIO_BITS
198 #define __NVIC_PRIO_BITS 3U
199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
202 #ifndef __Vendor_SysTickConfig
203 #define __Vendor_SysTickConfig 0U
204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
219 #define __I volatile const
222 #define __IO volatile
225 #define __IM volatile const
226 #define __OM volatile
227 #define __IOM volatile
276 #define APSR_N_Pos 31U
277 #define APSR_N_Msk (1UL << APSR_N_Pos)
279 #define APSR_Z_Pos 30U
280 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
282 #define APSR_C_Pos 29U
283 #define APSR_C_Msk (1UL << APSR_C_Pos)
285 #define APSR_V_Pos 28U
286 #define APSR_V_Msk (1UL << APSR_V_Pos)
288 #define APSR_Q_Pos 27U
289 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
291 #define APSR_GE_Pos 16U
292 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
309 #define IPSR_ISR_Pos 0U
310 #define IPSR_ISR_Msk (0x1FFUL )
337 #define xPSR_N_Pos 31U
338 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
340 #define xPSR_Z_Pos 30U
341 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
343 #define xPSR_C_Pos 29U
344 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
346 #define xPSR_V_Pos 28U
347 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
349 #define xPSR_Q_Pos 27U
350 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
352 #define xPSR_ICI_IT_2_Pos 25U
353 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
355 #define xPSR_T_Pos 24U
356 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
358 #define xPSR_GE_Pos 16U
359 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
361 #define xPSR_ICI_IT_1_Pos 10U
362 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
364 #define xPSR_ISR_Pos 0U
365 #define xPSR_ISR_Msk (0x1FFUL )
384 #define CONTROL_FPCA_Pos 2U
385 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
387 #define CONTROL_SPSEL_Pos 1U
388 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
390 #define CONTROL_nPRIV_Pos 0U
391 #define CONTROL_nPRIV_Msk (1UL )
408 __IOM uint32_t ISER[8U];
409 uint32_t RESERVED0[24U];
410 __IOM uint32_t ICER[8U];
411 uint32_t RESERVED1[24U];
412 __IOM uint32_t ISPR[8U];
413 uint32_t RESERVED2[24U];
414 __IOM uint32_t ICPR[8U];
415 uint32_t RESERVED3[24U];
416 __IOM uint32_t IABR[8U];
417 uint32_t RESERVED4[56U];
418 __IOM uint8_t IP[240U];
419 uint32_t RESERVED5[644U];
424 #define NVIC_STIR_INTID_Pos 0U
425 #define NVIC_STIR_INTID_Msk (0x1FFUL )
445 __IOM uint32_t AIRCR;
448 __IOM uint8_t SHP[12U];
449 __IOM uint32_t SHCSR;
453 __IOM uint32_t MMFAR;
456 __IM uint32_t PFR[2U];
459 __IM uint32_t MMFR[4U];
460 __IM uint32_t ISAR[5U];
461 uint32_t RESERVED0[5U];
462 __IOM uint32_t CPACR;
466 #define SCB_CPUID_IMPLEMENTER_Pos 24U
467 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
469 #define SCB_CPUID_VARIANT_Pos 20U
470 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
472 #define SCB_CPUID_ARCHITECTURE_Pos 16U
473 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
475 #define SCB_CPUID_PARTNO_Pos 4U
476 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
478 #define SCB_CPUID_REVISION_Pos 0U
479 #define SCB_CPUID_REVISION_Msk (0xFUL )
482 #define SCB_ICSR_NMIPENDSET_Pos 31U
483 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
485 #define SCB_ICSR_PENDSVSET_Pos 28U
486 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
488 #define SCB_ICSR_PENDSVCLR_Pos 27U
489 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
491 #define SCB_ICSR_PENDSTSET_Pos 26U
492 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
494 #define SCB_ICSR_PENDSTCLR_Pos 25U
495 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
497 #define SCB_ICSR_ISRPREEMPT_Pos 23U
498 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
500 #define SCB_ICSR_ISRPENDING_Pos 22U
501 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
503 #define SCB_ICSR_VECTPENDING_Pos 12U
504 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
506 #define SCB_ICSR_RETTOBASE_Pos 11U
507 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
509 #define SCB_ICSR_VECTACTIVE_Pos 0U
510 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
513 #define SCB_VTOR_TBLOFF_Pos 7U
514 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
517 #define SCB_AIRCR_VECTKEY_Pos 16U
518 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
520 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
521 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
523 #define SCB_AIRCR_ENDIANESS_Pos 15U
524 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
526 #define SCB_AIRCR_PRIGROUP_Pos 8U
527 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
529 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
530 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
532 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
533 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
535 #define SCB_AIRCR_VECTRESET_Pos 0U
536 #define SCB_AIRCR_VECTRESET_Msk (1UL )
539 #define SCB_SCR_SEVONPEND_Pos 4U
540 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
542 #define SCB_SCR_SLEEPDEEP_Pos 2U
543 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
545 #define SCB_SCR_SLEEPONEXIT_Pos 1U
546 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
549 #define SCB_CCR_STKALIGN_Pos 9U
550 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
552 #define SCB_CCR_BFHFNMIGN_Pos 8U
553 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
555 #define SCB_CCR_DIV_0_TRP_Pos 4U
556 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
558 #define SCB_CCR_UNALIGN_TRP_Pos 3U
559 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
561 #define SCB_CCR_USERSETMPEND_Pos 1U
562 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
564 #define SCB_CCR_NONBASETHRDENA_Pos 0U
565 #define SCB_CCR_NONBASETHRDENA_Msk (1UL )
568 #define SCB_SHCSR_USGFAULTENA_Pos 18U
569 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
571 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
572 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
574 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
575 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
577 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
578 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
580 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
581 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
583 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
584 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
586 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
587 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
589 #define SCB_SHCSR_SYSTICKACT_Pos 11U
590 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
592 #define SCB_SHCSR_PENDSVACT_Pos 10U
593 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
595 #define SCB_SHCSR_MONITORACT_Pos 8U
596 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
598 #define SCB_SHCSR_SVCALLACT_Pos 7U
599 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
601 #define SCB_SHCSR_USGFAULTACT_Pos 3U
602 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
604 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
605 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
607 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
608 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL )
611 #define SCB_CFSR_USGFAULTSR_Pos 16U
612 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
614 #define SCB_CFSR_BUSFAULTSR_Pos 8U
615 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
617 #define SCB_CFSR_MEMFAULTSR_Pos 0U
618 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL )
621 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
622 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
624 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
625 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
627 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
628 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
630 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
631 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
633 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
634 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
636 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
637 #define SCB_CFSR_IACCVIOL_Msk (1UL )
640 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
641 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
643 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
644 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
646 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
647 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
649 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
650 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
652 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
653 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
655 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
656 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
658 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
659 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
662 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
663 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
665 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
666 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
668 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
669 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
671 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
672 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
674 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
675 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
677 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
678 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
681 #define SCB_HFSR_DEBUGEVT_Pos 31U
682 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
684 #define SCB_HFSR_FORCED_Pos 30U
685 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
687 #define SCB_HFSR_VECTTBL_Pos 1U
688 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
691 #define SCB_DFSR_EXTERNAL_Pos 4U
692 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
694 #define SCB_DFSR_VCATCH_Pos 3U
695 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
697 #define SCB_DFSR_DWTTRAP_Pos 2U
698 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
700 #define SCB_DFSR_BKPT_Pos 1U
701 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
703 #define SCB_DFSR_HALTED_Pos 0U
704 #define SCB_DFSR_HALTED_Msk (1UL )
721 uint32_t RESERVED0[1U];
723 __IOM uint32_t ACTLR;
727 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
728 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )
731 #define SCnSCB_ACTLR_DISOOFP_Pos 9U
732 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
734 #define SCnSCB_ACTLR_DISFPCA_Pos 8U
735 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
737 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
738 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
740 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
741 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
743 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
744 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL )
768 #define SysTick_CTRL_COUNTFLAG_Pos 16U
769 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
771 #define SysTick_CTRL_CLKSOURCE_Pos 2U
772 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
774 #define SysTick_CTRL_TICKINT_Pos 1U
775 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
777 #define SysTick_CTRL_ENABLE_Pos 0U
778 #define SysTick_CTRL_ENABLE_Msk (1UL )
781 #define SysTick_LOAD_RELOAD_Pos 0U
782 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
785 #define SysTick_VAL_CURRENT_Pos 0U
786 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
789 #define SysTick_CALIB_NOREF_Pos 31U
790 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
792 #define SysTick_CALIB_SKEW_Pos 30U
793 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
795 #define SysTick_CALIB_TENMS_Pos 0U
796 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
819 uint32_t RESERVED0[864U];
821 uint32_t RESERVED1[15U];
823 uint32_t RESERVED2[15U];
825 uint32_t RESERVED3[32U];
826 uint32_t RESERVED4[43U];
829 uint32_t RESERVED5[6U];
845 #define ITM_TPR_PRIVMASK_Pos 0U
846 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL )
849 #define ITM_TCR_BUSY_Pos 23U
850 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
852 #define ITM_TCR_TraceBusID_Pos 16U
853 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
855 #define ITM_TCR_GTSFREQ_Pos 10U
856 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
858 #define ITM_TCR_TSPrescale_Pos 8U
859 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
861 #define ITM_TCR_SWOENA_Pos 4U
862 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
864 #define ITM_TCR_DWTENA_Pos 3U
865 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
867 #define ITM_TCR_SYNCENA_Pos 2U
868 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
870 #define ITM_TCR_TSENA_Pos 1U
871 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
873 #define ITM_TCR_ITMENA_Pos 0U
874 #define ITM_TCR_ITMENA_Msk (1UL )
877 #define ITM_LSR_ByteAcc_Pos 2U
878 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
880 #define ITM_LSR_Access_Pos 1U
881 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
883 #define ITM_LSR_Present_Pos 0U
884 #define ITM_LSR_Present_Msk (1UL )
902 __IOM uint32_t CYCCNT;
903 __IOM uint32_t CPICNT;
904 __IOM uint32_t EXCCNT;
905 __IOM uint32_t SLEEPCNT;
906 __IOM uint32_t LSUCNT;
907 __IOM uint32_t FOLDCNT;
909 __IOM uint32_t COMP0;
910 __IOM uint32_t MASK0;
911 __IOM uint32_t FUNCTION0;
912 uint32_t RESERVED0[1U];
914 __IOM uint32_t MASK1;
915 __IOM uint32_t FUNCTION1;
916 uint32_t RESERVED1[1U];
918 __IOM uint32_t MASK2;
919 __IOM uint32_t FUNCTION2;
920 uint32_t RESERVED2[1U];
921 __IOM uint32_t COMP3;
922 __IOM uint32_t MASK3;
923 __IOM uint32_t FUNCTION3;
927 #define DWT_CTRL_NUMCOMP_Pos 28U
928 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
930 #define DWT_CTRL_NOTRCPKT_Pos 27U
931 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
933 #define DWT_CTRL_NOEXTTRIG_Pos 26U
934 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
936 #define DWT_CTRL_NOCYCCNT_Pos 25U
937 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
939 #define DWT_CTRL_NOPRFCNT_Pos 24U
940 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
942 #define DWT_CTRL_CYCEVTENA_Pos 22U
943 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
945 #define DWT_CTRL_FOLDEVTENA_Pos 21U
946 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
948 #define DWT_CTRL_LSUEVTENA_Pos 20U
949 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
951 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
952 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
954 #define DWT_CTRL_EXCEVTENA_Pos 18U
955 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
957 #define DWT_CTRL_CPIEVTENA_Pos 17U
958 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
960 #define DWT_CTRL_EXCTRCENA_Pos 16U
961 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
963 #define DWT_CTRL_PCSAMPLENA_Pos 12U
964 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
966 #define DWT_CTRL_SYNCTAP_Pos 10U
967 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
969 #define DWT_CTRL_CYCTAP_Pos 9U
970 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
972 #define DWT_CTRL_POSTINIT_Pos 5U
973 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
975 #define DWT_CTRL_POSTPRESET_Pos 1U
976 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
978 #define DWT_CTRL_CYCCNTENA_Pos 0U
979 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL )
982 #define DWT_CPICNT_CPICNT_Pos 0U
983 #define DWT_CPICNT_CPICNT_Msk (0xFFUL )
986 #define DWT_EXCCNT_EXCCNT_Pos 0U
987 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL )
990 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
991 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL )
994 #define DWT_LSUCNT_LSUCNT_Pos 0U
995 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL )
998 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
999 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL )
1002 #define DWT_MASK_MASK_Pos 0U
1003 #define DWT_MASK_MASK_Msk (0x1FUL )
1006 #define DWT_FUNCTION_MATCHED_Pos 24U
1007 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1009 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
1010 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1012 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
1013 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1015 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1016 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1018 #define DWT_FUNCTION_LNK1ENA_Pos 9U
1019 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1021 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
1022 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1024 #define DWT_FUNCTION_CYCMATCH_Pos 7U
1025 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1027 #define DWT_FUNCTION_EMITRANGE_Pos 5U
1028 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1030 #define DWT_FUNCTION_FUNCTION_Pos 0U
1031 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL )
1048 __IM uint32_t SSPSR;
1049 __IOM uint32_t CSPSR;
1050 uint32_t RESERVED0[2U];
1051 __IOM uint32_t ACPR;
1052 uint32_t RESERVED1[55U];
1053 __IOM uint32_t SPPR;
1054 uint32_t RESERVED2[131U];
1056 __IOM uint32_t FFCR;
1058 uint32_t RESERVED3[759U];
1059 __IM uint32_t TRIGGER;
1060 __IM uint32_t FIFO0;
1061 __IM uint32_t ITATBCTR2;
1062 uint32_t RESERVED4[1U];
1063 __IM uint32_t ITATBCTR0;
1064 __IM uint32_t FIFO1;
1065 __IOM uint32_t ITCTRL;
1066 uint32_t RESERVED5[39U];
1067 __IOM uint32_t CLAIMSET;
1068 __IOM uint32_t CLAIMCLR;
1069 uint32_t RESERVED7[8U];
1070 __IM uint32_t DEVID;
1071 __IM uint32_t DEVTYPE;
1075 #define TPI_ACPR_PRESCALER_Pos 0U
1076 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL )
1079 #define TPI_SPPR_TXMODE_Pos 0U
1080 #define TPI_SPPR_TXMODE_Msk (0x3UL )
1083 #define TPI_FFSR_FtNonStop_Pos 3U
1084 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1086 #define TPI_FFSR_TCPresent_Pos 2U
1087 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1089 #define TPI_FFSR_FtStopped_Pos 1U
1090 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1092 #define TPI_FFSR_FlInProg_Pos 0U
1093 #define TPI_FFSR_FlInProg_Msk (0x1UL )
1096 #define TPI_FFCR_TrigIn_Pos 8U
1097 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1099 #define TPI_FFCR_EnFCont_Pos 1U
1100 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1103 #define TPI_TRIGGER_TRIGGER_Pos 0U
1104 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL )
1107 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1108 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
1110 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1111 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1113 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1114 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
1116 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1117 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1119 #define TPI_FIFO0_ETM2_Pos 16U
1120 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1122 #define TPI_FIFO0_ETM1_Pos 8U
1123 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1125 #define TPI_FIFO0_ETM0_Pos 0U
1126 #define TPI_FIFO0_ETM0_Msk (0xFFUL )
1129 #define TPI_ITATBCTR2_ATREADY2_Pos 0U
1130 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL )
1132 #define TPI_ITATBCTR2_ATREADY1_Pos 0U
1133 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL )
1136 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1137 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
1139 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1140 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1142 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1143 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
1145 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1146 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1148 #define TPI_FIFO1_ITM2_Pos 16U
1149 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1151 #define TPI_FIFO1_ITM1_Pos 8U
1152 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1154 #define TPI_FIFO1_ITM0_Pos 0U
1155 #define TPI_FIFO1_ITM0_Msk (0xFFUL )
1158 #define TPI_ITATBCTR0_ATREADY2_Pos 0U
1159 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL )
1161 #define TPI_ITATBCTR0_ATREADY1_Pos 0U
1162 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL )
1165 #define TPI_ITCTRL_Mode_Pos 0U
1166 #define TPI_ITCTRL_Mode_Msk (0x3UL )
1169 #define TPI_DEVID_NRZVALID_Pos 11U
1170 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1172 #define TPI_DEVID_MANCVALID_Pos 10U
1173 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1175 #define TPI_DEVID_PTINVALID_Pos 9U
1176 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1178 #define TPI_DEVID_MinBufSz_Pos 6U
1179 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1181 #define TPI_DEVID_AsynClkIn_Pos 5U
1182 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1184 #define TPI_DEVID_NrTraceInput_Pos 0U
1185 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL )
1188 #define TPI_DEVTYPE_SubType_Pos 4U
1189 #define TPI_DEVTYPE_SubType_Msk (0xFUL )
1191 #define TPI_DEVTYPE_MajorType_Pos 0U
1192 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1197 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1211 __IOM uint32_t CTRL;
1213 __IOM uint32_t RBAR;
1214 __IOM uint32_t RASR;
1215 __IOM uint32_t RBAR_A1;
1216 __IOM uint32_t RASR_A1;
1217 __IOM uint32_t RBAR_A2;
1218 __IOM uint32_t RASR_A2;
1219 __IOM uint32_t RBAR_A3;
1220 __IOM uint32_t RASR_A3;
1223 #define MPU_TYPE_RALIASES 4U
1226 #define MPU_TYPE_IREGION_Pos 16U
1227 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1229 #define MPU_TYPE_DREGION_Pos 8U
1230 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1232 #define MPU_TYPE_SEPARATE_Pos 0U
1233 #define MPU_TYPE_SEPARATE_Msk (1UL )
1236 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1237 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1239 #define MPU_CTRL_HFNMIENA_Pos 1U
1240 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1242 #define MPU_CTRL_ENABLE_Pos 0U
1243 #define MPU_CTRL_ENABLE_Msk (1UL )
1246 #define MPU_RNR_REGION_Pos 0U
1247 #define MPU_RNR_REGION_Msk (0xFFUL )
1250 #define MPU_RBAR_ADDR_Pos 5U
1251 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1253 #define MPU_RBAR_VALID_Pos 4U
1254 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1256 #define MPU_RBAR_REGION_Pos 0U
1257 #define MPU_RBAR_REGION_Msk (0xFUL )
1260 #define MPU_RASR_ATTRS_Pos 16U
1261 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1263 #define MPU_RASR_XN_Pos 28U
1264 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1266 #define MPU_RASR_AP_Pos 24U
1267 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1269 #define MPU_RASR_TEX_Pos 19U
1270 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1272 #define MPU_RASR_S_Pos 18U
1273 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1275 #define MPU_RASR_C_Pos 17U
1276 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1278 #define MPU_RASR_B_Pos 16U
1279 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1281 #define MPU_RASR_SRD_Pos 8U
1282 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1284 #define MPU_RASR_SIZE_Pos 1U
1285 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1287 #define MPU_RASR_ENABLE_Pos 0U
1288 #define MPU_RASR_ENABLE_Msk (1UL )
1306 uint32_t RESERVED0[1U];
1307 __IOM uint32_t FPCCR;
1308 __IOM uint32_t FPCAR;
1309 __IOM uint32_t FPDSCR;
1310 __IM uint32_t MVFR0;
1311 __IM uint32_t MVFR1;
1312 __IM uint32_t MVFR2;
1316 #define FPU_FPCCR_ASPEN_Pos 31U
1317 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1319 #define FPU_FPCCR_LSPEN_Pos 30U
1320 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1322 #define FPU_FPCCR_MONRDY_Pos 8U
1323 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1325 #define FPU_FPCCR_BFRDY_Pos 6U
1326 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1328 #define FPU_FPCCR_MMRDY_Pos 5U
1329 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1331 #define FPU_FPCCR_HFRDY_Pos 4U
1332 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1334 #define FPU_FPCCR_THREAD_Pos 3U
1335 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1337 #define FPU_FPCCR_USER_Pos 1U
1338 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1340 #define FPU_FPCCR_LSPACT_Pos 0U
1341 #define FPU_FPCCR_LSPACT_Msk (1UL )
1344 #define FPU_FPCAR_ADDRESS_Pos 3U
1345 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1348 #define FPU_FPDSCR_AHP_Pos 26U
1349 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1351 #define FPU_FPDSCR_DN_Pos 25U
1352 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1354 #define FPU_FPDSCR_FZ_Pos 24U
1355 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1357 #define FPU_FPDSCR_RMode_Pos 22U
1358 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1361 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1362 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1364 #define FPU_MVFR0_Short_vectors_Pos 24U
1365 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1367 #define FPU_MVFR0_Square_root_Pos 20U
1368 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1370 #define FPU_MVFR0_Divide_Pos 16U
1371 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1373 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1374 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1376 #define FPU_MVFR0_Double_precision_Pos 8U
1377 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1379 #define FPU_MVFR0_Single_precision_Pos 4U
1380 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1382 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1383 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL )
1386 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1387 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1389 #define FPU_MVFR1_FP_HPFP_Pos 24U
1390 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1392 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1393 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1395 #define FPU_MVFR1_FtZ_mode_Pos 0U
1396 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL )
1400 #define FPU_MVFR2_VFP_Misc_Pos 4U
1401 #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)
1418 __IOM uint32_t DHCSR;
1419 __OM uint32_t DCRSR;
1420 __IOM uint32_t DCRDR;
1421 __IOM uint32_t DEMCR;
1425 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1426 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1428 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1429 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1431 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1432 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1434 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1435 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1437 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1438 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1440 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1441 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1443 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1444 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1446 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1447 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1449 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1450 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1452 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1453 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1455 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1456 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1458 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1459 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
1462 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1463 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1465 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1466 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
1469 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1470 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1472 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1473 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1475 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1476 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1478 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1479 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1481 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1482 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1484 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1485 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1487 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1488 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1490 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1491 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1493 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1494 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1496 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1497 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1499 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1500 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1502 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1503 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1505 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1506 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
1524 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1532 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1545 #define SCS_BASE (0xE000E000UL)
1546 #define ITM_BASE (0xE0000000UL)
1547 #define DWT_BASE (0xE0001000UL)
1548 #define TPI_BASE (0xE0040000UL)
1549 #define CoreDebug_BASE (0xE000EDF0UL)
1550 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1551 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1552 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1554 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1555 #define SCB ((SCB_Type *) SCB_BASE )
1556 #define SysTick ((SysTick_Type *) SysTick_BASE )
1557 #define NVIC ((NVIC_Type *) NVIC_BASE )
1558 #define ITM ((ITM_Type *) ITM_BASE )
1559 #define DWT ((DWT_Type *) DWT_BASE )
1560 #define TPI ((TPI_Type *) TPI_BASE )
1561 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1563 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1564 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1565 #define MPU ((MPU_Type *) MPU_BASE )
1568 #define FPU_BASE (SCS_BASE + 0x0F30UL)
1569 #define FPU ((FPU_Type *) FPU_BASE )
1597 #ifdef CMSIS_NVIC_VIRTUAL
1598 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1599 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1601 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1603 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1604 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1605 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1606 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1607 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1608 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1609 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1610 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1611 #define NVIC_GetActive __NVIC_GetActive
1612 #define NVIC_SetPriority __NVIC_SetPriority
1613 #define NVIC_GetPriority __NVIC_GetPriority
1614 #define NVIC_SystemReset __NVIC_SystemReset
1617 #ifdef CMSIS_VECTAB_VIRTUAL
1618 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1619 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1621 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1623 #define NVIC_SetVector __NVIC_SetVector
1624 #define NVIC_GetVector __NVIC_GetVector
1627 #define NVIC_USER_IRQ_OFFSET 16
1631 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL)
1632 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
1633 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
1634 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL)
1635 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL)
1636 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL)
1651 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1653 reg_value =
SCB->AIRCR;
1655 reg_value = (reg_value |
1658 SCB->AIRCR = reg_value;
1681 if ((int32_t)(
IRQn) >= 0)
1684 NVIC->ISER[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1700 if ((int32_t)(
IRQn) >= 0)
1702 return((uint32_t)(((
NVIC->ISER[(((uint32_t)
IRQn) >> 5UL)] & (1UL << (((uint32_t)
IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1719 if ((int32_t)(
IRQn) >= 0)
1721 NVIC->ICER[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1738 if ((int32_t)(
IRQn) >= 0)
1740 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)
IRQn) >> 5UL)] & (1UL << (((uint32_t)
IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1757 if ((int32_t)(
IRQn) >= 0)
1759 NVIC->ISPR[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1772 if ((int32_t)(
IRQn) >= 0)
1774 NVIC->ICPR[(((uint32_t)
IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)
IRQn) & 0x1FUL));
1789 if ((int32_t)(
IRQn) >= 0)
1791 return((uint32_t)(((
NVIC->IABR[(((uint32_t)
IRQn) >> 5UL)] & (1UL << (((uint32_t)
IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1811 if ((int32_t)(
IRQn) >= 0)
1817 SCB->SHP[(((uint32_t)
IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1834 if ((int32_t)(
IRQn) >= 0)
1858 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1859 uint32_t PreemptPriorityBits;
1860 uint32_t SubPriorityBits;
1863 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1866 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1867 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1885 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1886 uint32_t PreemptPriorityBits;
1887 uint32_t SubPriorityBits;
1890 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1892 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1893 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1908 uint32_t vectors = (uint32_t )
SCB->VTOR;
1924 uint32_t vectors = (uint32_t )
SCB->VTOR;
1953 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1955 #include "mpu_armv7.h"
2004 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2024 SysTick->LOAD = (uint32_t)(ticks - 1UL);
2048 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2059 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2062 ((
ITM->TER & 1UL ) != 0UL) )
2064 while (
ITM->PORT[0U].u32 == 0UL)
2068 ITM->PORT[0U].u8 = (uint8_t)ch;
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
#define SysTick_CTRL_CLKSOURCE_Msk
Union type to access the Special-Purpose Program Status Registers (xPSR).
#define SCB_AIRCR_SYSRESETREQ_Msk
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
#define FPU_MVFR0_Double_precision_Msk
Union type to access the Application Program Status Register (APSR).
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
#define __NOP
No Operation.
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Structure type to access the System Control Block (SCB).
#define ITM_TCR_ITMENA_Msk
#define SysTick_CTRL_TICKINT_Msk
Structure type to access the Data Watchpoint and Trace Register (DWT).
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
volatile int32_t ITM_RxBuffer
CMSIS Core(M) Version definitions.
#define SysTick_LOAD_RELOAD_Msk
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Union type to access the Control Registers (CONTROL).
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
#define SCB_AIRCR_VECTKEY_Pos
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
#define ITM_RXBUFFER_EMPTY
Structure type to access the Core Debug Register (CoreDebug).
#define SCB_AIRCR_PRIGROUP_Pos
Structure type to access the Floating Point Unit (FPU).
Structure type to access the Trace Port Interface Register (TPI).
#define SysTick_CTRL_ENABLE_Msk
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
#define NVIC_USER_IRQ_OFFSET
Structure type to access the System Control and ID Register not in the SCB.
#define SCB_AIRCR_PRIGROUP_Msk
CMSIS compiler generic header file.
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Structure type to access the System Timer (SysTick).
Union type to access the Interrupt Program Status Register (IPSR).
#define __COMPILER_BARRIER()
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
#define FPU_MVFR0_Single_precision_Msk
#define SCB_AIRCR_VECTKEY_Msk