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Iomuxc_driver

Files

file  fsl_iomuxc.h
 

Macros

#define FSL_COMPONENT_ID   "platform.drivers.iomuxc"
 

Driver version

#define FSL_IOMUXC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))
 IOMUXC driver version 2.0.1. More...
 

Pin function ID

The pin function ID is a tuple of <muxRegister muxMode inputRegister inputDaisy configRegister>

enum  _iomuxc_gpr_mode {
  kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK,
  kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
  kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK
}
 
enum  _iomuxc_gpr_saimclk {
  kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
  kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT
}
 
enum  _iomuxc_mqs_pwm_oversample_rate { kIOMUXC_MqsPwmOverSampleRate32 = 0, kIOMUXC_MqsPwmOverSampleRate64 = 1 }
 
typedef enum _iomuxc_gpr_mode iomuxc_gpr_mode_t
 
typedef enum _iomuxc_gpr_saimclk iomuxc_gpr_saimclk_t
 
typedef enum _iomuxc_mqs_pwm_oversample_rate iomuxc_mqs_pwm_oversample_rate_t
 
#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00   0x400A8000U, 0x5U, 0, 0, 0x400A8018U
 
#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI   0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U
 
#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ   0x400A8004U, 0x0U, 0, 0, 0x400A801CU
 
#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01   0x400A8004U, 0x5U, 0, 0, 0x400A801CU
 
#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ   0x400A8008U, 0x0U, 0, 0, 0x400A8020U
 
#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02   0x400A8008U, 0x5U, 0, 0, 0x400A8020U
 
#define IOMUXC_SNVS_TEST_MODE   0, 0, 0, 0, 0x400A800CU
 
#define IOMUXC_SNVS_POR_B   0, 0, 0, 0, 0x400A8010U
 
#define IOMUXC_SNVS_ONOFF   0, 0, 0, 0, 0x400A8014U
 
#define IOMUXC_GPIO_EMC_00_SEMC_DATA00   0x401F8014U, 0x0U, 0, 0, 0x401F8204U
 
#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00   0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U
 
#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK   0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U
 
#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02   0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U
 
#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00   0x401F8014U, 0x4U, 0, 0, 0x401F8204U
 
#define IOMUXC_GPIO_EMC_00_GPIO4_IO00   0x401F8014U, 0x5U, 0, 0, 0x401F8204U
 
#define IOMUXC_GPIO_EMC_01_SEMC_DATA01   0x401F8018U, 0x0U, 0, 0, 0x401F8208U
 
#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00   0x401F8018U, 0x1U, 0, 0, 0x401F8208U
 
#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0   0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U
 
#define IOMUXC_GPIO_EMC_01_XBAR1_IN03   0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U
 
#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01   0x401F8018U, 0x4U, 0, 0, 0x401F8208U
 
#define IOMUXC_GPIO_EMC_01_GPIO4_IO01   0x401F8018U, 0x5U, 0, 0, 0x401F8208U
 
#define IOMUXC_GPIO_EMC_02_SEMC_DATA02   0x401F801CU, 0x0U, 0, 0, 0x401F820CU
 
#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01   0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU
 
#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO   0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU
 
#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04   0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU
 
#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02   0x401F801CU, 0x4U, 0, 0, 0x401F820CU
 
#define IOMUXC_GPIO_EMC_02_GPIO4_IO02   0x401F801CU, 0x5U, 0, 0, 0x401F820CU
 
#define IOMUXC_GPIO_EMC_03_SEMC_DATA03   0x401F8020U, 0x0U, 0, 0, 0x401F8210U
 
#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01   0x401F8020U, 0x1U, 0, 0, 0x401F8210U
 
#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI   0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U
 
#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05   0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U
 
#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03   0x401F8020U, 0x4U, 0, 0, 0x401F8210U
 
#define IOMUXC_GPIO_EMC_03_GPIO4_IO03   0x401F8020U, 0x5U, 0, 0, 0x401F8210U
 
#define IOMUXC_GPIO_EMC_04_SEMC_DATA04   0x401F8024U, 0x0U, 0, 0, 0x401F8214U
 
#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02   0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U
 
#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA   0x401F8024U, 0x2U, 0, 0, 0x401F8214U
 
#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06   0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U
 
#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04   0x401F8024U, 0x4U, 0, 0, 0x401F8214U
 
#define IOMUXC_GPIO_EMC_04_GPIO4_IO04   0x401F8024U, 0x5U, 0, 0, 0x401F8214U
 
#define IOMUXC_GPIO_EMC_05_SEMC_DATA05   0x401F8028U, 0x0U, 0, 0, 0x401F8218U
 
#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02   0x401F8028U, 0x1U, 0, 0, 0x401F8218U
 
#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC   0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U
 
#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07   0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U
 
#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05   0x401F8028U, 0x4U, 0, 0, 0x401F8218U
 
#define IOMUXC_GPIO_EMC_05_GPIO4_IO05   0x401F8028U, 0x5U, 0, 0, 0x401F8218U
 
#define IOMUXC_GPIO_EMC_06_SEMC_DATA06   0x401F802CU, 0x0U, 0, 0, 0x401F821CU
 
#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00   0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU
 
#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK   0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU
 
#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08   0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU
 
#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06   0x401F802CU, 0x4U, 0, 0, 0x401F821CU
 
#define IOMUXC_GPIO_EMC_06_GPIO4_IO06   0x401F802CU, 0x5U, 0, 0, 0x401F821CU
 
#define IOMUXC_GPIO_EMC_07_SEMC_DATA07   0x401F8030U, 0x0U, 0, 0, 0x401F8220U
 
#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00   0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U
 
#define IOMUXC_GPIO_EMC_07_SAI2_MCLK   0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U
 
#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09   0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U
 
#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07   0x401F8030U, 0x4U, 0, 0, 0x401F8220U
 
#define IOMUXC_GPIO_EMC_07_GPIO4_IO07   0x401F8030U, 0x5U, 0, 0, 0x401F8220U
 
#define IOMUXC_GPIO_EMC_08_SEMC_DM00   0x401F8034U, 0x0U, 0, 0, 0x401F8224U
 
#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01   0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U
 
#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA   0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U
 
#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17   0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U
 
#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08   0x401F8034U, 0x4U, 0, 0, 0x401F8224U
 
#define IOMUXC_GPIO_EMC_08_GPIO4_IO08   0x401F8034U, 0x5U, 0, 0, 0x401F8224U
 
#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00   0x401F8038U, 0x0U, 0, 0, 0x401F8228U
 
#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01   0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U
 
#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC   0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U
 
#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX   0x401F8038U, 0x3U, 0, 0, 0x401F8228U
 
#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09   0x401F8038U, 0x4U, 0, 0, 0x401F8228U
 
#define IOMUXC_GPIO_EMC_09_GPIO4_IO09   0x401F8038U, 0x5U, 0, 0, 0x401F8228U
 
#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01   0x401F803CU, 0x0U, 0, 0, 0x401F822CU
 
#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02   0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU
 
#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK   0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU
 
#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX   0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU
 
#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10   0x401F803CU, 0x4U, 0, 0, 0x401F822CU
 
#define IOMUXC_GPIO_EMC_10_GPIO4_IO10   0x401F803CU, 0x5U, 0, 0, 0x401F822CU
 
#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02   0x401F8040U, 0x0U, 0, 0, 0x401F8230U
 
#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02   0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U
 
#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA   0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U
 
#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B   0x401F8040U, 0x3U, 0, 0, 0x401F8230U
 
#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11   0x401F8040U, 0x4U, 0, 0, 0x401F8230U
 
#define IOMUXC_GPIO_EMC_11_GPIO4_IO11   0x401F8040U, 0x5U, 0, 0, 0x401F8230U
 
#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03   0x401F8044U, 0x0U, 0, 0, 0x401F8234U
 
#define IOMUXC_GPIO_EMC_12_XBAR1_IN24   0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U
 
#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL   0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U
 
#define IOMUXC_GPIO_EMC_12_USDHC1_WP   0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U
 
#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03   0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U
 
#define IOMUXC_GPIO_EMC_12_GPIO4_IO12   0x401F8044U, 0x5U, 0, 0, 0x401F8234U
 
#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04   0x401F8048U, 0x0U, 0, 0, 0x401F8238U
 
#define IOMUXC_GPIO_EMC_13_XBAR1_IN25   0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U
 
#define IOMUXC_GPIO_EMC_13_LPUART3_TX   0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U
 
#define IOMUXC_GPIO_EMC_13_MQS_RIGHT   0x401F8048U, 0x3U, 0, 0, 0x401F8238U
 
#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03   0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U
 
#define IOMUXC_GPIO_EMC_13_GPIO4_IO13   0x401F8048U, 0x5U, 0, 0, 0x401F8238U
 
#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05   0x401F804CU, 0x0U, 0, 0, 0x401F823CU
 
#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19   0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU
 
#define IOMUXC_GPIO_EMC_14_LPUART3_RX   0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU
 
#define IOMUXC_GPIO_EMC_14_MQS_LEFT   0x401F804CU, 0x3U, 0, 0, 0x401F823CU
 
#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1   0x401F804CU, 0x4U, 0, 0, 0x401F823CU
 
#define IOMUXC_GPIO_EMC_14_GPIO4_IO14   0x401F804CU, 0x5U, 0, 0, 0x401F823CU
 
#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06   0x401F8050U, 0x0U, 0, 0, 0x401F8240U
 
#define IOMUXC_GPIO_EMC_15_XBAR1_IN20   0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U
 
#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B   0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U
 
#define IOMUXC_GPIO_EMC_15_SPDIF_OUT   0x401F8050U, 0x3U, 0, 0, 0x401F8240U
 
#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0   0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U
 
#define IOMUXC_GPIO_EMC_15_GPIO4_IO15   0x401F8050U, 0x5U, 0, 0, 0x401F8240U
 
#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07   0x401F8054U, 0x0U, 0, 0, 0x401F8244U
 
#define IOMUXC_GPIO_EMC_16_XBAR1_IN21   0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U
 
#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B   0x401F8054U, 0x2U, 0, 0, 0x401F8244U
 
#define IOMUXC_GPIO_EMC_16_SPDIF_IN   0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U
 
#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1   0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U
 
#define IOMUXC_GPIO_EMC_16_GPIO4_IO16   0x401F8054U, 0x5U, 0, 0, 0x401F8244U
 
#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08   0x401F8058U, 0x0U, 0, 0, 0x401F8248U
 
#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03   0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U
 
#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B   0x401F8058U, 0x2U, 0, 0, 0x401F8248U
 
#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX   0x401F8058U, 0x3U, 0, 0, 0x401F8248U
 
#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2   0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U
 
#define IOMUXC_GPIO_EMC_17_GPIO4_IO17   0x401F8058U, 0x5U, 0, 0, 0x401F8248U
 
#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09   0x401F805CU, 0x0U, 0, 0, 0x401F824CU
 
#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03   0x401F805CU, 0x1U, 0, 0, 0x401F824CU
 
#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B   0x401F805CU, 0x2U, 0, 0, 0x401F824CU
 
#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX   0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU
 
#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3   0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU
 
#define IOMUXC_GPIO_EMC_18_GPIO4_IO18   0x401F805CU, 0x5U, 0, 0, 0x401F824CU
 
#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL   0x401F805CU, 0x6U, 0, 0, 0x401F824CU
 
#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11   0x401F8060U, 0x0U, 0, 0, 0x401F8250U
 
#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03   0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U
 
#define IOMUXC_GPIO_EMC_19_LPUART4_TX   0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U
 
#define IOMUXC_GPIO_EMC_19_ENET_RDATA01   0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U
 
#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0   0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U
 
#define IOMUXC_GPIO_EMC_19_GPIO4_IO19   0x401F8060U, 0x5U, 0, 0, 0x401F8250U
 
#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5   0x401F8060U, 0x6U, 0, 0, 0x401F8250U
 
#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12   0x401F8064U, 0x0U, 0, 0, 0x401F8254U
 
#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03   0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U
 
#define IOMUXC_GPIO_EMC_20_LPUART4_RX   0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U
 
#define IOMUXC_GPIO_EMC_20_ENET_RDATA00   0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U
 
#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1   0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U
 
#define IOMUXC_GPIO_EMC_20_GPIO4_IO20   0x401F8064U, 0x5U, 0, 0, 0x401F8254U
 
#define IOMUXC_GPIO_EMC_21_SEMC_BA0   0x401F8068U, 0x0U, 0, 0, 0x401F8258U
 
#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03   0x401F8068U, 0x1U, 0, 0, 0x401F8258U
 
#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA   0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U
 
#define IOMUXC_GPIO_EMC_21_ENET_TDATA01   0x401F8068U, 0x3U, 0, 0, 0x401F8258U
 
#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2   0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U
 
#define IOMUXC_GPIO_EMC_21_GPIO4_IO21   0x401F8068U, 0x5U, 0, 0, 0x401F8258U
 
#define IOMUXC_GPIO_EMC_22_SEMC_BA1   0x401F806CU, 0x0U, 0, 0, 0x401F825CU
 
#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03   0x401F806CU, 0x1U, 0, 0, 0x401F825CU
 
#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL   0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU
 
#define IOMUXC_GPIO_EMC_22_ENET_TDATA00   0x401F806CU, 0x3U, 0, 0, 0x401F825CU
 
#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3   0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU
 
#define IOMUXC_GPIO_EMC_22_GPIO4_IO22   0x401F806CU, 0x5U, 0, 0, 0x401F825CU
 
#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10   0x401F8070U, 0x0U, 0, 0, 0x401F8260U
 
#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00   0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U
 
#define IOMUXC_GPIO_EMC_23_LPUART5_TX   0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U
 
#define IOMUXC_GPIO_EMC_23_ENET_RX_EN   0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U
 
#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2   0x401F8070U, 0x4U, 0, 0, 0x401F8260U
 
#define IOMUXC_GPIO_EMC_23_GPIO4_IO23   0x401F8070U, 0x5U, 0, 0, 0x401F8260U
 
#define IOMUXC_GPIO_EMC_24_SEMC_CAS   0x401F8074U, 0x0U, 0, 0, 0x401F8264U
 
#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00   0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U
 
#define IOMUXC_GPIO_EMC_24_LPUART5_RX   0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U
 
#define IOMUXC_GPIO_EMC_24_ENET_TX_EN   0x401F8074U, 0x3U, 0, 0, 0x401F8264U
 
#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1   0x401F8074U, 0x4U, 0, 0, 0x401F8264U
 
#define IOMUXC_GPIO_EMC_24_GPIO4_IO24   0x401F8074U, 0x5U, 0, 0, 0x401F8264U
 
#define IOMUXC_GPIO_EMC_25_SEMC_RAS   0x401F8078U, 0x0U, 0, 0, 0x401F8268U
 
#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01   0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U
 
#define IOMUXC_GPIO_EMC_25_LPUART6_TX   0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U
 
#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK   0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U
 
#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK   0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U
 
#define IOMUXC_GPIO_EMC_25_GPIO4_IO25   0x401F8078U, 0x5U, 0, 0, 0x401F8268U
 
#define IOMUXC_GPIO_EMC_26_SEMC_CLK   0x401F807CU, 0x0U, 0, 0, 0x401F826CU
 
#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01   0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU
 
#define IOMUXC_GPIO_EMC_26_LPUART6_RX   0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU
 
#define IOMUXC_GPIO_EMC_26_ENET_RX_ER   0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU
 
#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12   0x401F807CU, 0x4U, 0, 0, 0x401F826CU
 
#define IOMUXC_GPIO_EMC_26_GPIO4_IO26   0x401F807CU, 0x5U, 0, 0, 0x401F826CU
 
#define IOMUXC_GPIO_EMC_27_SEMC_CKE   0x401F8080U, 0x0U, 0, 0, 0x401F8270U
 
#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02   0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U
 
#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B   0x401F8080U, 0x2U, 0, 0, 0x401F8270U
 
#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK   0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U
 
#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13   0x401F8080U, 0x4U, 0, 0, 0x401F8270U
 
#define IOMUXC_GPIO_EMC_27_GPIO4_IO27   0x401F8080U, 0x5U, 0, 0, 0x401F8270U
 
#define IOMUXC_GPIO_EMC_28_SEMC_WE   0x401F8084U, 0x0U, 0, 0, 0x401F8274U
 
#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02   0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U
 
#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B   0x401F8084U, 0x2U, 0, 0, 0x401F8274U
 
#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO   0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U
 
#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14   0x401F8084U, 0x4U, 0, 0, 0x401F8274U
 
#define IOMUXC_GPIO_EMC_28_GPIO4_IO28   0x401F8084U, 0x5U, 0, 0, 0x401F8274U
 
#define IOMUXC_GPIO_EMC_29_SEMC_CS0   0x401F8088U, 0x0U, 0, 0, 0x401F8278U
 
#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00   0x401F8088U, 0x1U, 0, 0, 0x401F8278U
 
#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B   0x401F8088U, 0x2U, 0, 0, 0x401F8278U
 
#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI   0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U
 
#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15   0x401F8088U, 0x4U, 0, 0, 0x401F8278U
 
#define IOMUXC_GPIO_EMC_29_GPIO4_IO29   0x401F8088U, 0x5U, 0, 0, 0x401F8278U
 
#define IOMUXC_GPIO_EMC_30_SEMC_DATA08   0x401F808CU, 0x0U, 0, 0, 0x401F827CU
 
#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00   0x401F808CU, 0x1U, 0, 0, 0x401F827CU
 
#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B   0x401F808CU, 0x2U, 0, 0, 0x401F827CU
 
#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0   0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU
 
#define IOMUXC_GPIO_EMC_30_CSI_DATA23   0x401F808CU, 0x4U, 0, 0, 0x401F827CU
 
#define IOMUXC_GPIO_EMC_30_GPIO4_IO30   0x401F808CU, 0x5U, 0, 0, 0x401F827CU
 
#define IOMUXC_GPIO_EMC_31_SEMC_DATA09   0x401F8090U, 0x0U, 0, 0, 0x401F8280U
 
#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01   0x401F8090U, 0x1U, 0, 0, 0x401F8280U
 
#define IOMUXC_GPIO_EMC_31_LPUART7_TX   0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U
 
#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1   0x401F8090U, 0x3U, 0, 0, 0x401F8280U
 
#define IOMUXC_GPIO_EMC_31_CSI_DATA22   0x401F8090U, 0x4U, 0, 0, 0x401F8280U
 
#define IOMUXC_GPIO_EMC_31_GPIO4_IO31   0x401F8090U, 0x5U, 0, 0, 0x401F8280U
 
#define IOMUXC_GPIO_EMC_32_SEMC_DATA10   0x401F8094U, 0x0U, 0, 0, 0x401F8284U
 
#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01   0x401F8094U, 0x1U, 0, 0, 0x401F8284U
 
#define IOMUXC_GPIO_EMC_32_LPUART7_RX   0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U
 
#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY   0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U
 
#define IOMUXC_GPIO_EMC_32_CSI_DATA21   0x401F8094U, 0x4U, 0, 0, 0x401F8284U
 
#define IOMUXC_GPIO_EMC_32_GPIO3_IO18   0x401F8094U, 0x5U, 0, 0, 0x401F8284U
 
#define IOMUXC_GPIO_EMC_33_SEMC_DATA11   0x401F8098U, 0x0U, 0, 0, 0x401F8288U
 
#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02   0x401F8098U, 0x1U, 0, 0, 0x401F8288U
 
#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B   0x401F8098U, 0x2U, 0, 0, 0x401F8288U
 
#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA   0x401F8098U, 0x3U, 0, 0, 0x401F8288U
 
#define IOMUXC_GPIO_EMC_33_CSI_DATA20   0x401F8098U, 0x4U, 0, 0, 0x401F8288U
 
#define IOMUXC_GPIO_EMC_33_GPIO3_IO19   0x401F8098U, 0x5U, 0, 0, 0x401F8288U
 
#define IOMUXC_GPIO_EMC_34_SEMC_DATA12   0x401F809CU, 0x0U, 0, 0, 0x401F828CU
 
#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02   0x401F809CU, 0x1U, 0, 0, 0x401F828CU
 
#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT   0x401F809CU, 0x2U, 0, 0, 0x401F828CU
 
#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC   0x401F809CU, 0x3U, 0, 0, 0x401F828CU
 
#define IOMUXC_GPIO_EMC_34_CSI_DATA19   0x401F809CU, 0x4U, 0, 0, 0x401F828CU
 
#define IOMUXC_GPIO_EMC_34_GPIO3_IO20   0x401F809CU, 0x5U, 0, 0, 0x401F828CU
 
#define IOMUXC_GPIO_EMC_35_SEMC_DATA13   0x401F80A0U, 0x0U, 0, 0, 0x401F8290U
 
#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18   0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U
 
#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1   0x401F80A0U, 0x2U, 0, 0, 0x401F8290U
 
#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK   0x401F80A0U, 0x3U, 0, 0, 0x401F8290U
 
#define IOMUXC_GPIO_EMC_35_CSI_DATA18   0x401F80A0U, 0x4U, 0, 0, 0x401F8290U
 
#define IOMUXC_GPIO_EMC_35_GPIO3_IO21   0x401F80A0U, 0x5U, 0, 0, 0x401F8290U
 
#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B   0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U
 
#define IOMUXC_GPIO_EMC_36_SEMC_DATA14   0x401F80A4U, 0x0U, 0, 0, 0x401F8294U
 
#define IOMUXC_GPIO_EMC_36_XBAR1_IN22   0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U
 
#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2   0x401F80A4U, 0x2U, 0, 0, 0x401F8294U
 
#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA   0x401F80A4U, 0x3U, 0, 0, 0x401F8294U
 
#define IOMUXC_GPIO_EMC_36_CSI_DATA17   0x401F80A4U, 0x4U, 0, 0, 0x401F8294U
 
#define IOMUXC_GPIO_EMC_36_GPIO3_IO22   0x401F80A4U, 0x5U, 0, 0, 0x401F8294U
 
#define IOMUXC_GPIO_EMC_36_USDHC1_WP   0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U
 
#define IOMUXC_GPIO_EMC_37_SEMC_DATA15   0x401F80A8U, 0x0U, 0, 0, 0x401F8298U
 
#define IOMUXC_GPIO_EMC_37_XBAR1_IN23   0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U
 
#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3   0x401F80A8U, 0x2U, 0, 0, 0x401F8298U
 
#define IOMUXC_GPIO_EMC_37_SAI3_MCLK   0x401F80A8U, 0x3U, 0, 0, 0x401F8298U
 
#define IOMUXC_GPIO_EMC_37_CSI_DATA16   0x401F80A8U, 0x4U, 0, 0, 0x401F8298U
 
#define IOMUXC_GPIO_EMC_37_GPIO3_IO23   0x401F80A8U, 0x5U, 0, 0, 0x401F8298U
 
#define IOMUXC_GPIO_EMC_37_USDHC2_WP   0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U
 
#define IOMUXC_GPIO_EMC_38_SEMC_DM01   0x401F80ACU, 0x0U, 0, 0, 0x401F829CU
 
#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03   0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU
 
#define IOMUXC_GPIO_EMC_38_LPUART8_TX   0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU
 
#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK   0x401F80ACU, 0x3U, 0, 0, 0x401F829CU
 
#define IOMUXC_GPIO_EMC_38_CSI_FIELD   0x401F80ACU, 0x4U, 0, 0, 0x401F829CU
 
#define IOMUXC_GPIO_EMC_38_GPIO3_IO24   0x401F80ACU, 0x5U, 0, 0, 0x401F829CU
 
#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT   0x401F80ACU, 0x6U, 0, 0, 0x401F829CU
 
#define IOMUXC_GPIO_EMC_39_SEMC_DQS   0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U
 
#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03   0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U
 
#define IOMUXC_GPIO_EMC_39_LPUART8_RX   0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U
 
#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC   0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U
 
#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B   0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U
 
#define IOMUXC_GPIO_EMC_39_GPIO3_IO25   0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U
 
#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B   0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U
 
#define IOMUXC_GPIO_EMC_40_SEMC_RDY   0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U
 
#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2   0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U
 
#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2   0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U
 
#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC   0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U
 
#define IOMUXC_GPIO_EMC_40_ENET_MDC   0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U
 
#define IOMUXC_GPIO_EMC_40_GPIO3_IO26   0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U
 
#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B   0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U
 
#define IOMUXC_GPIO_EMC_41_SEMC_CSX00   0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U
 
#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1   0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U
 
#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3   0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U
 
#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR   0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U
 
#define IOMUXC_GPIO_EMC_41_ENET_MDIO   0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U
 
#define IOMUXC_GPIO_EMC_41_GPIO3_IO27   0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U
 
#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT   0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U
 
#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03   0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14   0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K   0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID   0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS   0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00   0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B   0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK   0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU
 
#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03   0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15   0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M   0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID   0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS   0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01   0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B   0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO   0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U
 
#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX   0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16   0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX   0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR   0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00   0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02   0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ   0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI   0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U
 
#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX   0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17   0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX   0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC   0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01   0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03   0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M   0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0   0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U
 
#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00   0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT   0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03   0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC   0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09   0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04   0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00   0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1   0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU
 
#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01   0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT   0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02   0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK   0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08   0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05   0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17   0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2   0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U
 
#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS   0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1   0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK   0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK   0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07   0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06   0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18   0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3   0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U
 
#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK   0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2   0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER   0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC   0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06   0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07   0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19   0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT   0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U
 
#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD   0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3   0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03   0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA   0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05   0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08   0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20   0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN   0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU
 
#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI   0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03   0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02   0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA   0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04   0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09   0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21   0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK   0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U
 
#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO   0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03   0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_10_ENET_CRS   0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK   0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03   0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10   0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22   0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT   0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U
 
#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB   0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03   0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_11_ENET_COL   0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B   0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02   0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11   0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23   0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN   0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U
 
#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL   0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY   0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX   0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B   0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02   0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12   0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT   0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI   0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU
 
#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA   0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK   0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX   0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B   0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03   0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13   0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN   0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M   0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U
 
#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC   0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U
 
#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24   0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U
 
#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B   0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U
 
#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT   0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U
 
#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC   0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U
 
#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14   0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U
 
#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX   0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U
 
#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR   0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25   0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B   0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN   0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC   0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15   0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX   0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB   0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U
 
#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID   0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0   0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B   0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL   0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_00_WDOG1_B   0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16   0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP   0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07   0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU
 
#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR   0x401F8100U, 0x0U, 0, 0, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1   0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B   0x401F8100U, 0x2U, 0, 0, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA   0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY   0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17   0x401F8100U, 0x5U, 0, 0, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT   0x401F8100U, 0x6U, 0, 0, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_01_KPP_COL07   0x401F8100U, 0x7U, 0, 0, 0x401F82F0U
 
#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID   0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2   0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX   0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT   0x401F8104U, 0x3U, 0, 0, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT   0x401F8104U, 0x4U, 0, 0, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18   0x401F8104U, 0x5U, 0, 0, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B   0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06   0x401F8104U, 0x7U, 0, 0, 0x401F82F4U
 
#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC   0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3   0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX   0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN   0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN   0x401F8108U, 0x4U, 0, 0, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19   0x401F8108U, 0x5U, 0, 0, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B   0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_03_KPP_COL06   0x401F8108U, 0x7U, 0, 0, 0x401F82F8U
 
#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03   0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_04_ENET_MDC   0x401F810CU, 0x1U, 0, 0, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B   0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK   0x401F810CU, 0x3U, 0, 0, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK   0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20   0x401F810CU, 0x5U, 0, 0, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0   0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05   0x401F810CU, 0x7U, 0, 0, 0x401F82FCU
 
#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02   0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO   0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B   0x401F8110U, 0x2U, 0, 0, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT   0x401F8110U, 0x3U, 0, 0, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK   0x401F8110U, 0x4U, 0, 0, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21   0x401F8110U, 0x5U, 0, 0, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1   0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_05_KPP_COL05   0x401F8110U, 0x7U, 0, 0, 0x401F8300U
 
#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01   0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA   0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX   0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK   0x401F8114U, 0x3U, 0, 0, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC   0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22   0x401F8114U, 0x5U, 0, 0, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2   0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04   0x401F8114U, 0x7U, 0, 0, 0x401F8304U
 
#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00   0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL   0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX   0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK   0x401F8118U, 0x3U, 0, 0, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC   0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23   0x401F8118U, 0x5U, 0, 0, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3   0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_07_KPP_COL04   0x401F8118U, 0x7U, 0, 0, 0x401F8308U
 
#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B   0x401F811CU, 0x0U, 0, 0, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00   0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX   0x401F811CU, 0x2U, 0, 0, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY   0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09   0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24   0x401F811CU, 0x5U, 0, 0, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD   0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03   0x401F811CU, 0x7U, 0, 0, 0x401F830CU
 
#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS   0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01   0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX   0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK   0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08   0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25   0x401F8120U, 0x5U, 0, 0, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK   0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_09_KPP_COL03   0x401F8120U, 0x7U, 0, 0, 0x401F8310U
 
#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03   0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_10_WDOG1_B   0x401F8124U, 0x1U, 0, 0, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX   0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC   0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07   0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26   0x401F8124U, 0x5U, 0, 0, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP   0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02   0x401F8124U, 0x7U, 0, 0, 0x401F8314U
 
#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02   0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B   0x401F8128U, 0x1U, 0, 0, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX   0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK   0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06   0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27   0x401F8128U, 0x5U, 0, 0, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B   0x401F8128U, 0x6U, 0, 0, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_11_KPP_COL02   0x401F8128U, 0x7U, 0, 0, 0x401F8318U
 
#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01   0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00   0x401F812CU, 0x1U, 0, 0, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0   0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00   0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05   0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28   0x401F812CU, 0x5U, 0, 0, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4   0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01   0x401F812CU, 0x7U, 0, 0, 0x401F831CU
 
#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00   0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01   0x401F8130U, 0x1U, 0, 0, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI   0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00   0x401F8130U, 0x3U, 0, 0, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04   0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29   0x401F8130U, 0x5U, 0, 0, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5   0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_13_KPP_COL01   0x401F8130U, 0x7U, 0, 0, 0x401F8320U
 
#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK   0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02   0x401F8134U, 0x1U, 0, 0, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO   0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK   0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03   0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30   0x401F8134U, 0x5U, 0, 0, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6   0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00   0x401F8134U, 0x7U, 0, 0, 0x401F8324U
 
#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B   0x401F8138U, 0x0U, 0, 0, 0x401F8328U
 
#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03   0x401F8138U, 0x1U, 0, 0, 0x401F8328U
 
#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK   0x401F8138U, 0x2U, 0, 0, 0x401F8328U
 
#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC   0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U
 
#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02   0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U
 
#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31   0x401F8138U, 0x5U, 0, 0, 0x401F8328U
 
#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7   0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U
 
#define IOMUXC_GPIO_AD_B1_15_KPP_COL00   0x401F8138U, 0x7U, 0, 0, 0x401F8328U
 
#define IOMUXC_GPIO_B0_00_LCD_CLK   0x401F813CU, 0x0U, 0, 0, 0x401F832CU
 
#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0   0x401F813CU, 0x1U, 0, 0, 0x401F832CU
 
#define IOMUXC_GPIO_B0_00_MQS_RIGHT   0x401F813CU, 0x2U, 0, 0, 0x401F832CU
 
#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0   0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU
 
#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00   0x401F813CU, 0x4U, 0, 0, 0x401F832CU
 
#define IOMUXC_GPIO_B0_00_GPIO2_IO00   0x401F813CU, 0x5U, 0, 0, 0x401F832CU
 
#define IOMUXC_GPIO_B0_00_SEMC_CSX01   0x401F813CU, 0x6U, 0, 0, 0x401F832CU
 
#define IOMUXC_GPIO_B0_01_LCD_ENABLE   0x401F8140U, 0x0U, 0, 0, 0x401F8330U
 
#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1   0x401F8140U, 0x1U, 0, 0, 0x401F8330U
 
#define IOMUXC_GPIO_B0_01_MQS_LEFT   0x401F8140U, 0x2U, 0, 0, 0x401F8330U
 
#define IOMUXC_GPIO_B0_01_LPSPI4_SDI   0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U
 
#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01   0x401F8140U, 0x4U, 0, 0, 0x401F8330U
 
#define IOMUXC_GPIO_B0_01_GPIO2_IO01   0x401F8140U, 0x5U, 0, 0, 0x401F8330U
 
#define IOMUXC_GPIO_B0_01_SEMC_CSX02   0x401F8140U, 0x6U, 0, 0, 0x401F8330U
 
#define IOMUXC_GPIO_B0_02_LCD_HSYNC   0x401F8144U, 0x0U, 0, 0, 0x401F8334U
 
#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2   0x401F8144U, 0x1U, 0, 0, 0x401F8334U
 
#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX   0x401F8144U, 0x2U, 0, 0, 0x401F8334U
 
#define IOMUXC_GPIO_B0_02_LPSPI4_SDO   0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U
 
#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02   0x401F8144U, 0x4U, 0, 0, 0x401F8334U
 
#define IOMUXC_GPIO_B0_02_GPIO2_IO02   0x401F8144U, 0x5U, 0, 0, 0x401F8334U
 
#define IOMUXC_GPIO_B0_02_SEMC_CSX03   0x401F8144U, 0x6U, 0, 0, 0x401F8334U
 
#define IOMUXC_GPIO_B0_03_LCD_VSYNC   0x401F8148U, 0x0U, 0, 0, 0x401F8338U
 
#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0   0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U
 
#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX   0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U
 
#define IOMUXC_GPIO_B0_03_LPSPI4_SCK   0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U
 
#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03   0x401F8148U, 0x4U, 0, 0, 0x401F8338U
 
#define IOMUXC_GPIO_B0_03_GPIO2_IO03   0x401F8148U, 0x5U, 0, 0, 0x401F8338U
 
#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB   0x401F8148U, 0x6U, 0, 0, 0x401F8338U
 
#define IOMUXC_GPIO_B0_04_LCD_DATA00   0x401F814CU, 0x0U, 0, 0, 0x401F833CU
 
#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1   0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU
 
#define IOMUXC_GPIO_B0_04_LPI2C2_SCL   0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU
 
#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00   0x401F814CU, 0x3U, 0, 0, 0x401F833CU
 
#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04   0x401F814CU, 0x4U, 0, 0, 0x401F833CU
 
#define IOMUXC_GPIO_B0_04_GPIO2_IO04   0x401F814CU, 0x5U, 0, 0, 0x401F833CU
 
#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00   0x401F814CU, 0x6U, 0, 0, 0x401F833CU
 
#define IOMUXC_GPIO_B0_05_LCD_DATA01   0x401F8150U, 0x0U, 0, 0, 0x401F8340U
 
#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2   0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U
 
#define IOMUXC_GPIO_B0_05_LPI2C2_SDA   0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U
 
#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01   0x401F8150U, 0x3U, 0, 0, 0x401F8340U
 
#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05   0x401F8150U, 0x4U, 0, 0, 0x401F8340U
 
#define IOMUXC_GPIO_B0_05_GPIO2_IO05   0x401F8150U, 0x5U, 0, 0, 0x401F8340U
 
#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01   0x401F8150U, 0x6U, 0, 0, 0x401F8340U
 
#define IOMUXC_GPIO_B0_06_LCD_DATA02   0x401F8154U, 0x0U, 0, 0, 0x401F8344U
 
#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0   0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U
 
#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00   0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U
 
#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02   0x401F8154U, 0x3U, 0, 0, 0x401F8344U
 
#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06   0x401F8154U, 0x4U, 0, 0, 0x401F8344U
 
#define IOMUXC_GPIO_B0_06_GPIO2_IO06   0x401F8154U, 0x5U, 0, 0, 0x401F8344U
 
#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02   0x401F8154U, 0x6U, 0, 0, 0x401F8344U
 
#define IOMUXC_GPIO_B0_07_LCD_DATA03   0x401F8158U, 0x0U, 0, 0, 0x401F8348U
 
#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1   0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U
 
#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00   0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U
 
#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03   0x401F8158U, 0x3U, 0, 0, 0x401F8348U
 
#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07   0x401F8158U, 0x4U, 0, 0, 0x401F8348U
 
#define IOMUXC_GPIO_B0_07_GPIO2_IO07   0x401F8158U, 0x5U, 0, 0, 0x401F8348U
 
#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03   0x401F8158U, 0x6U, 0, 0, 0x401F8348U
 
#define IOMUXC_GPIO_B0_08_LCD_DATA04   0x401F815CU, 0x0U, 0, 0, 0x401F834CU
 
#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2   0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU
 
#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01   0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU
 
#define IOMUXC_GPIO_B0_08_LPUART3_TX   0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU
 
#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08   0x401F815CU, 0x4U, 0, 0, 0x401F834CU
 
#define IOMUXC_GPIO_B0_08_GPIO2_IO08   0x401F815CU, 0x5U, 0, 0, 0x401F834CU
 
#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04   0x401F815CU, 0x6U, 0, 0, 0x401F834CU
 
#define IOMUXC_GPIO_B0_09_LCD_DATA05   0x401F8160U, 0x0U, 0, 0, 0x401F8350U
 
#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0   0x401F8160U, 0x1U, 0, 0, 0x401F8350U
 
#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01   0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U
 
#define IOMUXC_GPIO_B0_09_LPUART3_RX   0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U
 
#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09   0x401F8160U, 0x4U, 0, 0, 0x401F8350U
 
#define IOMUXC_GPIO_B0_09_GPIO2_IO09   0x401F8160U, 0x5U, 0, 0, 0x401F8350U
 
#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05   0x401F8160U, 0x6U, 0, 0, 0x401F8350U
 
#define IOMUXC_GPIO_B0_10_LCD_DATA06   0x401F8164U, 0x0U, 0, 0, 0x401F8354U
 
#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1   0x401F8164U, 0x1U, 0, 0, 0x401F8354U
 
#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02   0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U
 
#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03   0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U
 
#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10   0x401F8164U, 0x4U, 0, 0, 0x401F8354U
 
#define IOMUXC_GPIO_B0_10_GPIO2_IO10   0x401F8164U, 0x5U, 0, 0, 0x401F8354U
 
#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06   0x401F8164U, 0x6U, 0, 0, 0x401F8354U
 
#define IOMUXC_GPIO_B0_11_LCD_DATA07   0x401F8168U, 0x0U, 0, 0, 0x401F8358U
 
#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2   0x401F8168U, 0x1U, 0, 0, 0x401F8358U
 
#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02   0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U
 
#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02   0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U
 
#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11   0x401F8168U, 0x4U, 0, 0, 0x401F8358U
 
#define IOMUXC_GPIO_B0_11_GPIO2_IO11   0x401F8168U, 0x5U, 0, 0, 0x401F8358U
 
#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07   0x401F8168U, 0x6U, 0, 0, 0x401F8358U
 
#define IOMUXC_GPIO_B0_12_LCD_DATA08   0x401F816CU, 0x0U, 0, 0, 0x401F835CU
 
#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10   0x401F816CU, 0x1U, 0, 0, 0x401F835CU
 
#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK   0x401F816CU, 0x2U, 0, 0, 0x401F835CU
 
#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01   0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU
 
#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12   0x401F816CU, 0x4U, 0, 0, 0x401F835CU
 
#define IOMUXC_GPIO_B0_12_GPIO2_IO12   0x401F816CU, 0x5U, 0, 0, 0x401F835CU
 
#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08   0x401F816CU, 0x6U, 0, 0, 0x401F835CU
 
#define IOMUXC_GPIO_B0_13_LCD_DATA09   0x401F8170U, 0x0U, 0, 0, 0x401F8360U
 
#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11   0x401F8170U, 0x1U, 0, 0, 0x401F8360U
 
#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO   0x401F8170U, 0x2U, 0, 0, 0x401F8360U
 
#define IOMUXC_GPIO_B0_13_SAI1_MCLK   0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U
 
#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13   0x401F8170U, 0x4U, 0, 0, 0x401F8360U
 
#define IOMUXC_GPIO_B0_13_GPIO2_IO13   0x401F8170U, 0x5U, 0, 0, 0x401F8360U
 
#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09   0x401F8170U, 0x6U, 0, 0, 0x401F8360U
 
#define IOMUXC_GPIO_B0_14_LCD_DATA10   0x401F8174U, 0x0U, 0, 0, 0x401F8364U
 
#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12   0x401F8174U, 0x1U, 0, 0, 0x401F8364U
 
#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV   0x401F8174U, 0x2U, 0, 0, 0x401F8364U
 
#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC   0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U
 
#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14   0x401F8174U, 0x4U, 0, 0, 0x401F8364U
 
#define IOMUXC_GPIO_B0_14_GPIO2_IO14   0x401F8174U, 0x5U, 0, 0, 0x401F8364U
 
#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10   0x401F8174U, 0x6U, 0, 0, 0x401F8364U
 
#define IOMUXC_GPIO_B0_15_LCD_DATA11   0x401F8178U, 0x0U, 0, 0, 0x401F8368U
 
#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13   0x401F8178U, 0x1U, 0, 0, 0x401F8368U
 
#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV   0x401F8178U, 0x2U, 0, 0, 0x401F8368U
 
#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK   0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U
 
#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15   0x401F8178U, 0x4U, 0, 0, 0x401F8368U
 
#define IOMUXC_GPIO_B0_15_GPIO2_IO15   0x401F8178U, 0x5U, 0, 0, 0x401F8368U
 
#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11   0x401F8178U, 0x6U, 0, 0, 0x401F8368U
 
#define IOMUXC_GPIO_B1_00_LCD_DATA12   0x401F817CU, 0x0U, 0, 0, 0x401F836CU
 
#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14   0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU
 
#define IOMUXC_GPIO_B1_00_LPUART4_TX   0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU
 
#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00   0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU
 
#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16   0x401F817CU, 0x4U, 0, 0, 0x401F836CU
 
#define IOMUXC_GPIO_B1_00_GPIO2_IO16   0x401F817CU, 0x5U, 0, 0, 0x401F836CU
 
#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03   0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU
 
#define IOMUXC_GPIO_B1_01_LCD_DATA13   0x401F8180U, 0x0U, 0, 0, 0x401F8370U
 
#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15   0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U
 
#define IOMUXC_GPIO_B1_01_LPUART4_RX   0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U
 
#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00   0x401F8180U, 0x3U, 0, 0, 0x401F8370U
 
#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17   0x401F8180U, 0x4U, 0, 0, 0x401F8370U
 
#define IOMUXC_GPIO_B1_01_GPIO2_IO17   0x401F8180U, 0x5U, 0, 0, 0x401F8370U
 
#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03   0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U
 
#define IOMUXC_GPIO_B1_02_LCD_DATA14   0x401F8184U, 0x0U, 0, 0, 0x401F8374U
 
#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16   0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U
 
#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2   0x401F8184U, 0x2U, 0, 0, 0x401F8374U
 
#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK   0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U
 
#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18   0x401F8184U, 0x4U, 0, 0, 0x401F8374U
 
#define IOMUXC_GPIO_B1_02_GPIO2_IO18   0x401F8184U, 0x5U, 0, 0, 0x401F8374U
 
#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03   0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U
 
#define IOMUXC_GPIO_B1_03_LCD_DATA15   0x401F8188U, 0x0U, 0, 0, 0x401F8378U
 
#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17   0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U
 
#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1   0x401F8188U, 0x2U, 0, 0, 0x401F8378U
 
#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC   0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U
 
#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19   0x401F8188U, 0x4U, 0, 0, 0x401F8378U
 
#define IOMUXC_GPIO_B1_03_GPIO2_IO19   0x401F8188U, 0x5U, 0, 0, 0x401F8378U
 
#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03   0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U
 
#define IOMUXC_GPIO_B1_04_LCD_DATA16   0x401F818CU, 0x0U, 0, 0, 0x401F837CU
 
#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0   0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU
 
#define IOMUXC_GPIO_B1_04_CSI_DATA15   0x401F818CU, 0x2U, 0, 0, 0x401F837CU
 
#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00   0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU
 
#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20   0x401F818CU, 0x4U, 0, 0, 0x401F837CU
 
#define IOMUXC_GPIO_B1_04_GPIO2_IO20   0x401F818CU, 0x5U, 0, 0, 0x401F837CU
 
#define IOMUXC_GPIO_B1_05_LCD_DATA17   0x401F8190U, 0x0U, 0, 0, 0x401F8380U
 
#define IOMUXC_GPIO_B1_05_LPSPI4_SDI   0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U
 
#define IOMUXC_GPIO_B1_05_CSI_DATA14   0x401F8190U, 0x2U, 0, 0, 0x401F8380U
 
#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01   0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U
 
#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21   0x401F8190U, 0x4U, 0, 0, 0x401F8380U
 
#define IOMUXC_GPIO_B1_05_GPIO2_IO21   0x401F8190U, 0x5U, 0, 0, 0x401F8380U
 
#define IOMUXC_GPIO_B1_06_LCD_DATA18   0x401F8194U, 0x0U, 0, 0, 0x401F8384U
 
#define IOMUXC_GPIO_B1_06_LPSPI4_SDO   0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U
 
#define IOMUXC_GPIO_B1_06_CSI_DATA13   0x401F8194U, 0x2U, 0, 0, 0x401F8384U
 
#define IOMUXC_GPIO_B1_06_ENET_RX_EN   0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U
 
#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22   0x401F8194U, 0x4U, 0, 0, 0x401F8384U
 
#define IOMUXC_GPIO_B1_06_GPIO2_IO22   0x401F8194U, 0x5U, 0, 0, 0x401F8384U
 
#define IOMUXC_GPIO_B1_07_LCD_DATA19   0x401F8198U, 0x0U, 0, 0, 0x401F8388U
 
#define IOMUXC_GPIO_B1_07_LPSPI4_SCK   0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U
 
#define IOMUXC_GPIO_B1_07_CSI_DATA12   0x401F8198U, 0x2U, 0, 0, 0x401F8388U
 
#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00   0x401F8198U, 0x3U, 0, 0, 0x401F8388U
 
#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23   0x401F8198U, 0x4U, 0, 0, 0x401F8388U
 
#define IOMUXC_GPIO_B1_07_GPIO2_IO23   0x401F8198U, 0x5U, 0, 0, 0x401F8388U
 
#define IOMUXC_GPIO_B1_08_LCD_DATA20   0x401F819CU, 0x0U, 0, 0, 0x401F838CU
 
#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3   0x401F819CU, 0x1U, 0, 0, 0x401F838CU
 
#define IOMUXC_GPIO_B1_08_CSI_DATA11   0x401F819CU, 0x2U, 0, 0, 0x401F838CU
 
#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01   0x401F819CU, 0x3U, 0, 0, 0x401F838CU
 
#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24   0x401F819CU, 0x4U, 0, 0, 0x401F838CU
 
#define IOMUXC_GPIO_B1_08_GPIO2_IO24   0x401F819CU, 0x5U, 0, 0, 0x401F838CU
 
#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX   0x401F819CU, 0x6U, 0, 0, 0x401F838CU
 
#define IOMUXC_GPIO_B1_09_LCD_DATA21   0x401F81A0U, 0x0U, 0, 0, 0x401F8390U
 
#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3   0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U
 
#define IOMUXC_GPIO_B1_09_CSI_DATA10   0x401F81A0U, 0x2U, 0, 0, 0x401F8390U
 
#define IOMUXC_GPIO_B1_09_ENET_TX_EN   0x401F81A0U, 0x3U, 0, 0, 0x401F8390U
 
#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25   0x401F81A0U, 0x4U, 0, 0, 0x401F8390U
 
#define IOMUXC_GPIO_B1_09_GPIO2_IO25   0x401F81A0U, 0x5U, 0, 0, 0x401F8390U
 
#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX   0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U
 
#define IOMUXC_GPIO_B1_10_LCD_DATA22   0x401F81A4U, 0x0U, 0, 0, 0x401F8394U
 
#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3   0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U
 
#define IOMUXC_GPIO_B1_10_CSI_DATA00   0x401F81A4U, 0x2U, 0, 0, 0x401F8394U
 
#define IOMUXC_GPIO_B1_10_ENET_TX_CLK   0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U
 
#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26   0x401F81A4U, 0x4U, 0, 0, 0x401F8394U
 
#define IOMUXC_GPIO_B1_10_GPIO2_IO26   0x401F81A4U, 0x5U, 0, 0, 0x401F8394U
 
#define IOMUXC_GPIO_B1_10_ENET_REF_CLK   0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U
 
#define IOMUXC_GPIO_B1_11_LCD_DATA23   0x401F81A8U, 0x0U, 0, 0, 0x401F8398U
 
#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3   0x401F81A8U, 0x1U, 0, 0, 0x401F8398U
 
#define IOMUXC_GPIO_B1_11_CSI_DATA01   0x401F81A8U, 0x2U, 0, 0, 0x401F8398U
 
#define IOMUXC_GPIO_B1_11_ENET_RX_ER   0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U
 
#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27   0x401F81A8U, 0x4U, 0, 0, 0x401F8398U
 
#define IOMUXC_GPIO_B1_11_GPIO2_IO27   0x401F81A8U, 0x5U, 0, 0, 0x401F8398U
 
#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3   0x401F81A8U, 0x6U, 0, 0, 0x401F8398U
 
#define IOMUXC_GPIO_B1_12_LPUART5_TX   0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU
 
#define IOMUXC_GPIO_B1_12_CSI_PIXCLK   0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU
 
#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN   0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU
 
#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28   0x401F81ACU, 0x4U, 0, 0, 0x401F839CU
 
#define IOMUXC_GPIO_B1_12_GPIO2_IO28   0x401F81ACU, 0x5U, 0, 0, 0x401F839CU
 
#define IOMUXC_GPIO_B1_12_USDHC1_CD_B   0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU
 
#define IOMUXC_GPIO_B1_13_WDOG1_B   0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U
 
#define IOMUXC_GPIO_B1_13_LPUART5_RX   0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U
 
#define IOMUXC_GPIO_B1_13_CSI_VSYNC   0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U
 
#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT   0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U
 
#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29   0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U
 
#define IOMUXC_GPIO_B1_13_GPIO2_IO29   0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U
 
#define IOMUXC_GPIO_B1_13_USDHC1_WP   0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U
 
#define IOMUXC_GPIO_B1_14_ENET_MDC   0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U
 
#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02   0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U
 
#define IOMUXC_GPIO_B1_14_CSI_HSYNC   0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U
 
#define IOMUXC_GPIO_B1_14_XBAR1_IN02   0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U
 
#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30   0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U
 
#define IOMUXC_GPIO_B1_14_GPIO2_IO30   0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U
 
#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT   0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U
 
#define IOMUXC_GPIO_B1_15_ENET_MDIO   0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U
 
#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03   0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U
 
#define IOMUXC_GPIO_B1_15_CSI_MCLK   0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U
 
#define IOMUXC_GPIO_B1_15_XBAR1_IN03   0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U
 
#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31   0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U
 
#define IOMUXC_GPIO_B1_15_GPIO2_IO31   0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U
 
#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B   0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U
 
#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD   0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU
 
#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00   0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU
 
#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL   0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU
 
#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04   0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU
 
#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK   0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU
 
#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12   0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU
 
#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B   0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU
 
#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK   0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U
 
#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00   0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U
 
#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA   0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U
 
#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05   0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U
 
#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0   0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U
 
#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13   0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U
 
#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B   0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U
 
#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0   0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U
 
#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01   0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U
 
#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B   0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U
 
#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06   0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U
 
#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO   0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U
 
#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14   0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U
 
#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1   0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U
 
#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01   0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U
 
#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B   0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U
 
#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07   0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U
 
#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI   0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U
 
#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15   0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U
 
#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2   0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU
 
#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02   0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU
 
#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX   0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU
 
#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08   0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU
 
#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B   0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU
 
#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16   0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU
 
#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1   0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU
 
#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3   0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U
 
#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02   0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U
 
#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX   0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U
 
#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09   0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U
 
#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS   0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U
 
#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17   0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U
 
#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2   0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U
 
#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3   0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U
 
#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03   0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U
 
#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03   0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U
 
#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03   0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U
 
#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX   0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U
 
#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00   0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U
 
#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2   0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U
 
#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02   0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U
 
#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03   0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U
 
#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02   0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U
 
#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX   0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U
 
#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01   0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U
 
#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1   0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU
 
#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01   0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU
 
#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03   0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU
 
#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01   0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU
 
#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX   0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU
 
#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02   0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU
 
#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT   0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU
 
#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0   0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U
 
#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00   0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U
 
#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03   0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U
 
#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK   0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U
 
#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX   0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U
 
#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03   0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U
 
#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY   0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U
 
#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK   0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U
 
#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK   0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U
 
#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL   0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U
 
#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC   0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U
 
#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B   0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U
 
#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04   0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U
 
#define IOMUXC_GPIO_SD_B1_04_CCM_STOP   0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U
 
#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD   0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U
 
#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS   0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U
 
#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA   0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U
 
#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK   0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U
 
#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B   0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U
 
#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05   0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U
 
#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B   0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU
 
#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B   0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU
 
#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B   0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU
 
#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00   0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU
 
#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0   0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU
 
#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06   0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU
 
#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01   0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U
 
#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK   0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U
 
#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B   0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U
 
#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00   0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U
 
#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK   0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U
 
#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07   0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U
 
#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4   0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U
 
#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00   0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U
 
#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX   0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U
 
#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK   0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U
 
#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0   0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U
 
#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08   0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U
 
#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02   0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U
 
#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5   0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U
 
#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01   0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U
 
#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX   0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U
 
#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC   0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U
 
#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI   0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U
 
#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09   0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U
 
#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6   0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU
 
#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02   0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU
 
#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX   0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU
 
#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA   0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU
 
#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2   0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU
 
#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10   0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU
 
#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7   0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U
 
#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03   0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U
 
#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX   0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U
 
#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL   0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U
 
#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3   0x401F8200U, 0x4U, 0, 0, 0x401F83F0U
 
#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11   0x401F8200U, 0x5U, 0, 0, 0x401F83F0U
 
#define IOMUXC_GPR_SAIMCLK_LOWBITMASK   (0x7U)
 
#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK   (0x3U)
 

Configuration

static void IOMUXC_SetPinMux (uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)
 Sets the IOMUXC pin mux mode. More...
 
static void IOMUXC_SetPinConfig (uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)
 Sets the IOMUXC pin configuration. More...
 
static void IOMUXC_EnableMode (IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
 Sets IOMUXC general configuration for some mode. More...
 
static void IOMUXC_SetSaiMClkClockSource (IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)
 Sets IOMUXC general configuration for SAI MCLK selection. More...
 
static void IOMUXC_MQSEnterSoftwareReset (IOMUXC_GPR_Type *base, bool enable)
 Enters or exit MQS software reset. More...
 
static void IOMUXC_MQSEnable (IOMUXC_GPR_Type *base, bool enable)
 Enables or disables MQS. More...
 
static void IOMUXC_MQSConfig (IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
 Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. More...
 

Detailed Description

Macro Definition Documentation

◆ FSL_COMPONENT_ID

#define FSL_COMPONENT_ID   "platform.drivers.iomuxc"

Definition at line 26 of file fsl_iomuxc.h.

◆ FSL_IOMUXC_DRIVER_VERSION

#define FSL_IOMUXC_DRIVER_VERSION   (MAKE_VERSION(2, 0, 1))

IOMUXC driver version 2.0.1.

Definition at line 32 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03

#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03   0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU

Definition at line 359 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_GPIO1_IO00

#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00   0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU

Definition at line 364 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS

#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS   0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU

Definition at line 363 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK

#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK   0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU

Definition at line 366 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_REF_CLK_32K

#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K   0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU

Definition at line 361 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID

#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID   0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU

Definition at line 362 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B

#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B   0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU

Definition at line 365 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14

#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14   0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU

Definition at line 360 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_EWM_OUT_B

#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B   0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U

Definition at line 374 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03

#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03   0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U

Definition at line 368 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_GPIO1_IO01

#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01   0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U

Definition at line 373 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS

#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS   0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U

Definition at line 372 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO

#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO   0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U

Definition at line 375 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_REF_CLK_24M

#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M   0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U

Definition at line 370 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID

#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID   0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U

Definition at line 371 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15

#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15   0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U

Definition at line 369 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX

#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX   0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U

Definition at line 377 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00

#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00   0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U

Definition at line 381 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_GPIO1_IO02

#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02   0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U

Definition at line 382 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ

#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ   0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U

Definition at line 383 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI

#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI   0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U

Definition at line 384 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_LPUART6_TX

#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX   0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U

Definition at line 379 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR

#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR   0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U

Definition at line 380 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16

#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16   0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U

Definition at line 378 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX

#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX   0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U

Definition at line 386 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01

#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01   0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U

Definition at line 390 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_GPIO1_IO03

#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03   0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U

Definition at line 391 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0

#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0   0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U

Definition at line 393 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_LPUART6_RX

#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX   0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U

Definition at line 388 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_REF_CLK_24M

#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M   0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U

Definition at line 392 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC

#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC   0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U

Definition at line 389 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17

#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17   0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U

Definition at line 387 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_CSI_DATA09

#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09   0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU

Definition at line 399 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03

#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03   0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU

Definition at line 397 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_GPIO1_IO04

#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04   0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU

Definition at line 400 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1

#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1   0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU

Definition at line 402 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_MQS_RIGHT

#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT   0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU

Definition at line 396 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00

#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00   0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU

Definition at line 401 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC

#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC   0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU

Definition at line 398 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00

#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00   0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU

Definition at line 395 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_CSI_DATA08

#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08   0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U

Definition at line 408 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02

#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02   0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U

Definition at line 406 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_GPIO1_IO05

#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05   0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U

Definition at line 409 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2

#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2   0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U

Definition at line 411 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_MQS_LEFT

#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT   0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U

Definition at line 405 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK

#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK   0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U

Definition at line 407 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01

#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01   0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U

Definition at line 404 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17

#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17   0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U

Definition at line 410 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_CSI_DATA07

#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07   0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U

Definition at line 417 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK

#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK   0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U

Definition at line 415 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_GPIO1_IO06

#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06   0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U

Definition at line 418 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1

#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1   0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U

Definition at line 414 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_JTAG_TMS

#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS   0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U

Definition at line 413 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3

#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3   0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U

Definition at line 420 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK

#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK   0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U

Definition at line 416 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18

#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18   0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U

Definition at line 419 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_CSI_DATA06

#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06   0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U

Definition at line 426 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT

#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT   0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U

Definition at line 429 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_ENET_TX_ER

#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER   0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U

Definition at line 424 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_GPIO1_IO07

#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07   0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U

Definition at line 427 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2

#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2   0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U

Definition at line 423 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_JTAG_TCK

#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK   0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U

Definition at line 422 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC

#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC   0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U

Definition at line 425 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19

#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19   0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U

Definition at line 428 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_CSI_DATA05

#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05   0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU

Definition at line 435 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN

#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN   0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU

Definition at line 438 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03

#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03   0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU

Definition at line 433 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_GPIO1_IO08

#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08   0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU

Definition at line 436 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3

#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3   0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU

Definition at line 432 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_JTAG_MOD

#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD   0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU

Definition at line 431 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA

#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA   0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU

Definition at line 434 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_08_XBAR1_IN20

#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20   0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU

Definition at line 437 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_CSI_DATA04

#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04   0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U

Definition at line 444 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02

#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02   0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U

Definition at line 442 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03

#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03   0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U

Definition at line 441 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_GPIO1_IO09

#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09   0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U

Definition at line 445 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_GPT2_CLK

#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK   0x401F80E0U, 0x7U, 0, 0, 0x401F82D0U

Definition at line 447 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_JTAG_TDI

#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI   0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U

Definition at line 440 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA

#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA   0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U

Definition at line 443 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_09_XBAR1_IN21

#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21   0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U

Definition at line 446 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_CSI_DATA03

#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03   0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U

Definition at line 453 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT

#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT   0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U

Definition at line 456 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_ENET_CRS

#define IOMUXC_GPIO_AD_B0_10_ENET_CRS   0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U

Definition at line 451 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03

#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03   0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U

Definition at line 450 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_GPIO1_IO10

#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10   0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U

Definition at line 454 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_JTAG_TDO

#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO   0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U

Definition at line 449 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_SAI2_MCLK

#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK   0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U

Definition at line 452 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_10_XBAR1_IN22

#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22   0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U

Definition at line 455 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_CSI_DATA02

#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02   0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U

Definition at line 462 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN

#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN   0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U

Definition at line 465 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_ENET_COL

#define IOMUXC_GPIO_AD_B0_11_ENET_COL   0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U

Definition at line 460 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03

#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03   0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U

Definition at line 459 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_GPIO1_IO11

#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11   0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U

Definition at line 463 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB

#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB   0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U

Definition at line 458 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B

#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B   0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U

Definition at line 461 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_11_XBAR1_IN23

#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23   0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U

Definition at line 464 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY

#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY   0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU

Definition at line 468 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT

#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT   0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU

Definition at line 473 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02

#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02   0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU

Definition at line 471 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_GPIO1_IO12

#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12   0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU

Definition at line 472 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL

#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL   0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU

Definition at line 467 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_LPUART1_TX

#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX   0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU

Definition at line 469 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI

#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI   0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU

Definition at line 474 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B

#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B   0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU

Definition at line 470 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN

#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN   0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U

Definition at line 482 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_EWM_OUT_B

#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B   0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U

Definition at line 479 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03

#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03   0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U

Definition at line 480 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_GPIO1_IO13

#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13   0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U

Definition at line 481 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_GPT1_CLK

#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK   0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U

Definition at line 477 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA

#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA   0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U

Definition at line 476 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_LPUART1_RX

#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX   0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U

Definition at line 478 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_13_REF_CLK_24M

#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M   0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U

Definition at line 483 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_14_CSI_VSYNC

#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC   0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U

Definition at line 489 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT

#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT   0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U

Definition at line 488 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX

#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX   0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U

Definition at line 491 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_14_GPIO1_IO14

#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14   0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U

Definition at line 490 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B

#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B   0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U

Definition at line 487 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC

#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC   0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U

Definition at line 485 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_14_XBAR1_IN24

#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24   0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U

Definition at line 486 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_CSI_HSYNC

#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC   0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U

Definition at line 497 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN

#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN   0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U

Definition at line 496 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX

#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX   0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U

Definition at line 499 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_GPIO1_IO15

#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15   0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U

Definition at line 498 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B

#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B   0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U

Definition at line 495 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR

#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR   0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U

Definition at line 493 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB

#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB   0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U

Definition at line 500 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B0_15_XBAR1_IN25

#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25   0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U

Definition at line 494 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_GPIO1_IO16

#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16   0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU

Definition at line 507 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_KPP_ROW07

#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07   0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU

Definition at line 509 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL

#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL   0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU

Definition at line 505 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B

#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B   0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU

Definition at line 504 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0

#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0   0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU

Definition at line 503 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID

#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID   0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU

Definition at line 502 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_USDHC1_WP

#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP   0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU

Definition at line 508 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_00_WDOG1_B

#define IOMUXC_GPIO_AD_B1_00_WDOG1_B   0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU

Definition at line 506 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY

#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY   0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U

Definition at line 515 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_GPIO1_IO17

#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17   0x401F8100U, 0x5U, 0, 0, 0x401F82F0U

Definition at line 516 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_KPP_COL07

#define IOMUXC_GPIO_AD_B1_01_KPP_COL07   0x401F8100U, 0x7U, 0, 0, 0x401F82F0U

Definition at line 518 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA

#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA   0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U

Definition at line 514 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B

#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B   0x401F8100U, 0x2U, 0, 0, 0x401F82F0U

Definition at line 513 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1

#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1   0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U

Definition at line 512 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR

#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR   0x401F8100U, 0x0U, 0, 0, 0x401F82F0U

Definition at line 511 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT

#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT   0x401F8100U, 0x6U, 0, 0, 0x401F82F0U

Definition at line 517 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT

#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT   0x401F8104U, 0x4U, 0, 0, 0x401F82F4U

Definition at line 524 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_GPIO1_IO18

#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18   0x401F8104U, 0x5U, 0, 0, 0x401F82F4U

Definition at line 525 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_KPP_ROW06

#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06   0x401F8104U, 0x7U, 0, 0, 0x401F82F4U

Definition at line 527 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_LPUART2_TX

#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX   0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U

Definition at line 522 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2

#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2   0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U

Definition at line 521 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_SPDIF_OUT

#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT   0x401F8104U, 0x3U, 0, 0, 0x401F82F4U

Definition at line 523 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID

#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID   0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U

Definition at line 520 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B

#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B   0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U

Definition at line 526 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN

#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN   0x401F8108U, 0x4U, 0, 0, 0x401F82F8U

Definition at line 533 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_GPIO1_IO19

#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19   0x401F8108U, 0x5U, 0, 0, 0x401F82F8U

Definition at line 534 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_KPP_COL06

#define IOMUXC_GPIO_AD_B1_03_KPP_COL06   0x401F8108U, 0x7U, 0, 0, 0x401F82F8U

Definition at line 536 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_LPUART2_RX

#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX   0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U

Definition at line 531 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3

#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3   0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U

Definition at line 530 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_SPDIF_IN

#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN   0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U

Definition at line 532 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC

#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC   0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U

Definition at line 529 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B

#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B   0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U

Definition at line 535 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK

#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK   0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU

Definition at line 542 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_ENET_MDC

#define IOMUXC_GPIO_AD_B1_04_ENET_MDC   0x401F810CU, 0x1U, 0, 0, 0x401F82FCU

Definition at line 539 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03

#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03   0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU

Definition at line 538 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_GPIO1_IO20

#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20   0x401F810CU, 0x5U, 0, 0, 0x401F82FCU

Definition at line 543 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_KPP_ROW05

#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05   0x401F810CU, 0x7U, 0, 0, 0x401F82FCU

Definition at line 545 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B

#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B   0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU

Definition at line 540 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK

#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK   0x401F810CU, 0x3U, 0, 0, 0x401F82FCU

Definition at line 541 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0

#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0   0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU

Definition at line 544 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_CSI_MCLK

#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK   0x401F8110U, 0x4U, 0, 0, 0x401F8300U

Definition at line 551 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_ENET_MDIO

#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO   0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U

Definition at line 548 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02

#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02   0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U

Definition at line 547 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_GPIO1_IO21

#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21   0x401F8110U, 0x5U, 0, 0, 0x401F8300U

Definition at line 552 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_KPP_COL05

#define IOMUXC_GPIO_AD_B1_05_KPP_COL05   0x401F8110U, 0x7U, 0, 0, 0x401F8300U

Definition at line 554 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B

#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B   0x401F8110U, 0x2U, 0, 0, 0x401F8300U

Definition at line 549 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_SPDIF_OUT

#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT   0x401F8110U, 0x3U, 0, 0, 0x401F8300U

Definition at line 550 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1

#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1   0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U

Definition at line 553 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_CSI_VSYNC

#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC   0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U

Definition at line 560 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01

#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01   0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U

Definition at line 556 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_GPIO1_IO22

#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22   0x401F8114U, 0x5U, 0, 0, 0x401F8304U

Definition at line 561 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_KPP_ROW04

#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04   0x401F8114U, 0x7U, 0, 0, 0x401F8304U

Definition at line 563 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA

#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA   0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U

Definition at line 557 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_LPUART3_TX

#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX   0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U

Definition at line 558 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK

#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK   0x401F8114U, 0x3U, 0, 0, 0x401F8304U

Definition at line 559 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2

#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2   0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U

Definition at line 562 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_CSI_HSYNC

#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC   0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U

Definition at line 569 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00

#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00   0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U

Definition at line 565 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_GPIO1_IO23

#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23   0x401F8118U, 0x5U, 0, 0, 0x401F8308U

Definition at line 570 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_KPP_COL04

#define IOMUXC_GPIO_AD_B1_07_KPP_COL04   0x401F8118U, 0x7U, 0, 0, 0x401F8308U

Definition at line 572 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL

#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL   0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U

Definition at line 566 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_LPUART3_RX

#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX   0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U

Definition at line 567 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK

#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK   0x401F8118U, 0x3U, 0, 0, 0x401F8308U

Definition at line 568 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3

#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3   0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U

Definition at line 571 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY

#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY   0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU

Definition at line 577 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_CSI_DATA09

#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09   0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU

Definition at line 578 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX

#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX   0x401F811CU, 0x2U, 0, 0, 0x401F830CU

Definition at line 576 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00

#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00   0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU

Definition at line 575 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B

#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B   0x401F811CU, 0x0U, 0, 0, 0x401F830CU

Definition at line 574 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_GPIO1_IO24

#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24   0x401F811CU, 0x5U, 0, 0, 0x401F830CU

Definition at line 579 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_KPP_ROW03

#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03   0x401F811CU, 0x7U, 0, 0, 0x401F830CU

Definition at line 581 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_08_USDHC2_CMD

#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD   0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU

Definition at line 580 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_CSI_DATA08

#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08   0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U

Definition at line 587 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX

#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX   0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U

Definition at line 585 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01

#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01   0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U

Definition at line 584 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS

#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS   0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U

Definition at line 583 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_GPIO1_IO25

#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25   0x401F8120U, 0x5U, 0, 0, 0x401F8310U

Definition at line 588 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_KPP_COL03

#define IOMUXC_GPIO_AD_B1_09_KPP_COL03   0x401F8120U, 0x7U, 0, 0, 0x401F8310U

Definition at line 590 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_SAI1_MCLK

#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK   0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U

Definition at line 586 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_09_USDHC2_CLK

#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK   0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U

Definition at line 589 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_CSI_DATA07

#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07   0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U

Definition at line 596 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03

#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03   0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U

Definition at line 592 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_GPIO1_IO26

#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26   0x401F8124U, 0x5U, 0, 0, 0x401F8314U

Definition at line 597 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_KPP_ROW02

#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02   0x401F8124U, 0x7U, 0, 0, 0x401F8314U

Definition at line 599 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_LPUART8_TX

#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX   0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U

Definition at line 594 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC

#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC   0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U

Definition at line 595 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_USDHC2_WP

#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP   0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U

Definition at line 598 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_10_WDOG1_B

#define IOMUXC_GPIO_AD_B1_10_WDOG1_B   0x401F8124U, 0x1U, 0, 0, 0x401F8314U

Definition at line 593 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_CSI_DATA06

#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06   0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U

Definition at line 605 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_EWM_OUT_B

#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B   0x401F8128U, 0x1U, 0, 0, 0x401F8318U

Definition at line 602 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02

#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02   0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U

Definition at line 601 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_GPIO1_IO27

#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27   0x401F8128U, 0x5U, 0, 0, 0x401F8318U

Definition at line 606 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_KPP_COL02

#define IOMUXC_GPIO_AD_B1_11_KPP_COL02   0x401F8128U, 0x7U, 0, 0, 0x401F8318U

Definition at line 608 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_LPUART8_RX

#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX   0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U

Definition at line 603 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK

#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK   0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U

Definition at line 604 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B

#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B   0x401F8128U, 0x6U, 0, 0, 0x401F8318U

Definition at line 607 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_ACMP_OUT00

#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00   0x401F812CU, 0x1U, 0, 0, 0x401F831CU

Definition at line 611 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_CSI_DATA05

#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05   0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU

Definition at line 614 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01

#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01   0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU

Definition at line 610 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_GPIO1_IO28

#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28   0x401F812CU, 0x5U, 0, 0, 0x401F831CU

Definition at line 615 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_KPP_ROW01

#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01   0x401F812CU, 0x7U, 0, 0, 0x401F831CU

Definition at line 617 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0

#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0   0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU

Definition at line 612 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00

#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00   0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU

Definition at line 613 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4

#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4   0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU

Definition at line 616 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_ACMP_OUT01

#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01   0x401F8130U, 0x1U, 0, 0, 0x401F8320U

Definition at line 620 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_CSI_DATA04

#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04   0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U

Definition at line 623 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00

#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00   0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U

Definition at line 619 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_GPIO1_IO29

#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29   0x401F8130U, 0x5U, 0, 0, 0x401F8320U

Definition at line 624 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_KPP_COL01

#define IOMUXC_GPIO_AD_B1_13_KPP_COL01   0x401F8130U, 0x7U, 0, 0, 0x401F8320U

Definition at line 626 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI

#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI   0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U

Definition at line 621 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00

#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00   0x401F8130U, 0x3U, 0, 0, 0x401F8320U

Definition at line 622 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5

#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5   0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U

Definition at line 625 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_ACMP_OUT02

#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02   0x401F8134U, 0x1U, 0, 0, 0x401F8324U

Definition at line 629 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_CSI_DATA03

#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03   0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U

Definition at line 632 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK

#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK   0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U

Definition at line 628 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_GPIO1_IO30

#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30   0x401F8134U, 0x5U, 0, 0, 0x401F8324U

Definition at line 633 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_KPP_ROW00

#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00   0x401F8134U, 0x7U, 0, 0, 0x401F8324U

Definition at line 635 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO

#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO   0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U

Definition at line 630 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK

#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK   0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U

Definition at line 631 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6

#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6   0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U

Definition at line 634 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_ACMP_OUT03

#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03   0x401F8138U, 0x1U, 0, 0, 0x401F8328U

Definition at line 638 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_CSI_DATA02

#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02   0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U

Definition at line 641 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B

#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B   0x401F8138U, 0x0U, 0, 0, 0x401F8328U

Definition at line 637 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_GPIO1_IO31

#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31   0x401F8138U, 0x5U, 0, 0, 0x401F8328U

Definition at line 642 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_KPP_COL00

#define IOMUXC_GPIO_AD_B1_15_KPP_COL00   0x401F8138U, 0x7U, 0, 0, 0x401F8328U

Definition at line 644 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK

#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK   0x401F8138U, 0x2U, 0, 0, 0x401F8328U

Definition at line 639 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC

#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC   0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U

Definition at line 640 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7

#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7   0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U

Definition at line 643 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00

#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00   0x401F813CU, 0x4U, 0, 0, 0x401F832CU

Definition at line 650 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_00_GPIO2_IO00

#define IOMUXC_GPIO_B0_00_GPIO2_IO00   0x401F813CU, 0x5U, 0, 0, 0x401F832CU

Definition at line 651 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_00_LCD_CLK

#define IOMUXC_GPIO_B0_00_LCD_CLK   0x401F813CU, 0x0U, 0, 0, 0x401F832CU

Definition at line 646 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_00_LPSPI4_PCS0

#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0   0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU

Definition at line 649 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_00_MQS_RIGHT

#define IOMUXC_GPIO_B0_00_MQS_RIGHT   0x401F813CU, 0x2U, 0, 0, 0x401F832CU

Definition at line 648 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_00_QTIMER1_TIMER0

#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0   0x401F813CU, 0x1U, 0, 0, 0x401F832CU

Definition at line 647 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_00_SEMC_CSX01

#define IOMUXC_GPIO_B0_00_SEMC_CSX01   0x401F813CU, 0x6U, 0, 0, 0x401F832CU

Definition at line 652 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01

#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01   0x401F8140U, 0x4U, 0, 0, 0x401F8330U

Definition at line 658 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_01_GPIO2_IO01

#define IOMUXC_GPIO_B0_01_GPIO2_IO01   0x401F8140U, 0x5U, 0, 0, 0x401F8330U

Definition at line 659 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_01_LCD_ENABLE

#define IOMUXC_GPIO_B0_01_LCD_ENABLE   0x401F8140U, 0x0U, 0, 0, 0x401F8330U

Definition at line 654 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_01_LPSPI4_SDI

#define IOMUXC_GPIO_B0_01_LPSPI4_SDI   0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U

Definition at line 657 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_01_MQS_LEFT

#define IOMUXC_GPIO_B0_01_MQS_LEFT   0x401F8140U, 0x2U, 0, 0, 0x401F8330U

Definition at line 656 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_01_QTIMER1_TIMER1

#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1   0x401F8140U, 0x1U, 0, 0, 0x401F8330U

Definition at line 655 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_01_SEMC_CSX02

#define IOMUXC_GPIO_B0_01_SEMC_CSX02   0x401F8140U, 0x6U, 0, 0, 0x401F8330U

Definition at line 660 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_02_FLEXCAN1_TX

#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX   0x401F8144U, 0x2U, 0, 0, 0x401F8334U

Definition at line 664 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02

#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02   0x401F8144U, 0x4U, 0, 0, 0x401F8334U

Definition at line 666 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_02_GPIO2_IO02

#define IOMUXC_GPIO_B0_02_GPIO2_IO02   0x401F8144U, 0x5U, 0, 0, 0x401F8334U

Definition at line 667 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_02_LCD_HSYNC

#define IOMUXC_GPIO_B0_02_LCD_HSYNC   0x401F8144U, 0x0U, 0, 0, 0x401F8334U

Definition at line 662 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_02_LPSPI4_SDO

#define IOMUXC_GPIO_B0_02_LPSPI4_SDO   0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U

Definition at line 665 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_02_QTIMER1_TIMER2

#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2   0x401F8144U, 0x1U, 0, 0, 0x401F8334U

Definition at line 663 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_02_SEMC_CSX03

#define IOMUXC_GPIO_B0_02_SEMC_CSX03   0x401F8144U, 0x6U, 0, 0, 0x401F8334U

Definition at line 668 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_03_FLEXCAN1_RX

#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX   0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U

Definition at line 672 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03

#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03   0x401F8148U, 0x4U, 0, 0, 0x401F8338U

Definition at line 674 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_03_GPIO2_IO03

#define IOMUXC_GPIO_B0_03_GPIO2_IO03   0x401F8148U, 0x5U, 0, 0, 0x401F8338U

Definition at line 675 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_03_LCD_VSYNC

#define IOMUXC_GPIO_B0_03_LCD_VSYNC   0x401F8148U, 0x0U, 0, 0, 0x401F8338U

Definition at line 670 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_03_LPSPI4_SCK

#define IOMUXC_GPIO_B0_03_LPSPI4_SCK   0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U

Definition at line 673 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_03_QTIMER2_TIMER0

#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0   0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U

Definition at line 671 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB

#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB   0x401F8148U, 0x6U, 0, 0, 0x401F8338U

Definition at line 676 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00

#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00   0x401F814CU, 0x3U, 0, 0, 0x401F833CU

Definition at line 681 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04

#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04   0x401F814CU, 0x4U, 0, 0, 0x401F833CU

Definition at line 682 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_04_GPIO2_IO04

#define IOMUXC_GPIO_B0_04_GPIO2_IO04   0x401F814CU, 0x5U, 0, 0, 0x401F833CU

Definition at line 683 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_04_LCD_DATA00

#define IOMUXC_GPIO_B0_04_LCD_DATA00   0x401F814CU, 0x0U, 0, 0, 0x401F833CU

Definition at line 678 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_04_LPI2C2_SCL

#define IOMUXC_GPIO_B0_04_LPI2C2_SCL   0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU

Definition at line 680 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_04_QTIMER2_TIMER1

#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1   0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU

Definition at line 679 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00

#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00   0x401F814CU, 0x6U, 0, 0, 0x401F833CU

Definition at line 684 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01

#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01   0x401F8150U, 0x3U, 0, 0, 0x401F8340U

Definition at line 689 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05

#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05   0x401F8150U, 0x4U, 0, 0, 0x401F8340U

Definition at line 690 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_05_GPIO2_IO05

#define IOMUXC_GPIO_B0_05_GPIO2_IO05   0x401F8150U, 0x5U, 0, 0, 0x401F8340U

Definition at line 691 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_05_LCD_DATA01

#define IOMUXC_GPIO_B0_05_LCD_DATA01   0x401F8150U, 0x0U, 0, 0, 0x401F8340U

Definition at line 686 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_05_LPI2C2_SDA

#define IOMUXC_GPIO_B0_05_LPI2C2_SDA   0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U

Definition at line 688 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_05_QTIMER2_TIMER2

#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2   0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U

Definition at line 687 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01

#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01   0x401F8150U, 0x6U, 0, 0, 0x401F8340U

Definition at line 692 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02

#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02   0x401F8154U, 0x3U, 0, 0, 0x401F8344U

Definition at line 697 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06

#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06   0x401F8154U, 0x4U, 0, 0, 0x401F8344U

Definition at line 698 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00

#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00   0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U

Definition at line 696 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_06_GPIO2_IO06

#define IOMUXC_GPIO_B0_06_GPIO2_IO06   0x401F8154U, 0x5U, 0, 0, 0x401F8344U

Definition at line 699 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_06_LCD_DATA02

#define IOMUXC_GPIO_B0_06_LCD_DATA02   0x401F8154U, 0x0U, 0, 0, 0x401F8344U

Definition at line 694 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_06_QTIMER3_TIMER0

#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0   0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U

Definition at line 695 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02

#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02   0x401F8154U, 0x6U, 0, 0, 0x401F8344U

Definition at line 700 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03

#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03   0x401F8158U, 0x3U, 0, 0, 0x401F8348U

Definition at line 705 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07

#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07   0x401F8158U, 0x4U, 0, 0, 0x401F8348U

Definition at line 706 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00

#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00   0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U

Definition at line 704 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_07_GPIO2_IO07

#define IOMUXC_GPIO_B0_07_GPIO2_IO07   0x401F8158U, 0x5U, 0, 0, 0x401F8348U

Definition at line 707 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_07_LCD_DATA03

#define IOMUXC_GPIO_B0_07_LCD_DATA03   0x401F8158U, 0x0U, 0, 0, 0x401F8348U

Definition at line 702 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_07_QTIMER3_TIMER1

#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1   0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U

Definition at line 703 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03

#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03   0x401F8158U, 0x6U, 0, 0, 0x401F8348U

Definition at line 708 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08

#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08   0x401F815CU, 0x4U, 0, 0, 0x401F834CU

Definition at line 714 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01

#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01   0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU

Definition at line 712 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_08_GPIO2_IO08

#define IOMUXC_GPIO_B0_08_GPIO2_IO08   0x401F815CU, 0x5U, 0, 0, 0x401F834CU

Definition at line 715 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_08_LCD_DATA04

#define IOMUXC_GPIO_B0_08_LCD_DATA04   0x401F815CU, 0x0U, 0, 0, 0x401F834CU

Definition at line 710 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_08_LPUART3_TX

#define IOMUXC_GPIO_B0_08_LPUART3_TX   0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU

Definition at line 713 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_08_QTIMER3_TIMER2

#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2   0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU

Definition at line 711 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04

#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04   0x401F815CU, 0x6U, 0, 0, 0x401F834CU

Definition at line 716 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09

#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09   0x401F8160U, 0x4U, 0, 0, 0x401F8350U

Definition at line 722 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01

#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01   0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U

Definition at line 720 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_09_GPIO2_IO09

#define IOMUXC_GPIO_B0_09_GPIO2_IO09   0x401F8160U, 0x5U, 0, 0, 0x401F8350U

Definition at line 723 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_09_LCD_DATA05

#define IOMUXC_GPIO_B0_09_LCD_DATA05   0x401F8160U, 0x0U, 0, 0, 0x401F8350U

Definition at line 718 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_09_LPUART3_RX

#define IOMUXC_GPIO_B0_09_LPUART3_RX   0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U

Definition at line 721 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_09_QTIMER4_TIMER0

#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0   0x401F8160U, 0x1U, 0, 0, 0x401F8350U

Definition at line 719 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05

#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05   0x401F8160U, 0x6U, 0, 0, 0x401F8350U

Definition at line 724 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10

#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10   0x401F8164U, 0x4U, 0, 0, 0x401F8354U

Definition at line 730 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02

#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02   0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U

Definition at line 728 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_10_GPIO2_IO10

#define IOMUXC_GPIO_B0_10_GPIO2_IO10   0x401F8164U, 0x5U, 0, 0, 0x401F8354U

Definition at line 731 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_10_LCD_DATA06

#define IOMUXC_GPIO_B0_10_LCD_DATA06   0x401F8164U, 0x0U, 0, 0, 0x401F8354U

Definition at line 726 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_10_QTIMER4_TIMER1

#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1   0x401F8164U, 0x1U, 0, 0, 0x401F8354U

Definition at line 727 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_10_SAI1_TX_DATA03

#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03   0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U

Definition at line 729 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06

#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06   0x401F8164U, 0x6U, 0, 0, 0x401F8354U

Definition at line 732 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11

#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11   0x401F8168U, 0x4U, 0, 0, 0x401F8358U

Definition at line 738 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02

#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02   0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U

Definition at line 736 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_11_GPIO2_IO11

#define IOMUXC_GPIO_B0_11_GPIO2_IO11   0x401F8168U, 0x5U, 0, 0, 0x401F8358U

Definition at line 739 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_11_LCD_DATA07

#define IOMUXC_GPIO_B0_11_LCD_DATA07   0x401F8168U, 0x0U, 0, 0, 0x401F8358U

Definition at line 734 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_11_QTIMER4_TIMER2

#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2   0x401F8168U, 0x1U, 0, 0, 0x401F8358U

Definition at line 735 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_11_SAI1_TX_DATA02

#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02   0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U

Definition at line 737 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07

#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07   0x401F8168U, 0x6U, 0, 0, 0x401F8358U

Definition at line 740 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK

#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK   0x401F816CU, 0x2U, 0, 0, 0x401F835CU

Definition at line 744 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12

#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12   0x401F816CU, 0x4U, 0, 0, 0x401F835CU

Definition at line 746 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_12_GPIO2_IO12

#define IOMUXC_GPIO_B0_12_GPIO2_IO12   0x401F816CU, 0x5U, 0, 0, 0x401F835CU

Definition at line 747 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_12_LCD_DATA08

#define IOMUXC_GPIO_B0_12_LCD_DATA08   0x401F816CU, 0x0U, 0, 0, 0x401F835CU

Definition at line 742 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_12_SAI1_TX_DATA01

#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01   0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU

Definition at line 745 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08

#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08   0x401F816CU, 0x6U, 0, 0, 0x401F835CU

Definition at line 748 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_12_XBAR1_INOUT10

#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10   0x401F816CU, 0x1U, 0, 0, 0x401F835CU

Definition at line 743 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO

#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO   0x401F8170U, 0x2U, 0, 0, 0x401F8360U

Definition at line 752 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13

#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13   0x401F8170U, 0x4U, 0, 0, 0x401F8360U

Definition at line 754 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_13_GPIO2_IO13

#define IOMUXC_GPIO_B0_13_GPIO2_IO13   0x401F8170U, 0x5U, 0, 0, 0x401F8360U

Definition at line 755 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_13_LCD_DATA09

#define IOMUXC_GPIO_B0_13_LCD_DATA09   0x401F8170U, 0x0U, 0, 0, 0x401F8360U

Definition at line 750 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_13_SAI1_MCLK

#define IOMUXC_GPIO_B0_13_SAI1_MCLK   0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U

Definition at line 753 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09

#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09   0x401F8170U, 0x6U, 0, 0, 0x401F8360U

Definition at line 756 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_13_XBAR1_INOUT11

#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11   0x401F8170U, 0x1U, 0, 0, 0x401F8360U

Definition at line 751 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_14_ARM_CM7_TXEV

#define IOMUXC_GPIO_B0_14_ARM_CM7_TXEV   0x401F8174U, 0x2U, 0, 0, 0x401F8364U

Definition at line 760 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14

#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14   0x401F8174U, 0x4U, 0, 0, 0x401F8364U

Definition at line 762 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_14_GPIO2_IO14

#define IOMUXC_GPIO_B0_14_GPIO2_IO14   0x401F8174U, 0x5U, 0, 0, 0x401F8364U

Definition at line 763 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_14_LCD_DATA10

#define IOMUXC_GPIO_B0_14_LCD_DATA10   0x401F8174U, 0x0U, 0, 0, 0x401F8364U

Definition at line 758 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_14_SAI1_RX_SYNC

#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC   0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U

Definition at line 761 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10

#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10   0x401F8174U, 0x6U, 0, 0, 0x401F8364U

Definition at line 764 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_14_XBAR1_INOUT12

#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12   0x401F8174U, 0x1U, 0, 0, 0x401F8364U

Definition at line 759 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_15_ARM_CM7_RXEV

#define IOMUXC_GPIO_B0_15_ARM_CM7_RXEV   0x401F8178U, 0x2U, 0, 0, 0x401F8368U

Definition at line 768 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15

#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15   0x401F8178U, 0x4U, 0, 0, 0x401F8368U

Definition at line 770 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_15_GPIO2_IO15

#define IOMUXC_GPIO_B0_15_GPIO2_IO15   0x401F8178U, 0x5U, 0, 0, 0x401F8368U

Definition at line 771 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_15_LCD_DATA11

#define IOMUXC_GPIO_B0_15_LCD_DATA11   0x401F8178U, 0x0U, 0, 0, 0x401F8368U

Definition at line 766 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_15_SAI1_RX_BCLK

#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK   0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U

Definition at line 769 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11

#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11   0x401F8178U, 0x6U, 0, 0, 0x401F8368U

Definition at line 772 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B0_15_XBAR1_INOUT13

#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13   0x401F8178U, 0x1U, 0, 0, 0x401F8368U

Definition at line 767 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16

#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16   0x401F817CU, 0x4U, 0, 0, 0x401F836CU

Definition at line 778 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03

#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03   0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU

Definition at line 780 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_00_GPIO2_IO16

#define IOMUXC_GPIO_B1_00_GPIO2_IO16   0x401F817CU, 0x5U, 0, 0, 0x401F836CU

Definition at line 779 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_00_LCD_DATA12

#define IOMUXC_GPIO_B1_00_LCD_DATA12   0x401F817CU, 0x0U, 0, 0, 0x401F836CU

Definition at line 774 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_00_LPUART4_TX

#define IOMUXC_GPIO_B1_00_LPUART4_TX   0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU

Definition at line 776 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_00_SAI1_RX_DATA00

#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00   0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU

Definition at line 777 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_00_XBAR1_INOUT14

#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14   0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU

Definition at line 775 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17

#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17   0x401F8180U, 0x4U, 0, 0, 0x401F8370U

Definition at line 786 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03

#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03   0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U

Definition at line 788 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_01_GPIO2_IO17

#define IOMUXC_GPIO_B1_01_GPIO2_IO17   0x401F8180U, 0x5U, 0, 0, 0x401F8370U

Definition at line 787 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_01_LCD_DATA13

#define IOMUXC_GPIO_B1_01_LCD_DATA13   0x401F8180U, 0x0U, 0, 0, 0x401F8370U

Definition at line 782 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_01_LPUART4_RX

#define IOMUXC_GPIO_B1_01_LPUART4_RX   0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U

Definition at line 784 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_01_SAI1_TX_DATA00

#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00   0x401F8180U, 0x3U, 0, 0, 0x401F8370U

Definition at line 785 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_01_XBAR1_INOUT15

#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15   0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U

Definition at line 783 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18

#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18   0x401F8184U, 0x4U, 0, 0, 0x401F8374U

Definition at line 794 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03

#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03   0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U

Definition at line 796 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_02_GPIO2_IO18

#define IOMUXC_GPIO_B1_02_GPIO2_IO18   0x401F8184U, 0x5U, 0, 0, 0x401F8374U

Definition at line 795 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_02_LCD_DATA14

#define IOMUXC_GPIO_B1_02_LCD_DATA14   0x401F8184U, 0x0U, 0, 0, 0x401F8374U

Definition at line 790 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_02_LPSPI4_PCS2

#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2   0x401F8184U, 0x2U, 0, 0, 0x401F8374U

Definition at line 792 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_02_SAI1_TX_BCLK

#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK   0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U

Definition at line 793 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_02_XBAR1_INOUT16

#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16   0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U

Definition at line 791 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19

#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19   0x401F8188U, 0x4U, 0, 0, 0x401F8378U

Definition at line 802 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03

#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03   0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U

Definition at line 804 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_03_GPIO2_IO19

#define IOMUXC_GPIO_B1_03_GPIO2_IO19   0x401F8188U, 0x5U, 0, 0, 0x401F8378U

Definition at line 803 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_03_LCD_DATA15

#define IOMUXC_GPIO_B1_03_LCD_DATA15   0x401F8188U, 0x0U, 0, 0, 0x401F8378U

Definition at line 798 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_03_LPSPI4_PCS1

#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1   0x401F8188U, 0x2U, 0, 0, 0x401F8378U

Definition at line 800 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_03_SAI1_TX_SYNC

#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC   0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U

Definition at line 801 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_03_XBAR1_INOUT17

#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17   0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U

Definition at line 799 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_04_CSI_DATA15

#define IOMUXC_GPIO_B1_04_CSI_DATA15   0x401F818CU, 0x2U, 0, 0, 0x401F837CU

Definition at line 808 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_04_ENET_RX_DATA00

#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00   0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU

Definition at line 809 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20

#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20   0x401F818CU, 0x4U, 0, 0, 0x401F837CU

Definition at line 810 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_04_GPIO2_IO20

#define IOMUXC_GPIO_B1_04_GPIO2_IO20   0x401F818CU, 0x5U, 0, 0, 0x401F837CU

Definition at line 811 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_04_LCD_DATA16

#define IOMUXC_GPIO_B1_04_LCD_DATA16   0x401F818CU, 0x0U, 0, 0, 0x401F837CU

Definition at line 806 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_04_LPSPI4_PCS0

#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0   0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU

Definition at line 807 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_05_CSI_DATA14

#define IOMUXC_GPIO_B1_05_CSI_DATA14   0x401F8190U, 0x2U, 0, 0, 0x401F8380U

Definition at line 815 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_05_ENET_RX_DATA01

#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01   0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U

Definition at line 816 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21

#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21   0x401F8190U, 0x4U, 0, 0, 0x401F8380U

Definition at line 817 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_05_GPIO2_IO21

#define IOMUXC_GPIO_B1_05_GPIO2_IO21   0x401F8190U, 0x5U, 0, 0, 0x401F8380U

Definition at line 818 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_05_LCD_DATA17

#define IOMUXC_GPIO_B1_05_LCD_DATA17   0x401F8190U, 0x0U, 0, 0, 0x401F8380U

Definition at line 813 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_05_LPSPI4_SDI

#define IOMUXC_GPIO_B1_05_LPSPI4_SDI   0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U

Definition at line 814 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_06_CSI_DATA13

#define IOMUXC_GPIO_B1_06_CSI_DATA13   0x401F8194U, 0x2U, 0, 0, 0x401F8384U

Definition at line 822 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_06_ENET_RX_EN

#define IOMUXC_GPIO_B1_06_ENET_RX_EN   0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U

Definition at line 823 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22

#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22   0x401F8194U, 0x4U, 0, 0, 0x401F8384U

Definition at line 824 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_06_GPIO2_IO22

#define IOMUXC_GPIO_B1_06_GPIO2_IO22   0x401F8194U, 0x5U, 0, 0, 0x401F8384U

Definition at line 825 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_06_LCD_DATA18

#define IOMUXC_GPIO_B1_06_LCD_DATA18   0x401F8194U, 0x0U, 0, 0, 0x401F8384U

Definition at line 820 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_06_LPSPI4_SDO

#define IOMUXC_GPIO_B1_06_LPSPI4_SDO   0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U

Definition at line 821 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_07_CSI_DATA12

#define IOMUXC_GPIO_B1_07_CSI_DATA12   0x401F8198U, 0x2U, 0, 0, 0x401F8388U

Definition at line 829 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_07_ENET_TX_DATA00

#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00   0x401F8198U, 0x3U, 0, 0, 0x401F8388U

Definition at line 830 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23

#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23   0x401F8198U, 0x4U, 0, 0, 0x401F8388U

Definition at line 831 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_07_GPIO2_IO23

#define IOMUXC_GPIO_B1_07_GPIO2_IO23   0x401F8198U, 0x5U, 0, 0, 0x401F8388U

Definition at line 832 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_07_LCD_DATA19

#define IOMUXC_GPIO_B1_07_LCD_DATA19   0x401F8198U, 0x0U, 0, 0, 0x401F8388U

Definition at line 827 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_07_LPSPI4_SCK

#define IOMUXC_GPIO_B1_07_LPSPI4_SCK   0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U

Definition at line 828 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_08_CSI_DATA11

#define IOMUXC_GPIO_B1_08_CSI_DATA11   0x401F819CU, 0x2U, 0, 0, 0x401F838CU

Definition at line 836 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_08_ENET_TX_DATA01

#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01   0x401F819CU, 0x3U, 0, 0, 0x401F838CU

Definition at line 837 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_08_FLEXCAN2_TX

#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX   0x401F819CU, 0x6U, 0, 0, 0x401F838CU

Definition at line 840 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24

#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24   0x401F819CU, 0x4U, 0, 0, 0x401F838CU

Definition at line 838 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_08_GPIO2_IO24

#define IOMUXC_GPIO_B1_08_GPIO2_IO24   0x401F819CU, 0x5U, 0, 0, 0x401F838CU

Definition at line 839 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_08_LCD_DATA20

#define IOMUXC_GPIO_B1_08_LCD_DATA20   0x401F819CU, 0x0U, 0, 0, 0x401F838CU

Definition at line 834 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_08_QTIMER1_TIMER3

#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3   0x401F819CU, 0x1U, 0, 0, 0x401F838CU

Definition at line 835 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_09_CSI_DATA10

#define IOMUXC_GPIO_B1_09_CSI_DATA10   0x401F81A0U, 0x2U, 0, 0, 0x401F8390U

Definition at line 844 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_09_ENET_TX_EN

#define IOMUXC_GPIO_B1_09_ENET_TX_EN   0x401F81A0U, 0x3U, 0, 0, 0x401F8390U

Definition at line 845 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_09_FLEXCAN2_RX

#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX   0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U

Definition at line 848 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25

#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25   0x401F81A0U, 0x4U, 0, 0, 0x401F8390U

Definition at line 846 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_09_GPIO2_IO25

#define IOMUXC_GPIO_B1_09_GPIO2_IO25   0x401F81A0U, 0x5U, 0, 0, 0x401F8390U

Definition at line 847 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_09_LCD_DATA21

#define IOMUXC_GPIO_B1_09_LCD_DATA21   0x401F81A0U, 0x0U, 0, 0, 0x401F8390U

Definition at line 842 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_09_QTIMER2_TIMER3

#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3   0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U

Definition at line 843 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_10_CSI_DATA00

#define IOMUXC_GPIO_B1_10_CSI_DATA00   0x401F81A4U, 0x2U, 0, 0, 0x401F8394U

Definition at line 852 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_10_ENET_REF_CLK

#define IOMUXC_GPIO_B1_10_ENET_REF_CLK   0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U

Definition at line 856 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_10_ENET_TX_CLK

#define IOMUXC_GPIO_B1_10_ENET_TX_CLK   0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U

Definition at line 853 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26

#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26   0x401F81A4U, 0x4U, 0, 0, 0x401F8394U

Definition at line 854 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_10_GPIO2_IO26

#define IOMUXC_GPIO_B1_10_GPIO2_IO26   0x401F81A4U, 0x5U, 0, 0, 0x401F8394U

Definition at line 855 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_10_LCD_DATA22

#define IOMUXC_GPIO_B1_10_LCD_DATA22   0x401F81A4U, 0x0U, 0, 0, 0x401F8394U

Definition at line 850 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_10_QTIMER3_TIMER3

#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3   0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U

Definition at line 851 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_11_CSI_DATA01

#define IOMUXC_GPIO_B1_11_CSI_DATA01   0x401F81A8U, 0x2U, 0, 0, 0x401F8398U

Definition at line 860 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_11_ENET_RX_ER

#define IOMUXC_GPIO_B1_11_ENET_RX_ER   0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U

Definition at line 861 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27

#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27   0x401F81A8U, 0x4U, 0, 0, 0x401F8398U

Definition at line 862 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_11_GPIO2_IO27

#define IOMUXC_GPIO_B1_11_GPIO2_IO27   0x401F81A8U, 0x5U, 0, 0, 0x401F8398U

Definition at line 863 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_11_LCD_DATA23

#define IOMUXC_GPIO_B1_11_LCD_DATA23   0x401F81A8U, 0x0U, 0, 0, 0x401F8398U

Definition at line 858 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_11_LPSPI4_PCS3

#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3   0x401F81A8U, 0x6U, 0, 0, 0x401F8398U

Definition at line 864 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_11_QTIMER4_TIMER3

#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3   0x401F81A8U, 0x1U, 0, 0, 0x401F8398U

Definition at line 859 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_12_CSI_PIXCLK

#define IOMUXC_GPIO_B1_12_CSI_PIXCLK   0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU

Definition at line 867 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN

#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN   0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU

Definition at line 868 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28

#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28   0x401F81ACU, 0x4U, 0, 0, 0x401F839CU

Definition at line 869 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_12_GPIO2_IO28

#define IOMUXC_GPIO_B1_12_GPIO2_IO28   0x401F81ACU, 0x5U, 0, 0, 0x401F839CU

Definition at line 870 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_12_LPUART5_TX

#define IOMUXC_GPIO_B1_12_LPUART5_TX   0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU

Definition at line 866 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_12_USDHC1_CD_B

#define IOMUXC_GPIO_B1_12_USDHC1_CD_B   0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU

Definition at line 871 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_13_CSI_VSYNC

#define IOMUXC_GPIO_B1_13_CSI_VSYNC   0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U

Definition at line 875 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT

#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT   0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U

Definition at line 876 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29

#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29   0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U

Definition at line 877 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_13_GPIO2_IO29

#define IOMUXC_GPIO_B1_13_GPIO2_IO29   0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U

Definition at line 878 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_13_LPUART5_RX

#define IOMUXC_GPIO_B1_13_LPUART5_RX   0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U

Definition at line 874 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_13_USDHC1_WP

#define IOMUXC_GPIO_B1_13_USDHC1_WP   0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U

Definition at line 879 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_13_WDOG1_B

#define IOMUXC_GPIO_B1_13_WDOG1_B   0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U

Definition at line 873 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_14_CSI_HSYNC

#define IOMUXC_GPIO_B1_14_CSI_HSYNC   0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U

Definition at line 883 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_14_ENET_MDC

#define IOMUXC_GPIO_B1_14_ENET_MDC   0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U

Definition at line 881 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30

#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30   0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U

Definition at line 885 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02

#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02   0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U

Definition at line 882 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_14_GPIO2_IO30

#define IOMUXC_GPIO_B1_14_GPIO2_IO30   0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U

Definition at line 886 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_14_USDHC1_VSELECT

#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT   0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U

Definition at line 887 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_14_XBAR1_IN02

#define IOMUXC_GPIO_B1_14_XBAR1_IN02   0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U

Definition at line 884 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_15_CSI_MCLK

#define IOMUXC_GPIO_B1_15_CSI_MCLK   0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U

Definition at line 891 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_15_ENET_MDIO

#define IOMUXC_GPIO_B1_15_ENET_MDIO   0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U

Definition at line 889 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31

#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31   0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U

Definition at line 893 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03

#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03   0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U

Definition at line 890 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_15_GPIO2_IO31

#define IOMUXC_GPIO_B1_15_GPIO2_IO31   0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U

Definition at line 894 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_15_USDHC1_RESET_B

#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B   0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U

Definition at line 895 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_B1_15_XBAR1_IN03

#define IOMUXC_GPIO_B1_15_XBAR1_IN03   0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U

Definition at line 892 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00

#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00   0x401F8014U, 0x4U, 0, 0, 0x401F8204U

Definition at line 60 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00

#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00   0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U

Definition at line 57 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_00_GPIO4_IO00

#define IOMUXC_GPIO_EMC_00_GPIO4_IO00   0x401F8014U, 0x5U, 0, 0, 0x401F8204U

Definition at line 61 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_00_LPSPI2_SCK

#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK   0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U

Definition at line 58 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_00_SEMC_DATA00

#define IOMUXC_GPIO_EMC_00_SEMC_DATA00   0x401F8014U, 0x0U, 0, 0, 0x401F8204U

Definition at line 56 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02

#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02   0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U

Definition at line 59 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01

#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01   0x401F8018U, 0x4U, 0, 0, 0x401F8208U

Definition at line 67 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00

#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00   0x401F8018U, 0x1U, 0, 0, 0x401F8208U

Definition at line 64 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_01_GPIO4_IO01

#define IOMUXC_GPIO_EMC_01_GPIO4_IO01   0x401F8018U, 0x5U, 0, 0, 0x401F8208U

Definition at line 68 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_01_LPSPI2_PCS0

#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0   0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U

Definition at line 65 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_01_SEMC_DATA01

#define IOMUXC_GPIO_EMC_01_SEMC_DATA01   0x401F8018U, 0x0U, 0, 0, 0x401F8208U

Definition at line 63 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_01_XBAR1_IN03

#define IOMUXC_GPIO_EMC_01_XBAR1_IN03   0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U

Definition at line 66 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02

#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02   0x401F801CU, 0x4U, 0, 0, 0x401F820CU

Definition at line 74 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01

#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01   0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU

Definition at line 71 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_02_GPIO4_IO02

#define IOMUXC_GPIO_EMC_02_GPIO4_IO02   0x401F801CU, 0x5U, 0, 0, 0x401F820CU

Definition at line 75 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_02_LPSPI2_SDO

#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO   0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU

Definition at line 72 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_02_SEMC_DATA02

#define IOMUXC_GPIO_EMC_02_SEMC_DATA02   0x401F801CU, 0x0U, 0, 0, 0x401F820CU

Definition at line 70 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_02_XBAR1_INOUT04

#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04   0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU

Definition at line 73 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03

#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03   0x401F8020U, 0x4U, 0, 0, 0x401F8210U

Definition at line 81 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01

#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01   0x401F8020U, 0x1U, 0, 0, 0x401F8210U

Definition at line 78 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_03_GPIO4_IO03

#define IOMUXC_GPIO_EMC_03_GPIO4_IO03   0x401F8020U, 0x5U, 0, 0, 0x401F8210U

Definition at line 82 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_03_LPSPI2_SDI

#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI   0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U

Definition at line 79 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_03_SEMC_DATA03

#define IOMUXC_GPIO_EMC_03_SEMC_DATA03   0x401F8020U, 0x0U, 0, 0, 0x401F8210U

Definition at line 77 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_03_XBAR1_INOUT05

#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05   0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U

Definition at line 80 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04

#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04   0x401F8024U, 0x4U, 0, 0, 0x401F8214U

Definition at line 88 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02

#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02   0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U

Definition at line 85 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_04_GPIO4_IO04

#define IOMUXC_GPIO_EMC_04_GPIO4_IO04   0x401F8024U, 0x5U, 0, 0, 0x401F8214U

Definition at line 89 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_04_SAI2_TX_DATA

#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA   0x401F8024U, 0x2U, 0, 0, 0x401F8214U

Definition at line 86 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_04_SEMC_DATA04

#define IOMUXC_GPIO_EMC_04_SEMC_DATA04   0x401F8024U, 0x0U, 0, 0, 0x401F8214U

Definition at line 84 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_04_XBAR1_INOUT06

#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06   0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U

Definition at line 87 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05

#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05   0x401F8028U, 0x4U, 0, 0, 0x401F8218U

Definition at line 95 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02

#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02   0x401F8028U, 0x1U, 0, 0, 0x401F8218U

Definition at line 92 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_05_GPIO4_IO05

#define IOMUXC_GPIO_EMC_05_GPIO4_IO05   0x401F8028U, 0x5U, 0, 0, 0x401F8218U

Definition at line 96 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC

#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC   0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U

Definition at line 93 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_05_SEMC_DATA05

#define IOMUXC_GPIO_EMC_05_SEMC_DATA05   0x401F8028U, 0x0U, 0, 0, 0x401F8218U

Definition at line 91 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_05_XBAR1_INOUT07

#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07   0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U

Definition at line 94 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06

#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06   0x401F802CU, 0x4U, 0, 0, 0x401F821CU

Definition at line 102 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00

#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00   0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU

Definition at line 99 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_06_GPIO4_IO06

#define IOMUXC_GPIO_EMC_06_GPIO4_IO06   0x401F802CU, 0x5U, 0, 0, 0x401F821CU

Definition at line 103 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK

#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK   0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU

Definition at line 100 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_06_SEMC_DATA06

#define IOMUXC_GPIO_EMC_06_SEMC_DATA06   0x401F802CU, 0x0U, 0, 0, 0x401F821CU

Definition at line 98 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_06_XBAR1_INOUT08

#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08   0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU

Definition at line 101 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07

#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07   0x401F8030U, 0x4U, 0, 0, 0x401F8220U

Definition at line 109 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00

#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00   0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U

Definition at line 106 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_07_GPIO4_IO07

#define IOMUXC_GPIO_EMC_07_GPIO4_IO07   0x401F8030U, 0x5U, 0, 0, 0x401F8220U

Definition at line 110 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_07_SAI2_MCLK

#define IOMUXC_GPIO_EMC_07_SAI2_MCLK   0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U

Definition at line 107 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_07_SEMC_DATA07

#define IOMUXC_GPIO_EMC_07_SEMC_DATA07   0x401F8030U, 0x0U, 0, 0, 0x401F8220U

Definition at line 105 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_07_XBAR1_INOUT09

#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09   0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U

Definition at line 108 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08

#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08   0x401F8034U, 0x4U, 0, 0, 0x401F8224U

Definition at line 116 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01

#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01   0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U

Definition at line 113 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_08_GPIO4_IO08

#define IOMUXC_GPIO_EMC_08_GPIO4_IO08   0x401F8034U, 0x5U, 0, 0, 0x401F8224U

Definition at line 117 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_08_SAI2_RX_DATA

#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA   0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U

Definition at line 114 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_08_SEMC_DM00

#define IOMUXC_GPIO_EMC_08_SEMC_DM00   0x401F8034U, 0x0U, 0, 0, 0x401F8224U

Definition at line 112 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_08_XBAR1_INOUT17

#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17   0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U

Definition at line 115 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_09_FLEXCAN2_TX

#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX   0x401F8038U, 0x3U, 0, 0, 0x401F8228U

Definition at line 122 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09

#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09   0x401F8038U, 0x4U, 0, 0, 0x401F8228U

Definition at line 123 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01

#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01   0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U

Definition at line 120 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_09_GPIO4_IO09

#define IOMUXC_GPIO_EMC_09_GPIO4_IO09   0x401F8038U, 0x5U, 0, 0, 0x401F8228U

Definition at line 124 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC

#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC   0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U

Definition at line 121 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_09_SEMC_ADDR00

#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00   0x401F8038U, 0x0U, 0, 0, 0x401F8228U

Definition at line 119 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_10_FLEXCAN2_RX

#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX   0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU

Definition at line 129 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10

#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10   0x401F803CU, 0x4U, 0, 0, 0x401F822CU

Definition at line 130 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02

#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02   0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU

Definition at line 127 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_10_GPIO4_IO10

#define IOMUXC_GPIO_EMC_10_GPIO4_IO10   0x401F803CU, 0x5U, 0, 0, 0x401F822CU

Definition at line 131 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK

#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK   0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU

Definition at line 128 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_10_SEMC_ADDR01

#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01   0x401F803CU, 0x0U, 0, 0, 0x401F822CU

Definition at line 126 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11

#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11   0x401F8040U, 0x4U, 0, 0, 0x401F8230U

Definition at line 137 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02

#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02   0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U

Definition at line 134 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_11_GPIO4_IO11

#define IOMUXC_GPIO_EMC_11_GPIO4_IO11   0x401F8040U, 0x5U, 0, 0, 0x401F8230U

Definition at line 138 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_11_LPI2C4_SDA

#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA   0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U

Definition at line 135 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_11_SEMC_ADDR02

#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02   0x401F8040U, 0x0U, 0, 0, 0x401F8230U

Definition at line 133 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_11_USDHC2_RESET_B

#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B   0x401F8040U, 0x3U, 0, 0, 0x401F8230U

Definition at line 136 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03

#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03   0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U

Definition at line 144 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_12_GPIO4_IO12

#define IOMUXC_GPIO_EMC_12_GPIO4_IO12   0x401F8044U, 0x5U, 0, 0, 0x401F8234U

Definition at line 145 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_12_LPI2C4_SCL

#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL   0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U

Definition at line 142 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_12_SEMC_ADDR03

#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03   0x401F8044U, 0x0U, 0, 0, 0x401F8234U

Definition at line 140 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_12_USDHC1_WP

#define IOMUXC_GPIO_EMC_12_USDHC1_WP   0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U

Definition at line 143 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_12_XBAR1_IN24

#define IOMUXC_GPIO_EMC_12_XBAR1_IN24   0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U

Definition at line 141 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03

#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03   0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U

Definition at line 151 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_13_GPIO4_IO13

#define IOMUXC_GPIO_EMC_13_GPIO4_IO13   0x401F8048U, 0x5U, 0, 0, 0x401F8238U

Definition at line 152 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_13_LPUART3_TX

#define IOMUXC_GPIO_EMC_13_LPUART3_TX   0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U

Definition at line 149 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_13_MQS_RIGHT

#define IOMUXC_GPIO_EMC_13_MQS_RIGHT   0x401F8048U, 0x3U, 0, 0, 0x401F8238U

Definition at line 150 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_13_SEMC_ADDR04

#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04   0x401F8048U, 0x0U, 0, 0, 0x401F8238U

Definition at line 147 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_13_XBAR1_IN25

#define IOMUXC_GPIO_EMC_13_XBAR1_IN25   0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U

Definition at line 148 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_14_GPIO4_IO14

#define IOMUXC_GPIO_EMC_14_GPIO4_IO14   0x401F804CU, 0x5U, 0, 0, 0x401F823CU

Definition at line 159 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_14_LPSPI2_PCS1

#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1   0x401F804CU, 0x4U, 0, 0, 0x401F823CU

Definition at line 158 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_14_LPUART3_RX

#define IOMUXC_GPIO_EMC_14_LPUART3_RX   0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU

Definition at line 156 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_14_MQS_LEFT

#define IOMUXC_GPIO_EMC_14_MQS_LEFT   0x401F804CU, 0x3U, 0, 0, 0x401F823CU

Definition at line 157 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_14_SEMC_ADDR05

#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05   0x401F804CU, 0x0U, 0, 0, 0x401F823CU

Definition at line 154 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_14_XBAR1_INOUT19

#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19   0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU

Definition at line 155 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_15_GPIO4_IO15

#define IOMUXC_GPIO_EMC_15_GPIO4_IO15   0x401F8050U, 0x5U, 0, 0, 0x401F8240U

Definition at line 166 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_15_LPUART3_CTS_B

#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B   0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U

Definition at line 163 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0

#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0   0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U

Definition at line 165 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_15_SEMC_ADDR06

#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06   0x401F8050U, 0x0U, 0, 0, 0x401F8240U

Definition at line 161 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_15_SPDIF_OUT

#define IOMUXC_GPIO_EMC_15_SPDIF_OUT   0x401F8050U, 0x3U, 0, 0, 0x401F8240U

Definition at line 164 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_15_XBAR1_IN20

#define IOMUXC_GPIO_EMC_15_XBAR1_IN20   0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U

Definition at line 162 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_16_GPIO4_IO16

#define IOMUXC_GPIO_EMC_16_GPIO4_IO16   0x401F8054U, 0x5U, 0, 0, 0x401F8244U

Definition at line 173 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_16_LPUART3_RTS_B

#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B   0x401F8054U, 0x2U, 0, 0, 0x401F8244U

Definition at line 170 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1

#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1   0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U

Definition at line 172 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_16_SEMC_ADDR07

#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07   0x401F8054U, 0x0U, 0, 0, 0x401F8244U

Definition at line 168 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_16_SPDIF_IN

#define IOMUXC_GPIO_EMC_16_SPDIF_IN   0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U

Definition at line 171 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_16_XBAR1_IN21

#define IOMUXC_GPIO_EMC_16_XBAR1_IN21   0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U

Definition at line 169 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_17_FLEXCAN1_TX

#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX   0x401F8058U, 0x3U, 0, 0, 0x401F8248U

Definition at line 178 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03

#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03   0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U

Definition at line 176 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_17_GPIO4_IO17

#define IOMUXC_GPIO_EMC_17_GPIO4_IO17   0x401F8058U, 0x5U, 0, 0, 0x401F8248U

Definition at line 180 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_17_LPUART4_CTS_B

#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B   0x401F8058U, 0x2U, 0, 0, 0x401F8248U

Definition at line 177 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2

#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2   0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U

Definition at line 179 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_17_SEMC_ADDR08

#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08   0x401F8058U, 0x0U, 0, 0, 0x401F8248U

Definition at line 175 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_18_FLEXCAN1_RX

#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX   0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU

Definition at line 185 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03

#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03   0x401F805CU, 0x1U, 0, 0, 0x401F824CU

Definition at line 183 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_18_GPIO4_IO18

#define IOMUXC_GPIO_EMC_18_GPIO4_IO18   0x401F805CU, 0x5U, 0, 0, 0x401F824CU

Definition at line 187 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_18_LPUART4_RTS_B

#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B   0x401F805CU, 0x2U, 0, 0, 0x401F824CU

Definition at line 184 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3

#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3   0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU

Definition at line 186 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_18_SEMC_ADDR09

#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09   0x401F805CU, 0x0U, 0, 0, 0x401F824CU

Definition at line 182 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL

#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL   0x401F805CU, 0x6U, 0, 0, 0x401F824CU

Definition at line 188 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_19_ENET_RDATA01

#define IOMUXC_GPIO_EMC_19_ENET_RDATA01   0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U

Definition at line 193 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03

#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03   0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U

Definition at line 191 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_19_GPIO4_IO19

#define IOMUXC_GPIO_EMC_19_GPIO4_IO19   0x401F8060U, 0x5U, 0, 0, 0x401F8250U

Definition at line 195 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_19_LPUART4_TX

#define IOMUXC_GPIO_EMC_19_LPUART4_TX   0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U

Definition at line 192 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0

#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0   0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U

Definition at line 194 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_19_SEMC_ADDR11

#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11   0x401F8060U, 0x0U, 0, 0, 0x401F8250U

Definition at line 190 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_19_SNVS_VIO_5

#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5   0x401F8060U, 0x6U, 0, 0, 0x401F8250U

Definition at line 196 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_20_ENET_RDATA00

#define IOMUXC_GPIO_EMC_20_ENET_RDATA00   0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U

Definition at line 201 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03

#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03   0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U

Definition at line 199 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_20_GPIO4_IO20

#define IOMUXC_GPIO_EMC_20_GPIO4_IO20   0x401F8064U, 0x5U, 0, 0, 0x401F8254U

Definition at line 203 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_20_LPUART4_RX

#define IOMUXC_GPIO_EMC_20_LPUART4_RX   0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U

Definition at line 200 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1

#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1   0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U

Definition at line 202 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_20_SEMC_ADDR12

#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12   0x401F8064U, 0x0U, 0, 0, 0x401F8254U

Definition at line 198 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_21_ENET_TDATA01

#define IOMUXC_GPIO_EMC_21_ENET_TDATA01   0x401F8068U, 0x3U, 0, 0, 0x401F8258U

Definition at line 208 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03

#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03   0x401F8068U, 0x1U, 0, 0, 0x401F8258U

Definition at line 206 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_21_GPIO4_IO21

#define IOMUXC_GPIO_EMC_21_GPIO4_IO21   0x401F8068U, 0x5U, 0, 0, 0x401F8258U

Definition at line 210 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_21_LPI2C3_SDA

#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA   0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U

Definition at line 207 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2

#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2   0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U

Definition at line 209 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_21_SEMC_BA0

#define IOMUXC_GPIO_EMC_21_SEMC_BA0   0x401F8068U, 0x0U, 0, 0, 0x401F8258U

Definition at line 205 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_22_ENET_TDATA00

#define IOMUXC_GPIO_EMC_22_ENET_TDATA00   0x401F806CU, 0x3U, 0, 0, 0x401F825CU

Definition at line 215 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03

#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03   0x401F806CU, 0x1U, 0, 0, 0x401F825CU

Definition at line 213 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_22_GPIO4_IO22

#define IOMUXC_GPIO_EMC_22_GPIO4_IO22   0x401F806CU, 0x5U, 0, 0, 0x401F825CU

Definition at line 217 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_22_LPI2C3_SCL

#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL   0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU

Definition at line 214 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3

#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3   0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU

Definition at line 216 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_22_SEMC_BA1

#define IOMUXC_GPIO_EMC_22_SEMC_BA1   0x401F806CU, 0x0U, 0, 0, 0x401F825CU

Definition at line 212 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_23_ENET_RX_EN

#define IOMUXC_GPIO_EMC_23_ENET_RX_EN   0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U

Definition at line 222 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00

#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00   0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U

Definition at line 220 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_23_GPIO4_IO23

#define IOMUXC_GPIO_EMC_23_GPIO4_IO23   0x401F8070U, 0x5U, 0, 0, 0x401F8260U

Definition at line 224 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2

#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2   0x401F8070U, 0x4U, 0, 0, 0x401F8260U

Definition at line 223 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_23_LPUART5_TX

#define IOMUXC_GPIO_EMC_23_LPUART5_TX   0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U

Definition at line 221 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_23_SEMC_ADDR10

#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10   0x401F8070U, 0x0U, 0, 0, 0x401F8260U

Definition at line 219 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_24_ENET_TX_EN

#define IOMUXC_GPIO_EMC_24_ENET_TX_EN   0x401F8074U, 0x3U, 0, 0, 0x401F8264U

Definition at line 229 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00

#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00   0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U

Definition at line 227 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_24_GPIO4_IO24

#define IOMUXC_GPIO_EMC_24_GPIO4_IO24   0x401F8074U, 0x5U, 0, 0, 0x401F8264U

Definition at line 231 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1

#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1   0x401F8074U, 0x4U, 0, 0, 0x401F8264U

Definition at line 230 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_24_LPUART5_RX

#define IOMUXC_GPIO_EMC_24_LPUART5_RX   0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U

Definition at line 228 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_24_SEMC_CAS

#define IOMUXC_GPIO_EMC_24_SEMC_CAS   0x401F8074U, 0x0U, 0, 0, 0x401F8264U

Definition at line 226 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_25_ENET_REF_CLK

#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK   0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U

Definition at line 237 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_25_ENET_TX_CLK

#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK   0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U

Definition at line 236 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01

#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01   0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U

Definition at line 234 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_25_GPIO4_IO25

#define IOMUXC_GPIO_EMC_25_GPIO4_IO25   0x401F8078U, 0x5U, 0, 0, 0x401F8268U

Definition at line 238 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_25_LPUART6_TX

#define IOMUXC_GPIO_EMC_25_LPUART6_TX   0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U

Definition at line 235 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_25_SEMC_RAS

#define IOMUXC_GPIO_EMC_25_SEMC_RAS   0x401F8078U, 0x0U, 0, 0, 0x401F8268U

Definition at line 233 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_26_ENET_RX_ER

#define IOMUXC_GPIO_EMC_26_ENET_RX_ER   0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU

Definition at line 243 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12

#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12   0x401F807CU, 0x4U, 0, 0, 0x401F826CU

Definition at line 244 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01

#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01   0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU

Definition at line 241 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_26_GPIO4_IO26

#define IOMUXC_GPIO_EMC_26_GPIO4_IO26   0x401F807CU, 0x5U, 0, 0, 0x401F826CU

Definition at line 245 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_26_LPUART6_RX

#define IOMUXC_GPIO_EMC_26_LPUART6_RX   0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU

Definition at line 242 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_26_SEMC_CLK

#define IOMUXC_GPIO_EMC_26_SEMC_CLK   0x401F807CU, 0x0U, 0, 0, 0x401F826CU

Definition at line 240 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13

#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13   0x401F8080U, 0x4U, 0, 0, 0x401F8270U

Definition at line 251 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02

#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02   0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U

Definition at line 248 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_27_GPIO4_IO27

#define IOMUXC_GPIO_EMC_27_GPIO4_IO27   0x401F8080U, 0x5U, 0, 0, 0x401F8270U

Definition at line 252 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_27_LPSPI1_SCK

#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK   0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U

Definition at line 250 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_27_LPUART5_RTS_B

#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B   0x401F8080U, 0x2U, 0, 0, 0x401F8270U

Definition at line 249 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_27_SEMC_CKE

#define IOMUXC_GPIO_EMC_27_SEMC_CKE   0x401F8080U, 0x0U, 0, 0, 0x401F8270U

Definition at line 247 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14

#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14   0x401F8084U, 0x4U, 0, 0, 0x401F8274U

Definition at line 258 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02

#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02   0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U

Definition at line 255 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_28_GPIO4_IO28

#define IOMUXC_GPIO_EMC_28_GPIO4_IO28   0x401F8084U, 0x5U, 0, 0, 0x401F8274U

Definition at line 259 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_28_LPSPI1_SDO

#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO   0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U

Definition at line 257 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_28_LPUART5_CTS_B

#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B   0x401F8084U, 0x2U, 0, 0, 0x401F8274U

Definition at line 256 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_28_SEMC_WE

#define IOMUXC_GPIO_EMC_28_SEMC_WE   0x401F8084U, 0x0U, 0, 0, 0x401F8274U

Definition at line 254 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15

#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15   0x401F8088U, 0x4U, 0, 0, 0x401F8278U

Definition at line 265 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00

#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00   0x401F8088U, 0x1U, 0, 0, 0x401F8278U

Definition at line 262 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_29_GPIO4_IO29

#define IOMUXC_GPIO_EMC_29_GPIO4_IO29   0x401F8088U, 0x5U, 0, 0, 0x401F8278U

Definition at line 266 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_29_LPSPI1_SDI

#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI   0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U

Definition at line 264 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_29_LPUART6_RTS_B

#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B   0x401F8088U, 0x2U, 0, 0, 0x401F8278U

Definition at line 263 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_29_SEMC_CS0

#define IOMUXC_GPIO_EMC_29_SEMC_CS0   0x401F8088U, 0x0U, 0, 0, 0x401F8278U

Definition at line 261 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_30_CSI_DATA23

#define IOMUXC_GPIO_EMC_30_CSI_DATA23   0x401F808CU, 0x4U, 0, 0, 0x401F827CU

Definition at line 272 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00

#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00   0x401F808CU, 0x1U, 0, 0, 0x401F827CU

Definition at line 269 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_30_GPIO4_IO30

#define IOMUXC_GPIO_EMC_30_GPIO4_IO30   0x401F808CU, 0x5U, 0, 0, 0x401F827CU

Definition at line 273 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_30_LPSPI1_PCS0

#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0   0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU

Definition at line 271 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_30_LPUART6_CTS_B

#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B   0x401F808CU, 0x2U, 0, 0, 0x401F827CU

Definition at line 270 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_30_SEMC_DATA08

#define IOMUXC_GPIO_EMC_30_SEMC_DATA08   0x401F808CU, 0x0U, 0, 0, 0x401F827CU

Definition at line 268 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_31_CSI_DATA22

#define IOMUXC_GPIO_EMC_31_CSI_DATA22   0x401F8090U, 0x4U, 0, 0, 0x401F8280U

Definition at line 279 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01

#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01   0x401F8090U, 0x1U, 0, 0, 0x401F8280U

Definition at line 276 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_31_GPIO4_IO31

#define IOMUXC_GPIO_EMC_31_GPIO4_IO31   0x401F8090U, 0x5U, 0, 0, 0x401F8280U

Definition at line 280 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_31_LPSPI1_PCS1

#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1   0x401F8090U, 0x3U, 0, 0, 0x401F8280U

Definition at line 278 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_31_LPUART7_TX

#define IOMUXC_GPIO_EMC_31_LPUART7_TX   0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U

Definition at line 277 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_31_SEMC_DATA09

#define IOMUXC_GPIO_EMC_31_SEMC_DATA09   0x401F8090U, 0x0U, 0, 0, 0x401F8280U

Definition at line 275 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY

#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY   0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U

Definition at line 285 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_32_CSI_DATA21

#define IOMUXC_GPIO_EMC_32_CSI_DATA21   0x401F8094U, 0x4U, 0, 0, 0x401F8284U

Definition at line 286 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01

#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01   0x401F8094U, 0x1U, 0, 0, 0x401F8284U

Definition at line 283 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_32_GPIO3_IO18

#define IOMUXC_GPIO_EMC_32_GPIO3_IO18   0x401F8094U, 0x5U, 0, 0, 0x401F8284U

Definition at line 287 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_32_LPUART7_RX

#define IOMUXC_GPIO_EMC_32_LPUART7_RX   0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U

Definition at line 284 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_32_SEMC_DATA10

#define IOMUXC_GPIO_EMC_32_SEMC_DATA10   0x401F8094U, 0x0U, 0, 0, 0x401F8284U

Definition at line 282 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_33_CSI_DATA20

#define IOMUXC_GPIO_EMC_33_CSI_DATA20   0x401F8098U, 0x4U, 0, 0, 0x401F8288U

Definition at line 293 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02

#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02   0x401F8098U, 0x1U, 0, 0, 0x401F8288U

Definition at line 290 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_33_GPIO3_IO19

#define IOMUXC_GPIO_EMC_33_GPIO3_IO19   0x401F8098U, 0x5U, 0, 0, 0x401F8288U

Definition at line 294 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_33_SAI3_RX_DATA

#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA   0x401F8098U, 0x3U, 0, 0, 0x401F8288U

Definition at line 292 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_33_SEMC_DATA11

#define IOMUXC_GPIO_EMC_33_SEMC_DATA11   0x401F8098U, 0x0U, 0, 0, 0x401F8288U

Definition at line 289 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_33_USDHC1_RESET_B

#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B   0x401F8098U, 0x2U, 0, 0, 0x401F8288U

Definition at line 291 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_34_CSI_DATA19

#define IOMUXC_GPIO_EMC_34_CSI_DATA19   0x401F809CU, 0x4U, 0, 0, 0x401F828CU

Definition at line 300 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02

#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02   0x401F809CU, 0x1U, 0, 0, 0x401F828CU

Definition at line 297 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_34_GPIO3_IO20

#define IOMUXC_GPIO_EMC_34_GPIO3_IO20   0x401F809CU, 0x5U, 0, 0, 0x401F828CU

Definition at line 301 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC

#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC   0x401F809CU, 0x3U, 0, 0, 0x401F828CU

Definition at line 299 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_34_SEMC_DATA12

#define IOMUXC_GPIO_EMC_34_SEMC_DATA12   0x401F809CU, 0x0U, 0, 0, 0x401F828CU

Definition at line 296 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_34_USDHC1_VSELECT

#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT   0x401F809CU, 0x2U, 0, 0, 0x401F828CU

Definition at line 298 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_35_CSI_DATA18

#define IOMUXC_GPIO_EMC_35_CSI_DATA18   0x401F80A0U, 0x4U, 0, 0, 0x401F8290U

Definition at line 307 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_35_GPIO3_IO21

#define IOMUXC_GPIO_EMC_35_GPIO3_IO21   0x401F80A0U, 0x5U, 0, 0, 0x401F8290U

Definition at line 308 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_35_GPT1_COMPARE1

#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1   0x401F80A0U, 0x2U, 0, 0, 0x401F8290U

Definition at line 305 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK

#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK   0x401F80A0U, 0x3U, 0, 0, 0x401F8290U

Definition at line 306 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_35_SEMC_DATA13

#define IOMUXC_GPIO_EMC_35_SEMC_DATA13   0x401F80A0U, 0x0U, 0, 0, 0x401F8290U

Definition at line 303 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_35_USDHC1_CD_B

#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B   0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U

Definition at line 309 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_35_XBAR1_INOUT18

#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18   0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U

Definition at line 304 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_36_CSI_DATA17

#define IOMUXC_GPIO_EMC_36_CSI_DATA17   0x401F80A4U, 0x4U, 0, 0, 0x401F8294U

Definition at line 315 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_36_GPIO3_IO22

#define IOMUXC_GPIO_EMC_36_GPIO3_IO22   0x401F80A4U, 0x5U, 0, 0, 0x401F8294U

Definition at line 316 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_36_GPT1_COMPARE2

#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2   0x401F80A4U, 0x2U, 0, 0, 0x401F8294U

Definition at line 313 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_36_SAI3_TX_DATA

#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA   0x401F80A4U, 0x3U, 0, 0, 0x401F8294U

Definition at line 314 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_36_SEMC_DATA14

#define IOMUXC_GPIO_EMC_36_SEMC_DATA14   0x401F80A4U, 0x0U, 0, 0, 0x401F8294U

Definition at line 311 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_36_USDHC1_WP

#define IOMUXC_GPIO_EMC_36_USDHC1_WP   0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U

Definition at line 317 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_36_XBAR1_IN22

#define IOMUXC_GPIO_EMC_36_XBAR1_IN22   0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U

Definition at line 312 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_37_CSI_DATA16

#define IOMUXC_GPIO_EMC_37_CSI_DATA16   0x401F80A8U, 0x4U, 0, 0, 0x401F8298U

Definition at line 323 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_37_GPIO3_IO23

#define IOMUXC_GPIO_EMC_37_GPIO3_IO23   0x401F80A8U, 0x5U, 0, 0, 0x401F8298U

Definition at line 324 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_37_GPT1_COMPARE3

#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3   0x401F80A8U, 0x2U, 0, 0, 0x401F8298U

Definition at line 321 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_37_SAI3_MCLK

#define IOMUXC_GPIO_EMC_37_SAI3_MCLK   0x401F80A8U, 0x3U, 0, 0, 0x401F8298U

Definition at line 322 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_37_SEMC_DATA15

#define IOMUXC_GPIO_EMC_37_SEMC_DATA15   0x401F80A8U, 0x0U, 0, 0, 0x401F8298U

Definition at line 319 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_37_USDHC2_WP

#define IOMUXC_GPIO_EMC_37_USDHC2_WP   0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U

Definition at line 325 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_37_XBAR1_IN23

#define IOMUXC_GPIO_EMC_37_XBAR1_IN23   0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U

Definition at line 320 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_38_CSI_FIELD

#define IOMUXC_GPIO_EMC_38_CSI_FIELD   0x401F80ACU, 0x4U, 0, 0, 0x401F829CU

Definition at line 331 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03

#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03   0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU

Definition at line 328 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_38_GPIO3_IO24

#define IOMUXC_GPIO_EMC_38_GPIO3_IO24   0x401F80ACU, 0x5U, 0, 0, 0x401F829CU

Definition at line 332 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_38_LPUART8_TX

#define IOMUXC_GPIO_EMC_38_LPUART8_TX   0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU

Definition at line 329 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK

#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK   0x401F80ACU, 0x3U, 0, 0, 0x401F829CU

Definition at line 330 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_38_SEMC_DM01

#define IOMUXC_GPIO_EMC_38_SEMC_DM01   0x401F80ACU, 0x0U, 0, 0, 0x401F829CU

Definition at line 327 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_38_USDHC2_VSELECT

#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT   0x401F80ACU, 0x6U, 0, 0, 0x401F829CU

Definition at line 333 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03

#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03   0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U

Definition at line 336 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_39_GPIO3_IO25

#define IOMUXC_GPIO_EMC_39_GPIO3_IO25   0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U

Definition at line 340 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_39_LPUART8_RX

#define IOMUXC_GPIO_EMC_39_LPUART8_RX   0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U

Definition at line 337 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC

#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC   0x401F80B0U, 0x3U, 0, 0, 0x401F82A0U

Definition at line 338 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_39_SEMC_DQS

#define IOMUXC_GPIO_EMC_39_SEMC_DQS   0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U

Definition at line 335 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_39_USDHC2_CD_B

#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B   0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U

Definition at line 341 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B

#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B   0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U

Definition at line 339 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_40_ENET_MDC

#define IOMUXC_GPIO_EMC_40_ENET_MDC   0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U

Definition at line 347 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_40_GPIO3_IO26

#define IOMUXC_GPIO_EMC_40_GPIO3_IO26   0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U

Definition at line 348 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2

#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2   0x401F80B4U, 0x1U, 0, 0, 0x401F82A4U

Definition at line 344 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_40_LPSPI1_PCS2

#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2   0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U

Definition at line 345 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_40_SEMC_RDY

#define IOMUXC_GPIO_EMC_40_SEMC_RDY   0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U

Definition at line 343 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_40_USB_OTG2_OC

#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC   0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U

Definition at line 346 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_40_USDHC2_RESET_B

#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B   0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U

Definition at line 349 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_41_ENET_MDIO

#define IOMUXC_GPIO_EMC_41_ENET_MDIO   0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U

Definition at line 355 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_41_GPIO3_IO27

#define IOMUXC_GPIO_EMC_41_GPIO3_IO27   0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U

Definition at line 356 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1

#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1   0x401F80B8U, 0x1U, 0, 0, 0x401F82A8U

Definition at line 352 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_41_LPSPI1_PCS3

#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3   0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U

Definition at line 353 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_41_SEMC_CSX00

#define IOMUXC_GPIO_EMC_41_SEMC_CSX00   0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U

Definition at line 351 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_41_USB_OTG2_PWR

#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR   0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U

Definition at line 354 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_EMC_41_USDHC1_VSELECT

#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT   0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U

Definition at line 357 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00

#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00   0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU

Definition at line 898 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B

#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B   0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU

Definition at line 903 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_00_GPIO3_IO12

#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12   0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU

Definition at line 902 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL

#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL   0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU

Definition at line 899 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK

#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK   0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU

Definition at line 901 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_00_USDHC1_CMD

#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD   0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU

Definition at line 897 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04

#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04   0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU

Definition at line 900 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00

#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00   0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U

Definition at line 906 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B

#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B   0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U

Definition at line 911 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_01_GPIO3_IO13

#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13   0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U

Definition at line 910 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA

#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA   0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U

Definition at line 907 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0

#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0   0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U

Definition at line 909 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_01_USDHC1_CLK

#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK   0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U

Definition at line 905 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05

#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05   0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U

Definition at line 908 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01

#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01   0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U

Definition at line 914 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_02_GPIO3_IO14

#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14   0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U

Definition at line 918 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO

#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO   0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U

Definition at line 917 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B

#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B   0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U

Definition at line 915 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0

#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0   0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U

Definition at line 913 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06

#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06   0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U

Definition at line 916 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01

#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01   0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U

Definition at line 921 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_03_GPIO3_IO15

#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15   0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U

Definition at line 925 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI

#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI   0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U

Definition at line 924 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B

#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B   0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U

Definition at line 922 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1

#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1   0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U

Definition at line 920 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07

#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07   0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U

Definition at line 923 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_04_CCM_CLKO1

#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1   0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU

Definition at line 933 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02

#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02   0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU

Definition at line 928 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B

#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B   0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU

Definition at line 931 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_04_GPIO3_IO16

#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16   0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU

Definition at line 932 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_04_LPUART8_TX

#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX   0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU

Definition at line 929 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2

#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2   0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU

Definition at line 927 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08

#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08   0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU

Definition at line 930 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_05_CCM_CLKO2

#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2   0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U

Definition at line 941 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02

#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02   0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U

Definition at line 936 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS

#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS   0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U

Definition at line 939 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_05_GPIO3_IO17

#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17   0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U

Definition at line 940 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_05_LPUART8_RX

#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX   0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U

Definition at line 937 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3

#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3   0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U

Definition at line 935 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09

#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09   0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U

Definition at line 938 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03

#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03   0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U

Definition at line 945 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03

#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03   0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U

Definition at line 944 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_00_GPIO3_IO00

#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00   0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U

Definition at line 948 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_00_LPUART4_TX

#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX   0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U

Definition at line 947 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03

#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03   0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U

Definition at line 946 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3

#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3   0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U

Definition at line 943 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03

#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03   0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U

Definition at line 952 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02

#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02   0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U

Definition at line 951 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_01_GPIO3_IO01

#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01   0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U

Definition at line 955 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_01_LPUART4_RX

#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX   0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U

Definition at line 954 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02

#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02   0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U

Definition at line 953 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2

#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2   0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U

Definition at line 950 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_02_CCM_WAIT

#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT   0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU

Definition at line 963 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX

#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX   0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU

Definition at line 961 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03

#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03   0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU

Definition at line 959 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01

#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01   0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU

Definition at line 958 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_02_GPIO3_IO02

#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02   0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU

Definition at line 962 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01

#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01   0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU

Definition at line 960 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1

#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1   0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU

Definition at line 957 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY

#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY   0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U

Definition at line 971 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX

#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX   0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U

Definition at line 969 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03

#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03   0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U

Definition at line 967 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00

#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00   0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U

Definition at line 966 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_03_GPIO3_IO03

#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03   0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U

Definition at line 970 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_03_SAI1_MCLK

#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK   0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U

Definition at line 968 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0

#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0   0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U

Definition at line 965 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_04_CCM_STOP

#define IOMUXC_GPIO_SD_B1_04_CCM_STOP   0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U

Definition at line 979 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B

#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B   0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U

Definition at line 977 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK

#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK   0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U

Definition at line 974 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_04_GPIO3_IO04

#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04   0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U

Definition at line 978 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL

#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL   0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U

Definition at line 975 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC

#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC   0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U

Definition at line 976 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_04_USDHC2_CLK

#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK   0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U

Definition at line 973 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS

#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS   0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U

Definition at line 982 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B

#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B   0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U

Definition at line 985 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_05_GPIO3_IO05

#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05   0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U

Definition at line 986 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA

#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA   0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U

Definition at line 983 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK

#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK   0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U

Definition at line 984 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_05_USDHC2_CMD

#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD   0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U

Definition at line 981 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B

#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B   0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU

Definition at line 989 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_06_GPIO3_IO06

#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06   0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU

Definition at line 993 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0

#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0   0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU

Definition at line 992 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B

#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B   0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU

Definition at line 990 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00

#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00   0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU

Definition at line 991 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B

#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B   0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU

Definition at line 988 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK

#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK   0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U

Definition at line 996 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_07_GPIO3_IO07

#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07   0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U

Definition at line 1000 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK

#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK   0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U

Definition at line 999 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B

#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B   0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U

Definition at line 997 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00

#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00   0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U

Definition at line 998 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_07_SEMC_CSX01

#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01   0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U

Definition at line 995 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00

#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00   0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U

Definition at line 1003 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_08_GPIO3_IO08

#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08   0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U

Definition at line 1007 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0

#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0   0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U

Definition at line 1006 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_08_LPUART7_TX

#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX   0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U

Definition at line 1004 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK

#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK   0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U

Definition at line 1005 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_08_SEMC_CSX02

#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02   0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U

Definition at line 1008 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4

#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4   0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U

Definition at line 1002 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01

#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01   0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U

Definition at line 1011 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_09_GPIO3_IO09

#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09   0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U

Definition at line 1015 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI

#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI   0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U

Definition at line 1014 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_09_LPUART7_RX

#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX   0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U

Definition at line 1012 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC

#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC   0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U

Definition at line 1013 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5

#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5   0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U

Definition at line 1010 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02

#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02   0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU

Definition at line 1018 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_10_GPIO3_IO10

#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10   0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU

Definition at line 1022 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA

#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA   0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU

Definition at line 1020 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2

#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2   0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU

Definition at line 1021 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_10_LPUART2_RX

#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX   0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU

Definition at line 1019 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6

#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6   0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU

Definition at line 1017 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03

#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03   0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U

Definition at line 1025 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_11_GPIO3_IO11

#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11   0x401F8200U, 0x5U, 0, 0, 0x401F83F0U

Definition at line 1029 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL

#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL   0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U

Definition at line 1027 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3

#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3   0x401F8200U, 0x4U, 0, 0, 0x401F83F0U

Definition at line 1028 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_11_LPUART2_TX

#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX   0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U

Definition at line 1026 of file fsl_iomuxc.h.

◆ IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7

#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7   0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U

Definition at line 1024 of file fsl_iomuxc.h.

◆ IOMUXC_GPR_SAIMCLK_HIGHBITMASK

#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK   (0x3U)

Definition at line 1034 of file fsl_iomuxc.h.

◆ IOMUXC_GPR_SAIMCLK_LOWBITMASK

#define IOMUXC_GPR_SAIMCLK_LOWBITMASK   (0x7U)

Definition at line 1033 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_ONOFF

#define IOMUXC_SNVS_ONOFF   0, 0, 0, 0, 0x400A8014U

Definition at line 54 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01

#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01   0x400A8004U, 0x5U, 0, 0, 0x400A801CU

Definition at line 45 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ

#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ   0x400A8004U, 0x0U, 0, 0, 0x400A801CU

Definition at line 44 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ

#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ   0x400A8008U, 0x0U, 0, 0, 0x400A8020U

Definition at line 47 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02

#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02   0x400A8008U, 0x5U, 0, 0, 0x400A8020U

Definition at line 48 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_POR_B

#define IOMUXC_SNVS_POR_B   0, 0, 0, 0, 0x400A8010U

Definition at line 52 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_TEST_MODE

#define IOMUXC_SNVS_TEST_MODE   0, 0, 0, 0, 0x400A800CU

Definition at line 50 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_WAKEUP_GPIO5_IO00

#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00   0x400A8000U, 0x5U, 0, 0, 0x400A8018U

Definition at line 41 of file fsl_iomuxc.h.

◆ IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI

#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI   0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U

Definition at line 42 of file fsl_iomuxc.h.

Typedef Documentation

◆ iomuxc_gpr_mode_t

typedef enum _iomuxc_gpr_mode iomuxc_gpr_mode_t

◆ iomuxc_gpr_saimclk_t

typedef enum _iomuxc_gpr_saimclk iomuxc_gpr_saimclk_t

◆ iomuxc_mqs_pwm_oversample_rate_t

typedef enum _iomuxc_mqs_pwm_oversample_rate iomuxc_mqs_pwm_oversample_rate_t

Enumeration Type Documentation

◆ _iomuxc_gpr_mode

enum _iomuxc_gpr_mode
Enumerator
kIOMUXC_GPR_GlobalInterruptRequest 
kIOMUXC_GPR_ENET1RefClkMode 
kIOMUXC_GPR_USBExposureMode 
kIOMUXC_GPR_ENET1TxClkOutputDir 
kIOMUXC_GPR_SAI1MClkOutputDir 
kIOMUXC_GPR_SAI2MClkOutputDir 
kIOMUXC_GPR_SAI3MClkOutputDir 
kIOMUXC_GPR_ExcMonitorSlavErrResponse 
kIOMUXC_GPR_ENETIpgClkOn 
kIOMUXC_GPR_AHBClockEnable 

Definition at line 1036 of file fsl_iomuxc.h.

◆ _iomuxc_gpr_saimclk

enum _iomuxc_gpr_saimclk
Enumerator
kIOMUXC_GPR_SAI1MClk1Sel 
kIOMUXC_GPR_SAI1MClk2Sel 
kIOMUXC_GPR_SAI1MClk3Sel 
kIOMUXC_GPR_SAI2MClk3Sel 
kIOMUXC_GPR_SAI3MClk3Sel 

Definition at line 1050 of file fsl_iomuxc.h.

◆ _iomuxc_mqs_pwm_oversample_rate

enum _iomuxc_mqs_pwm_oversample_rate
Enumerator
kIOMUXC_MqsPwmOverSampleRate32 
kIOMUXC_MqsPwmOverSampleRate64 

Definition at line 1059 of file fsl_iomuxc.h.

Function Documentation

◆ IOMUXC_EnableMode()

static void IOMUXC_EnableMode ( IOMUXC_GPR_Type *  base,
uint32_t  mode,
bool  enable 
)
inlinestatic

Sets IOMUXC general configuration for some mode.

Parameters
baseThe IOMUXC GPR base address.
modeThe mode for setting. the mode is the logical OR of "iomuxc_gpr_mode"
enableTrue enable false disable.

Definition at line 1145 of file fsl_iomuxc.h.

◆ IOMUXC_MQSConfig()

static void IOMUXC_MQSConfig ( IOMUXC_GPR_Type *  base,
iomuxc_mqs_pwm_oversample_rate_t  rate,
uint8_t  divider 
)
inlinestatic

Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.

Parameters
baseThe IOMUXC GPR base address.
rateThe MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
dividerThe divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq.

Definition at line 1228 of file fsl_iomuxc.h.

◆ IOMUXC_MQSEnable()

static void IOMUXC_MQSEnable ( IOMUXC_GPR_Type *  base,
bool  enable 
)
inlinestatic

Enables or disables MQS.

Parameters
baseThe IOMUXC GPR base address.
enableEnable or disable the MQS.

Definition at line 1208 of file fsl_iomuxc.h.

◆ IOMUXC_MQSEnterSoftwareReset()

static void IOMUXC_MQSEnterSoftwareReset ( IOMUXC_GPR_Type *  base,
bool  enable 
)
inlinestatic

Enters or exit MQS software reset.

Parameters
baseThe IOMUXC GPR base address.
enableEnter or exit MQS software reset.

Definition at line 1190 of file fsl_iomuxc.h.

◆ IOMUXC_SetPinConfig()

static void IOMUXC_SetPinConfig ( uint32_t  muxRegister,
uint32_t  muxMode,
uint32_t  inputRegister,
uint32_t  inputDaisy,
uint32_t  configRegister,
uint32_t  configValue 
)
inlinestatic

Sets the IOMUXC pin configuration.

Note
The previous five parameters can be filled with the pin function ID macros.

This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:

IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
Parameters
muxRegisterThe pin mux register.
muxModeThe pin mux mode.
inputRegisterThe select input register.
inputDaisyThe input daisy.
configRegisterThe config register.
configValueThe pin config value.

Definition at line 1125 of file fsl_iomuxc.h.

◆ IOMUXC_SetPinMux()

static void IOMUXC_SetPinMux ( uint32_t  muxRegister,
uint32_t  muxMode,
uint32_t  inputRegister,
uint32_t  inputDaisy,
uint32_t  configRegister,
uint32_t  inputOnfield 
)
inlinestatic

Sets the IOMUXC pin mux mode.

Note
The first five parameters can be filled with the pin function ID macros.

This is an example to set the PTA6 as the lpuart0_tx:

IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);

This is an example to set the PTA0 as GPIOA0:

IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
Parameters
muxRegisterThe pin mux register.
muxModeThe pin mux mode.
inputRegisterThe select input register.
inputDaisyThe input daisy.
configRegisterThe config register.
inputOnfieldSoftware input on field.

Definition at line 1093 of file fsl_iomuxc.h.

◆ IOMUXC_SetSaiMClkClockSource()

static void IOMUXC_SetSaiMClkClockSource ( IOMUXC_GPR_Type *  base,
iomuxc_gpr_saimclk_t  mclk,
uint8_t  clkSrc 
)
inlinestatic

Sets IOMUXC general configuration for SAI MCLK selection.

Parameters
baseThe IOMUXC GPR base address.
mclkThe SAI MCLK.
clkSrcThe clock source. Take refer to register setting details for the clock source in RM.

Definition at line 1168 of file fsl_iomuxc.h.

IOMUXC_SW_PAD_CTL_PAD_PUS
#define IOMUXC_SW_PAD_CTL_PAD_PUS(x)
Definition: MIMXRT1052.h:20799
IOMUXC_SetPinConfig
static void IOMUXC_SetPinConfig(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)
Sets the IOMUXC pin configuration.
Definition: fsl_iomuxc.h:1125
IOMUXC_SetPinMux
static void IOMUXC_SetPinMux(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)
Sets the IOMUXC pin mux mode.
Definition: fsl_iomuxc.h:1093
IOMUXC_SW_PAD_CTL_PAD_PUS_MASK
#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK
Definition: MIMXRT1052.h:20791

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:11