Macros
APB1 Peripheral Clock Enable Disable
STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Collaboration diagram for APB1 Peripheral Clock Enable Disable:

Macros

#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_I2C1_CLK_DISABLE [1/3]

#define __HAL_RCC_I2C1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 524 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C1_CLK_DISABLE [2/3]

#define __HAL_RCC_I2C1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 524 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C1_CLK_DISABLE [3/3]

#define __HAL_RCC_I2C1_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 524 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C1_CLK_ENABLE [1/3]

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 498 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C1_CLK_ENABLE [2/3]

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 498 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C1_CLK_ENABLE [3/3]

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 498 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_DISABLE [1/3]

#define __HAL_RCC_I2C2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 525 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_DISABLE [2/3]

#define __HAL_RCC_I2C2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 525 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_DISABLE [3/3]

#define __HAL_RCC_I2C2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 525 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_ENABLE [1/3]

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 505 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_ENABLE [2/3]

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 505 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_ENABLE [3/3]

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 505 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_DISABLE [1/4]

#define __HAL_RCC_PWR_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 456 of file stm32f7xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_DISABLE [2/4]

#define __HAL_RCC_PWR_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 526 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_DISABLE [3/4]

#define __HAL_RCC_PWR_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 526 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_DISABLE [4/4]

#define __HAL_RCC_PWR_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 526 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_ENABLE [1/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 447 of file stm32f7xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_ENABLE [2/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 512 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_ENABLE [3/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 512 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_ENABLE [4/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 512 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_DISABLE [1/3]

#define __HAL_RCC_SPI2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 522 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_DISABLE [2/3]

#define __HAL_RCC_SPI2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 522 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_DISABLE [3/3]

#define __HAL_RCC_SPI2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 522 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_ENABLE [1/3]

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 484 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_ENABLE [2/3]

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 484 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_ENABLE [3/3]

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 484 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM5_CLK_DISABLE [1/3]

#define __HAL_RCC_TIM5_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 520 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM5_CLK_DISABLE [2/3]

#define __HAL_RCC_TIM5_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 520 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM5_CLK_DISABLE [3/3]

#define __HAL_RCC_TIM5_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 520 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM5_CLK_ENABLE [1/3]

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 470 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM5_CLK_ENABLE [2/3]

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 470 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM5_CLK_ENABLE [3/3]

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 470 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_DISABLE [1/3]

#define __HAL_RCC_USART2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 523 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_DISABLE [2/3]

#define __HAL_RCC_USART2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 523 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_DISABLE [3/3]

#define __HAL_RCC_USART2_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 523 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_ENABLE [1/3]

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 491 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_ENABLE [2/3]

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 491 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_ENABLE [3/3]

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 491 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_DISABLE [1/4]

#define __HAL_RCC_WWDG_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 455 of file stm32f7xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_DISABLE [2/4]

#define __HAL_RCC_WWDG_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 521 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_DISABLE [3/4]

#define __HAL_RCC_WWDG_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 521 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_DISABLE [4/4]

#define __HAL_RCC_WWDG_CLK_DISABLE ( )    (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 521 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_ENABLE [1/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0)

Definition at line 439 of file stm32f7xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_ENABLE [2/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 477 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_ENABLE [3/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 477 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_ENABLE [4/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 477 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h.

RCC_APB1ENR_USART2EN
#define RCC_APB1ENR_USART2EN
Definition: stm32f407xx.h:10002
RCC_APB1ENR_SPI2EN
#define RCC_APB1ENR_SPI2EN
Definition: stm32f407xx.h:9996
RCC_APB1ENR_WWDGEN
#define RCC_APB1ENR_WWDGEN
Definition: stm32f407xx.h:9993
RCC_APB1ENR_I2C2EN
#define RCC_APB1ENR_I2C2EN
Definition: stm32f407xx.h:10017
RCC_APB1ENR_PWREN
#define RCC_APB1ENR_PWREN
Definition: stm32f407xx.h:10029
RCC_APB1ENR_I2C1EN
#define RCC_APB1ENR_I2C1EN
Definition: stm32f407xx.h:10014
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:216
RCC_APB1ENR_TIM5EN
#define RCC_APB1ENR_TIM5EN
Definition: stm32f407xx.h:9975
RCC
#define RCC
Definition: stm32f407xx.h:1113

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:06