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enum | HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U
} |
| HAL DMA Callbacks IDs structure definition. More...
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enum | HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U
} |
| HAL DMA Callbacks IDs structure definition. More...
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enum | HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U
} |
| HAL DMA Error Code structure definition. More...
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enum | HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U
} |
| HAL DMA Error Code structure definition. More...
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enum | HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U
} |
| HAL DMA Error Code structure definition. More...
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enum | HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U,
HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
HAL_DMA_XFER_ALL_CB_ID = 0x06U
} |
| HAL DMA Error Code structure definition. More...
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enum | HAL_DMA_LevelCompleteTypeDef {
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U
} |
| HAL DMA Transfer complete level structure definition. More...
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enum | HAL_DMA_LevelCompleteTypeDef {
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U
} |
| HAL DMA Transfer complete level structure definition. More...
|
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enum | HAL_DMA_LevelCompleteTypeDef {
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U
} |
| HAL DMA Error Code structure definition. More...
|
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enum | HAL_DMA_LevelCompleteTypeDef {
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U
} |
| HAL DMA Error Code structure definition. More...
|
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enum | HAL_DMA_LevelCompleteTypeDef {
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U
} |
| HAL DMA Error Code structure definition. More...
|
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enum | HAL_DMA_LevelCompleteTypeDef {
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U,
HAL_DMA_FULL_TRANSFER = 0x00U,
HAL_DMA_HALF_TRANSFER = 0x01U
} |
| HAL DMA Error Code structure definition. More...
|
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enum | HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
} |
| HAL DMA State structures definition. More...
|
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enum | HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
} |
| HAL DMA State structures definition. More...
|
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enum | HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
} |
| HAL DMA State structures definition. More...
|
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enum | HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
} |
| HAL DMA State structures definition. More...
|
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enum | HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
} |
| HAL DMA State structures definition. More...
|
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enum | HAL_DMA_StateTypeDef {
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_TIMEOUT = 0x03U,
HAL_DMA_STATE_ERROR = 0x04U,
HAL_DMA_STATE_ABORT = 0x05U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U,
HAL_DMA_STATE_RESET = 0x00U,
HAL_DMA_STATE_READY = 0x01U,
HAL_DMA_STATE_BUSY = 0x02U,
HAL_DMA_STATE_ERROR = 0x03U,
HAL_DMA_STATE_ABORT = 0x04U
} |
| HAL DMA State structures definition. More...
|
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DMA Exported Types.