utils/cmsis/same70/include/instance/pmc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_PMC_INSTANCE_
36 #define _SAME70_PMC_INSTANCE_
37 
38 /* ========== Register definition for PMC peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_PMC_SCER (0x400E0600U)
41  #define REG_PMC_SCDR (0x400E0604U)
42  #define REG_PMC_SCSR (0x400E0608U)
43  #define REG_PMC_PCER0 (0x400E0610U)
44  #define REG_PMC_PCDR0 (0x400E0614U)
45  #define REG_PMC_PCSR0 (0x400E0618U)
46  #define REG_CKGR_UCKR (0x400E061CU)
47  #define REG_CKGR_MOR (0x400E0620U)
48  #define REG_CKGR_MCFR (0x400E0624U)
49  #define REG_CKGR_PLLAR (0x400E0628U)
50  #define REG_PMC_MCKR (0x400E0630U)
51  #define REG_PMC_USB (0x400E0638U)
52  #define REG_PMC_PCK (0x400E0640U)
53  #define REG_PMC_IER (0x400E0660U)
54  #define REG_PMC_IDR (0x400E0664U)
55  #define REG_PMC_SR (0x400E0668U)
56  #define REG_PMC_IMR (0x400E066CU)
57  #define REG_PMC_FSMR (0x400E0670U)
58  #define REG_PMC_FSPR (0x400E0674U)
59  #define REG_PMC_FOCR (0x400E0678U)
60  #define REG_PMC_WPMR (0x400E06E4U)
61  #define REG_PMC_WPSR (0x400E06E8U)
62  #define REG_PMC_VERSION (0x400E06FCU)
63  #define REG_PMC_PCER1 (0x400E0700U)
64  #define REG_PMC_PCDR1 (0x400E0704U)
65  #define REG_PMC_PCSR1 (0x400E0708U)
66  #define REG_PMC_PCR (0x400E070CU)
67  #define REG_PMC_OCR (0x400E0710U)
68  #define REG_PMC_SLPWK_ER0 (0x400E0714U)
69  #define REG_PMC_SLPWK_DR0 (0x400E0718U)
70  #define REG_PMC_SLPWK_SR0 (0x400E071CU)
71  #define REG_PMC_SLPWK_ASR0 (0x400E0720U)
72  #define REG_PMC_PMMR (0x400E0730U)
73  #define REG_PMC_SLPWK_ER1 (0x400E0734U)
74  #define REG_PMC_SLPWK_DR1 (0x400E0738U)
75  #define REG_PMC_SLPWK_SR1 (0x400E073CU)
76  #define REG_PMC_SLPWK_ASR1 (0x400E0740U)
77  #define REG_PMC_SLPWK_AIPR (0x400E0744U)
78  #define REG_PMC_APLLACR (0x400E0758U)
79  #define REG_PMC_WMST (0x400E075CU)
80 #else
81  #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U)
82  #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U)
83  #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U)
84  #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U)
85  #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U)
86  #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U)
87  #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU)
88  #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U)
89  #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U)
90  #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U)
91  #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U)
92  #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U)
93  #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U)
94  #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U)
95  #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U)
96  #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U)
97  #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU)
98  #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U)
99  #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U)
100  #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U)
101  #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U)
102  #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U)
103  #define REG_PMC_VERSION (*(__I uint32_t*)0x400E06FCU)
104  #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U)
105  #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U)
106  #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U)
107  #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU)
108  #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U)
109  #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U)
110  #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U)
111  #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU)
112  #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U)
113  #define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U)
114  #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U)
115  #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U)
116  #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU)
117  #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U)
118  #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U)
119  #define REG_PMC_APLLACR (*(__IO uint32_t*)0x400E0758U)
120  #define REG_PMC_WMST (*(__IO uint32_t*)0x400E075CU)
121 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
122 
123 #endif /* _SAME70_PMC_INSTANCE_ */


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04