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Macros
#define	REG_TC1_BCR ((__O uint32_t)0x400100C0U)
	(TC1) Block Control Register More...

#define	REG_TC1_BMR ((__IO uint32_t)0x400100C4U)
	(TC1) Block Mode Register More...

#define	REG_TC1_CCR0 ((__O uint32_t)0x40010000U)
	(TC1) Channel Control Register (channel = 0) More...

#define	REG_TC1_CCR1 ((__O uint32_t)0x40010040U)
	(TC1) Channel Control Register (channel = 1) More...

#define	REG_TC1_CCR2 ((__O uint32_t)0x40010080U)
	(TC1) Channel Control Register (channel = 2) More...

#define	REG_TC1_CMR0 ((__IO uint32_t)0x40010004U)
	(TC1) Channel Mode Register (channel = 0) More...

#define	REG_TC1_CMR1 ((__IO uint32_t)0x40010044U)
	(TC1) Channel Mode Register (channel = 1) More...

#define	REG_TC1_CMR2 ((__IO uint32_t)0x40010084U)
	(TC1) Channel Mode Register (channel = 2) More...

#define	REG_TC1_CV0 ((__I uint32_t)0x40010010U)
	(TC1) Counter Value (channel = 0) More...

#define	REG_TC1_CV1 ((__I uint32_t)0x40010050U)
	(TC1) Counter Value (channel = 1) More...

#define	REG_TC1_CV2 ((__I uint32_t)0x40010090U)
	(TC1) Counter Value (channel = 2) More...

#define	REG_TC1_EMR0 ((__IO uint32_t)0x40010030U)
	(TC1) Extended Mode Register (channel = 0) More...

#define	REG_TC1_EMR1 ((__IO uint32_t)0x40010070U)
	(TC1) Extended Mode Register (channel = 1) More...

#define	REG_TC1_EMR2 ((__IO uint32_t)0x400100B0U)
	(TC1) Extended Mode Register (channel = 2) More...

#define	REG_TC1_FMR ((__IO uint32_t)0x400100D8U)
	(TC1) Fault Mode Register More...

#define	REG_TC1_IDR0 ((__O uint32_t)0x40010028U)
	(TC1) Interrupt Disable Register (channel = 0) More...

#define	REG_TC1_IDR1 ((__O uint32_t)0x40010068U)
	(TC1) Interrupt Disable Register (channel = 1) More...

#define	REG_TC1_IDR2 ((__O uint32_t)0x400100A8U)
	(TC1) Interrupt Disable Register (channel = 2) More...

#define	REG_TC1_IER0 ((__O uint32_t)0x40010024U)
	(TC1) Interrupt Enable Register (channel = 0) More...

#define	REG_TC1_IER1 ((__O uint32_t)0x40010064U)
	(TC1) Interrupt Enable Register (channel = 1) More...

#define	REG_TC1_IER2 ((__O uint32_t)0x400100A4U)
	(TC1) Interrupt Enable Register (channel = 2) More...

#define	REG_TC1_IMR0 ((__I uint32_t)0x4001002CU)
	(TC1) Interrupt Mask Register (channel = 0) More...

#define	REG_TC1_IMR1 ((__I uint32_t)0x4001006CU)
	(TC1) Interrupt Mask Register (channel = 1) More...

#define	REG_TC1_IMR2 ((__I uint32_t)0x400100ACU)
	(TC1) Interrupt Mask Register (channel = 2) More...

#define	REG_TC1_QIDR ((__O uint32_t)0x400100CCU)
	(TC1) QDEC Interrupt Disable Register More...

#define	REG_TC1_QIER ((__O uint32_t)0x400100C8U)
	(TC1) QDEC Interrupt Enable Register More...

#define	REG_TC1_QIMR ((__I uint32_t)0x400100D0U)
	(TC1) QDEC Interrupt Mask Register More...

#define	REG_TC1_QISR ((__I uint32_t)0x400100D4U)
	(TC1) QDEC Interrupt Status Register More...

#define	REG_TC1_RA0 ((__IO uint32_t)0x40010014U)
	(TC1) Register A (channel = 0) More...

#define	REG_TC1_RA1 ((__IO uint32_t)0x40010054U)
	(TC1) Register A (channel = 1) More...

#define	REG_TC1_RA2 ((__IO uint32_t)0x40010094U)
	(TC1) Register A (channel = 2) More...

#define	REG_TC1_RAB0 ((__I uint32_t)0x4001000CU)
	(TC1) Register AB (channel = 0) More...

#define	REG_TC1_RAB1 ((__I uint32_t)0x4001004CU)
	(TC1) Register AB (channel = 1) More...

#define	REG_TC1_RAB2 ((__I uint32_t)0x4001008CU)
	(TC1) Register AB (channel = 2) More...

#define	REG_TC1_RB0 ((__IO uint32_t)0x40010018U)
	(TC1) Register B (channel = 0) More...

#define	REG_TC1_RB1 ((__IO uint32_t)0x40010058U)
	(TC1) Register B (channel = 1) More...

#define	REG_TC1_RB2 ((__IO uint32_t)0x40010098U)
	(TC1) Register B (channel = 2) More...

#define	REG_TC1_RC0 ((__IO uint32_t)0x4001001CU)
	(TC1) Register C (channel = 0) More...

#define	REG_TC1_RC1 ((__IO uint32_t)0x4001005CU)
	(TC1) Register C (channel = 1) More...

#define	REG_TC1_RC2 ((__IO uint32_t)0x4001009CU)
	(TC1) Register C (channel = 2) More...

#define	REG_TC1_SMMR0 ((__IO uint32_t)0x40010008U)
	(TC1) Stepper Motor Mode Register (channel = 0) More...

#define	REG_TC1_SMMR1 ((__IO uint32_t)0x40010048U)
	(TC1) Stepper Motor Mode Register (channel = 1) More...

#define	REG_TC1_SMMR2 ((__IO uint32_t)0x40010088U)
	(TC1) Stepper Motor Mode Register (channel = 2) More...

#define	REG_TC1_SR0 ((__I uint32_t)0x40010020U)
	(TC1) Status Register (channel = 0) More...

#define	REG_TC1_SR1 ((__I uint32_t)0x40010060U)
	(TC1) Status Register (channel = 1) More...

#define	REG_TC1_SR2 ((__I uint32_t)0x400100A0U)
	(TC1) Status Register (channel = 2) More...

#define	REG_TC1_VER ((__I uint32_t)0x400100FCU)
	(TC1) Version Register More...

#define	REG_TC1_WPMR ((__IO uint32_t)0x400100E4U)
	(TC1) Write Protection Mode Register More...

Detailed Description

Definition in file tc1.h.

Macro Definition Documentation

◆ REG_TC1_BCR

#define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U)

(TC1) Block Control Register

Definition at line 128 of file tc1.h.

◆ REG_TC1_BMR

#define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U)

(TC1) Block Mode Register

Definition at line 129 of file tc1.h.

◆ REG_TC1_CCR0

#define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U)

(TC1) Channel Control Register (channel = 0)

Definition at line 89 of file tc1.h.

◆ REG_TC1_CCR1

#define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U)

(TC1) Channel Control Register (channel = 1)

Definition at line 102 of file tc1.h.

◆ REG_TC1_CCR2

#define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U)

(TC1) Channel Control Register (channel = 2)

Definition at line 115 of file tc1.h.

◆ REG_TC1_CMR0

#define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U)

(TC1) Channel Mode Register (channel = 0)

Definition at line 90 of file tc1.h.

◆ REG_TC1_CMR1

#define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U)

(TC1) Channel Mode Register (channel = 1)

Definition at line 103 of file tc1.h.

◆ REG_TC1_CMR2

#define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U)

(TC1) Channel Mode Register (channel = 2)

Definition at line 116 of file tc1.h.

◆ REG_TC1_CV0

#define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U)

(TC1) Counter Value (channel = 0)

Definition at line 93 of file tc1.h.

◆ REG_TC1_CV1

#define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U)

(TC1) Counter Value (channel = 1)

Definition at line 106 of file tc1.h.

◆ REG_TC1_CV2

#define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U)

(TC1) Counter Value (channel = 2)

Definition at line 119 of file tc1.h.

◆ REG_TC1_EMR0

#define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U)

(TC1) Extended Mode Register (channel = 0)

Definition at line 101 of file tc1.h.

◆ REG_TC1_EMR1

#define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U)

(TC1) Extended Mode Register (channel = 1)

Definition at line 114 of file tc1.h.

◆ REG_TC1_EMR2

#define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U)

(TC1) Extended Mode Register (channel = 2)

Definition at line 127 of file tc1.h.

◆ REG_TC1_FMR

#define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U)

(TC1) Fault Mode Register

Definition at line 134 of file tc1.h.

◆ REG_TC1_IDR0

#define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U)

(TC1) Interrupt Disable Register (channel = 0)

Definition at line 99 of file tc1.h.

◆ REG_TC1_IDR1

#define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U)

(TC1) Interrupt Disable Register (channel = 1)

Definition at line 112 of file tc1.h.

◆ REG_TC1_IDR2

#define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U)

(TC1) Interrupt Disable Register (channel = 2)

Definition at line 125 of file tc1.h.

◆ REG_TC1_IER0

#define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U)

(TC1) Interrupt Enable Register (channel = 0)

Definition at line 98 of file tc1.h.

◆ REG_TC1_IER1

#define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U)

(TC1) Interrupt Enable Register (channel = 1)

Definition at line 111 of file tc1.h.

◆ REG_TC1_IER2

#define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U)

(TC1) Interrupt Enable Register (channel = 2)

Definition at line 124 of file tc1.h.

◆ REG_TC1_IMR0

#define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU)

(TC1) Interrupt Mask Register (channel = 0)

Definition at line 100 of file tc1.h.

◆ REG_TC1_IMR1

#define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU)

(TC1) Interrupt Mask Register (channel = 1)

Definition at line 113 of file tc1.h.

◆ REG_TC1_IMR2

#define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU)

(TC1) Interrupt Mask Register (channel = 2)

Definition at line 126 of file tc1.h.

◆ REG_TC1_QIDR

#define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU)

(TC1) QDEC Interrupt Disable Register

Definition at line 131 of file tc1.h.

◆ REG_TC1_QIER

#define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U)

(TC1) QDEC Interrupt Enable Register

Definition at line 130 of file tc1.h.

◆ REG_TC1_QIMR

#define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U)

(TC1) QDEC Interrupt Mask Register

Definition at line 132 of file tc1.h.

◆ REG_TC1_QISR

#define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U)

(TC1) QDEC Interrupt Status Register

Definition at line 133 of file tc1.h.

◆ REG_TC1_RA0

#define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U)

(TC1) Register A (channel = 0)

Definition at line 94 of file tc1.h.

◆ REG_TC1_RA1

#define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U)

(TC1) Register A (channel = 1)

Definition at line 107 of file tc1.h.

◆ REG_TC1_RA2

#define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U)

(TC1) Register A (channel = 2)

Definition at line 120 of file tc1.h.

◆ REG_TC1_RAB0

#define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU)

(TC1) Register AB (channel = 0)

Definition at line 92 of file tc1.h.

◆ REG_TC1_RAB1

#define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU)

(TC1) Register AB (channel = 1)

Definition at line 105 of file tc1.h.

◆ REG_TC1_RAB2

#define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU)

(TC1) Register AB (channel = 2)

Definition at line 118 of file tc1.h.

◆ REG_TC1_RB0

#define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U)

(TC1) Register B (channel = 0)

Definition at line 95 of file tc1.h.

◆ REG_TC1_RB1

#define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U)

(TC1) Register B (channel = 1)

Definition at line 108 of file tc1.h.

◆ REG_TC1_RB2

#define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U)

(TC1) Register B (channel = 2)

Definition at line 121 of file tc1.h.

◆ REG_TC1_RC0

#define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU)

(TC1) Register C (channel = 0)

Definition at line 96 of file tc1.h.

◆ REG_TC1_RC1

#define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU)

(TC1) Register C (channel = 1)

Definition at line 109 of file tc1.h.

◆ REG_TC1_RC2

#define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU)

(TC1) Register C (channel = 2)

Definition at line 122 of file tc1.h.

◆ REG_TC1_SMMR0

#define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U)

(TC1) Stepper Motor Mode Register (channel = 0)

Definition at line 91 of file tc1.h.

◆ REG_TC1_SMMR1

#define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U)

(TC1) Stepper Motor Mode Register (channel = 1)

Definition at line 104 of file tc1.h.

◆ REG_TC1_SMMR2

#define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U)

(TC1) Stepper Motor Mode Register (channel = 2)

Definition at line 117 of file tc1.h.

◆ REG_TC1_SR0

#define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U)

(TC1) Status Register (channel = 0)

Definition at line 97 of file tc1.h.

◆ REG_TC1_SR1

#define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U)

(TC1) Status Register (channel = 1)

Definition at line 110 of file tc1.h.

◆ REG_TC1_SR2

#define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U)

(TC1) Status Register (channel = 2)

Definition at line 123 of file tc1.h.

◆ REG_TC1_VER

#define REG_TC1_VER (*(__I uint32_t*)0x400100FCU)

(TC1) Version Register

Definition at line 136 of file tc1.h.

◆ REG_TC1_WPMR

#define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U)

(TC1) Write Protection Mode Register

Definition at line 135 of file tc1.h.

Macros