51 #ifndef SPI_WPMR_WPKEY_PASSWD 52 #define SPI_WPMR_WPKEY_PASSWD SPI_WPMR_WPKEY((uint32_t) 0x535049) 62 #if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54) 65 #elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) 70 else if (p_spi ==
SPI1) {
79 else if (p_spi ==
SPI1) {
84 else if (p_spi == SPI2) {
89 else if (p_spi == SPI3) {
94 else if (p_spi == SPI4) {
99 else if (p_spi == SPI5) {
104 else if (p_spi == SPI6) {
109 else if (p_spi == SPI7) {
125 #if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54) 128 #elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) 133 else if (p_spi ==
SPI1) {
142 else if (p_spi ==
SPI1) {
147 else if (p_spi == SPI2) {
152 else if (p_spi == SPI3) {
157 else if (p_spi == SPI4) {
162 else if (p_spi == SPI5) {
167 else if (p_spi == SPI6) {
172 else if (p_spi == SPI7) {
227 static uint32_t reg_value;
258 uint8_t uc_pcs, uint8_t uc_last)
291 uint32_t ul_polarity)
324 uint32_t ul_cs_behavior)
349 p_spi->
SPI_CSR[ul_pcs_ch] |= ul_bits;
364 int baud_div =
div_ceil(mck, baudrate);
367 if (baud_div <= 0 || baud_div > 255) {
386 uint8_t uc_baudrate_divider)
389 if (!uc_baudrate_divider){
406 uint8_t uc_dlybs, uint8_t uc_dlybct)
424 p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE | SPI_WPCR_SPIWPEN;
426 p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE;
#define SPI_WPMR_WPEN
(SPI_WPMR) Write Protection Enable
__I uint32_t SPI_SR
(Spi Offset: 0x10) Status Register
#define div_ceil(a, b)
Calculate using integer arithmetic.
void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase)
Set Data Capture Phase.
void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_cs_behavior)
Configure CS behavior for SPI transfer (spi_cs_behavior_t).
#define SPI_CSR_SCBR_Msk
(SPI_CSR[4]) Serial Clock Bit Rate
#define SPI_CSR_SCBR(value)
#define SPI1
(SPI1 ) Base Address
__IO uint32_t SPI_CSR[4]
(Spi Offset: 0x30) Chip Select Register (CS_number = 0)
#define UNUSED(v)
Marking v as a unused parameter or value.
__I uint32_t SPI_RDR
(Spi Offset: 0x08) Receive Data Register
#define ID_SPI1
Serial Peripheral Interface 1 (SPI1)
spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs)
Read the received data and it's peripheral chip select value. While SPI works in fixed peripheral sel...
int16_t spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_baudrate_divider)
Set Serial Clock Baud Rate divider value (SCBR).
GeneratorWrapper< T > value(T &&value)
#define SPI_MR_DLYBCS(value)
void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits)
Set number of bits per transfer.
#define SPI_CSR_CSNAAT
(SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_polarity)
Set clock default state.
#define SPI_CSR_DLYBS_Msk
(SPI_CSR[4]) Delay Before SPCK
#define SPI_TDR_TD(value)
#define ID_SPI0
Serial Peripheral Interface 0 (SPI0)
#define SPI_MR_PCS(value)
void spi_enable_clock(Spi *p_spi)
Enable SPI clock.
__IO uint32_t SPI_WPMR
(Spi Offset: 0xE4) Write Protection Mode Register
#define SPI_CSR_BITS_Msk
(SPI_CSR[4]) Bits Per Transfer
#define SPI_RDR_PCS_Msk
(SPI_RDR) Peripheral Chip Select
__O uint32_t SPI_TDR
(Spi Offset: 0x0C) Transmit Data Register
spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs, uint8_t uc_last)
Write the transmitted data with specified peripheral chip select value.
#define SPI_CSR_DLYBCT(value)
static void sysclk_disable_peripheral_clock(uint32_t ul_id)
Disable a peripheral's clock.
#define SPI_SR_TDRE
(SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR)
void spi_disable_clock(Spi *p_spi)
Disable SPI clock.
void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value)
Set Peripheral Chip Select (PCS) value.
#define SPI0
(SPI0 ) Base Address
#define SPI_TDR_PCS(value)
#define SPI_WPMR_WPKEY_PASSWD
#define SPI_CSR_CPOL
(SPI_CSR[4]) Clock Polarity
#define SPI_MR_PCS_Msk
(SPI_MR) Peripheral Chip Select
int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck)
Calculate the baudrate divider.
void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs, uint8_t uc_dlybct)
Configure timing for SPI transfer.
Serial Peripheral Interface (SPI) driver for SAM.
__I uint32_t SPI_WPSR
(Spi Offset: 0xE8) Write Protection Status Register
void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay)
Set delay between chip selects (in number of MCK clocks). If DLYBCS <= 6, 6 MCK clocks will be insert...
#define SPI_CSR_NCPHA
(SPI_CSR[4]) Clock Phase
void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable)
Enable or disable write protection of SPI registers.
#define SPI_SR_RDRF
(SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR)
#define SPI_TDR_LASTXFER
(SPI_TDR) Last Transfer
static void sysclk_enable_peripheral_clock(uint32_t ul_id)
Enable a peripheral's clock.
static uint32_t spi_get_peripheral_select_mode(Spi *p_spi)
Get Peripheral Select mode.
#define SPI_RDR_RD_Msk
(SPI_RDR) Receive Data
#define SPI_CSR_DLYBCT_Msk
(SPI_CSR[4]) Delay Between Consecutive Transfers
__IO uint32_t SPI_MR
(Spi Offset: 0x04) Mode Register
#define SPI_CSR_DLYBS(value)
#define SPI_MR_DLYBCS_Msk
(SPI_MR) Delay Between Chip Selects
uint32_t spi_get_writeprotect_status(Spi *p_spi)
Indicate write protect status.
#define SPI_CSR_CSAAT
(SPI_CSR[4]) Chip Select Active After Transfer