same70/genclk.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef CHIP_GENCLK_H_INCLUDED
#define CHIP_GENCLK_H_INCLUDED

#include <osc.h>
#include <pll.h>


#ifdef __cplusplus
extern "C" {
#endif



#define GENCLK_PCK_0 0 
#define GENCLK_PCK_1 1 
#define GENCLK_PCK_2 2 




enum genclk_source {
        GENCLK_PCK_SRC_SLCK_RC       = 0,
        GENCLK_PCK_SRC_SLCK_XTAL     = 1,
        GENCLK_PCK_SRC_SLCK_BYPASS   = 2,
        GENCLK_PCK_SRC_MAINCK_4M_RC  = 3,
        GENCLK_PCK_SRC_MAINCK_8M_RC  = 4,
        GENCLK_PCK_SRC_MAINCK_12M_RC = 5,
        GENCLK_PCK_SRC_MAINCK_XTAL   = 6,
        GENCLK_PCK_SRC_MAINCK_BYPASS = 7,
        GENCLK_PCK_SRC_PLLACK        = 8,
        GENCLK_PCK_SRC_MCK           = 9,
};




enum genclk_divider {
        GENCLK_PCK_PRES_1  = PMC_PCK_PRES(0), 
        GENCLK_PCK_PRES_2  = PMC_PCK_PRES(1), 
        GENCLK_PCK_PRES_4  = PMC_PCK_PRES(2), 
        GENCLK_PCK_PRES_8  = PMC_PCK_PRES(3), 
        GENCLK_PCK_PRES_16 = PMC_PCK_PRES(4), 
        GENCLK_PCK_PRES_32 = PMC_PCK_PRES(5), 
        GENCLK_PCK_PRES_64 = PMC_PCK_PRES(6), 
};


struct genclk_config {
        uint32_t ctrl;
};

static inline void genclk_config_defaults(struct genclk_config *p_cfg,
                uint32_t ul_id)
{
        ul_id = ul_id;
        p_cfg->ctrl = 0;
}

static inline void genclk_config_read(struct genclk_config *p_cfg,
                uint32_t ul_id)
{
        p_cfg->ctrl = PMC->PMC_PCK[ul_id];
}

static inline void genclk_config_write(const struct genclk_config *p_cfg,
                uint32_t ul_id)
{
        PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
}



static inline void genclk_config_set_source(struct genclk_config *p_cfg,
                enum genclk_source e_src)
{
        p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);

        switch (e_src) {
        case GENCLK_PCK_SRC_SLCK_RC:
        case GENCLK_PCK_SRC_SLCK_XTAL:
        case GENCLK_PCK_SRC_SLCK_BYPASS:
                p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
                break;

        case GENCLK_PCK_SRC_MAINCK_4M_RC:
        case GENCLK_PCK_SRC_MAINCK_8M_RC:
        case GENCLK_PCK_SRC_MAINCK_12M_RC:
        case GENCLK_PCK_SRC_MAINCK_XTAL:
        case GENCLK_PCK_SRC_MAINCK_BYPASS:
                p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
                break;

        case GENCLK_PCK_SRC_PLLACK:
                p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
                break;

        case GENCLK_PCK_SRC_MCK:
                p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
                break;

        default:
                break;
        }
}

static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
                uint32_t e_divider)
{
        p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
        p_cfg->ctrl |= e_divider;
}


static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)
{
        PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
        pmc_enable_pck(ul_id);
}

static inline void genclk_disable(uint32_t ul_id)
{
        pmc_disable_pck(ul_id);
}

static inline void genclk_enable_source(enum genclk_source e_src)
{
        switch (e_src) {
        case GENCLK_PCK_SRC_SLCK_RC:
                if (!osc_is_ready(OSC_SLCK_32K_RC)) {
                        osc_enable(OSC_SLCK_32K_RC);
                        osc_wait_ready(OSC_SLCK_32K_RC);
                }
                break;

        case GENCLK_PCK_SRC_SLCK_XTAL:
                if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
                        osc_enable(OSC_SLCK_32K_XTAL);
                        osc_wait_ready(OSC_SLCK_32K_XTAL);
                }
                break;

        case GENCLK_PCK_SRC_SLCK_BYPASS:
                if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
                        osc_enable(OSC_SLCK_32K_BYPASS);
                        osc_wait_ready(OSC_SLCK_32K_BYPASS);
                }
                break;

        case GENCLK_PCK_SRC_MAINCK_4M_RC:
                if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
                        osc_enable(OSC_MAINCK_4M_RC);
                        osc_wait_ready(OSC_MAINCK_4M_RC);
                }
                break;

        case GENCLK_PCK_SRC_MAINCK_8M_RC:
                if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
                        osc_enable(OSC_MAINCK_8M_RC);
                        osc_wait_ready(OSC_MAINCK_8M_RC);
                }
                break;

        case GENCLK_PCK_SRC_MAINCK_12M_RC:
                if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
                        osc_enable(OSC_MAINCK_12M_RC);
                        osc_wait_ready(OSC_MAINCK_12M_RC);
                }
                break;

        case GENCLK_PCK_SRC_MAINCK_XTAL:
                if (!osc_is_ready(OSC_MAINCK_XTAL)) {
                        osc_enable(OSC_MAINCK_XTAL);
                        osc_wait_ready(OSC_MAINCK_XTAL);
                }
                break;

        case GENCLK_PCK_SRC_MAINCK_BYPASS:
                if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
                        osc_enable(OSC_MAINCK_BYPASS);
                        osc_wait_ready(OSC_MAINCK_BYPASS);
                }
                break;

#ifdef CONFIG_PLL0_SOURCE
        case GENCLK_PCK_SRC_PLLACK:
                pll_enable_config_defaults(0);
                break;
#endif

        case GENCLK_PCK_SRC_MCK:
                break;

        default:
                Assert(false);
                break;
        }
}



#ifdef __cplusplus
}
#endif


#endif /* CHIP_GENCLK_H_INCLUDED */