same70/genclk.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef CHIP_GENCLK_H_INCLUDED
38 #define CHIP_GENCLK_H_INCLUDED
39 
40 #include <osc.h>
41 #include <pll.h>
42 
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 
56 
58 #define GENCLK_PCK_0 0
59 #define GENCLK_PCK_1 1
60 #define GENCLK_PCK_2 2
61 
62 
63 
65 
77 };
78 
80 
82 
83 
92 };
93 
95 
96 struct genclk_config {
97  uint32_t ctrl;
98 };
99 
100 static inline void genclk_config_defaults(struct genclk_config *p_cfg,
101  uint32_t ul_id)
102 {
103  ul_id = ul_id;
104  p_cfg->ctrl = 0;
105 }
106 
107 static inline void genclk_config_read(struct genclk_config *p_cfg,
108  uint32_t ul_id)
109 {
110  p_cfg->ctrl = PMC->PMC_PCK[ul_id];
111 }
112 
113 static inline void genclk_config_write(const struct genclk_config *p_cfg,
114  uint32_t ul_id)
115 {
116  PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
117 }
118 
120 
121 
122 static inline void genclk_config_set_source(struct genclk_config *p_cfg,
123  enum genclk_source e_src)
124 {
125  p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
126 
127  switch (e_src) {
131  p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
132  break;
133 
139  p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
140  break;
141 
143  p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
144  break;
145 
146  case GENCLK_PCK_SRC_MCK:
147  p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
148  break;
149 
150  default:
151  break;
152  }
153 }
154 
155 static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
156  uint32_t e_divider)
157 {
158  p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
159  p_cfg->ctrl |= e_divider;
160 }
161 
163 
164 static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)
165 {
166  PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
167  pmc_enable_pck(ul_id);
168 }
169 
170 static inline void genclk_disable(uint32_t ul_id)
171 {
172  pmc_disable_pck(ul_id);
173 }
174 
175 static inline void genclk_enable_source(enum genclk_source e_src)
176 {
177  switch (e_src) {
182  }
183  break;
184 
189  }
190  break;
191 
196  }
197  break;
198 
203  }
204  break;
205 
210  }
211  break;
212 
217  }
218  break;
219 
224  }
225  break;
226 
231  }
232  break;
233 
234 #ifdef CONFIG_PLL0_SOURCE
237  break;
238 #endif
239 
240  case GENCLK_PCK_SRC_MCK:
241  break;
242 
243  default:
244  Assert(false);
245  break;
246  }
247 }
248 
250 
252 
253 #ifdef __cplusplus
254 }
255 #endif
256 
257 
259 #endif /* CHIP_GENCLK_H_INCLUDED */
static void osc_wait_ready(uint8_t id)
Wait until the oscillator identified by id is ready.
Definition: osc.h:162
#define PMC
(PMC ) Base Address
Definition: same70j19.h:524
#define OSC_SLCK_32K_RC
Internal 32kHz RC oscillator.
Definition: same70/osc.h:87
#define PMC_PCK_PRES_Msk
(PMC_PCK[8]) Programmable Clock Prescaler
void pmc_enable_pck(uint32_t ul_id)
Enable the specified programmable clock.
Definition: pmc.c:1020
#define OSC_SLCK_32K_BYPASS
External 32kHz bypass oscillator.
Definition: same70/osc.h:89
#define OSC_MAINCK_12M_RC
Internal 12MHz RC oscillator.
Definition: same70/osc.h:92
Set PCK clock prescaler to 32.
Definition: same70/genclk.h:90
Set PCK clock prescaler to 16.
Definition: same70/genclk.h:89
Set PCK clock prescaler to 8.
Definition: same70/genclk.h:88
Internal 12MHz RC oscillator as PCK source clock.
Definition: same70/genclk.h:72
genclk_source
Generic clock source ID.
Definition: same70/genclk.h:66
static void genclk_enable_source(enum genclk_source e_src)
Enable the source clock src used by a generic clock.
genclk_divider
Definition: same70/genclk.h:84
static void genclk_config_set_source(struct genclk_config *p_cfg, enum genclk_source e_src)
Select a new source clock src in configuration cfg.
#define PMC_PCK_CSS_SLOW_CLK
(PMC_PCK[8]) Slow Clock is selected
Set PCK clock prescaler to 4.
Definition: same70/genclk.h:87
void pmc_disable_pck(uint32_t ul_id)
Disable the specified programmable clock.
Definition: pmc.c:1030
Set PCK clock prescaler to 64.
Definition: same70/genclk.h:91
Chip-specific PLL definitions.
Set PCK clock prescaler to 2.
Definition: same70/genclk.h:86
#define PMC_PCK_CSS_PLLA_CLK
(PMC_PCK[8]) PLLA Clock is selected
Use PLLACK as PCK source clock.
Definition: same70/genclk.h:75
static void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)
External 32kHz crystal oscillator as PCK source clock.
Definition: same70/genclk.h:68
static void osc_enable(uint32_t ul_id)
Definition: same70/osc.h:109
static void genclk_config_defaults(struct genclk_config *p_cfg, uint32_t ul_id)
static void genclk_config_read(struct genclk_config *p_cfg, uint32_t ul_id)
External bypass oscillator as PCK source clock.
Definition: same70/genclk.h:74
#define PMC_PCK_CSS_MAIN_CLK
(PMC_PCK[8]) Main Clock is selected
Hardware representation of a set of generic clock parameters.
Definition: same70/genclk.h:96
static void genclk_config_write(const struct genclk_config *p_cfg, uint32_t ul_id)
#define PMC_PCK_PRES(value)
static void genclk_disable(uint32_t ul_id)
#define PMC_PCK_CSS_Msk
(PMC_PCK[8]) Programmable Clock Source Selection
Set PCK clock prescaler to 1.
Definition: same70/genclk.h:85
Internal 32kHz RC oscillator as PCK source clock.
Definition: same70/genclk.h:67
#define OSC_MAINCK_BYPASS
External bypass oscillator.
Definition: same70/osc.h:94
#define PMC_PCK_CSS_MCK
(PMC_PCK[8]) Master Clock is selected
static void genclk_config_set_divider(struct genclk_config *p_cfg, uint32_t e_divider)
uint32_t ctrl
Definition: same70/genclk.h:97
Use Master Clk as PCK source clock.
Definition: same70/genclk.h:76
static void pll_enable_config_defaults(unsigned int ul_pll_id)
Enable the pll with the default configuration. PLL is enabled, if the PLL is not already locked...
Definition: same70/pll.h:215
#define OSC_MAINCK_8M_RC
Internal 8MHz RC oscillator.
Definition: same70/osc.h:91
#define OSC_MAINCK_4M_RC
Internal 4MHz RC oscillator.
Definition: same70/osc.h:90
#define OSC_MAINCK_XTAL
External crystal oscillator.
Definition: same70/osc.h:93
static bool osc_is_ready(uint32_t ul_id)
Definition: same70/osc.h:175
Chip-specific oscillator management functions.
#define Assert(expr)
This macro is used to test fatal errors.
Definition: compiler.h:196
External crystal oscillator as PCK source clock.
Definition: same70/genclk.h:73
#define OSC_SLCK_32K_XTAL
External 32kHz crystal oscillator.
Definition: same70/osc.h:88
Internal 4MHz RC oscillator as PCK source clock.
Definition: same70/genclk.h:70
Internal 8MHz RC oscillator as PCK source clock.
Definition: same70/genclk.h:71
External 32kHz bypass oscillator as PCK source clock.
Definition: same70/genclk.h:69


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autogenerated on Sat Sep 19 2020 03:19:04