mpu.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 
38 #ifndef _MPU_H_
39 #define _MPU_H_
40 
41 #include "compiler.h"
42 
43 /*----------------------------------------------------------------------------
44  * Definitions
45  *----------------------------------------------------------------------------*/
46 #define ARM_MODE_USR 0x10
47 
48 #define PRIVILEGE_MODE 0
49 #define USER_MODE 1
50 
51 #define MPU_DEFAULT_ITCM_REGION ( 1 )
52 #define MPU_DEFAULT_IFLASH_REGION ( 2 )
53 #define MPU_DEFAULT_DTCM_REGION ( 3 )
54 #define MPU_DEFAULT_SRAM_REGION_1 ( 4 )
55 #define MPU_DEFAULT_SRAM_REGION_2 ( 5 )
56 #define MPU_PERIPHERALS_REGION ( 6 )
57 #define MPU_EXT_EBI_REGION ( 7 )
58 #define MPU_DEFAULT_SDRAM_REGION ( 8 )
59 #define MPU_QSPIMEM_REGION ( 9 )
60 #define MPU_USBHSRAM_REGION ( 10 )
61 #if defined MPU_HAS_NOCACHE_REGION
62 #define MPU_NOCACHE_SRAM_REGION ( 11 )
63 #endif
64 
65 #define MPU_REGION_VALID ( 0x10 )
66 #define MPU_REGION_ENABLE ( 0x01 )
67 #define MPU_REGION_DISABLE ( 0x0 )
68 
69 #define MPU_ENABLE ( 0x1 << MPU_CTRL_ENABLE_Pos)
70 #define MPU_HFNMIENA ( 0x1 << MPU_CTRL_HFNMIENA_Pos )
71 #define MPU_PRIVDEFENA ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos )
72 
73 
74 #define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos )
75 #define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos )
76 #define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos )
77 
78 #define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos )
79 
80 #define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos )
81 #define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos )
82 #define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos )
83 #define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos )
84 #define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos )
85 #define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos )
86 #define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos )
87 #define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos )
88 
89 #define MPU_TEX_B000 ( 0x01 << MPU_RASR_TEX_Pos )
90 #define MPU_TEX_B001 ( 0x01 << MPU_RASR_TEX_Pos )
91 #define MPU_TEX_B010 ( 0x01 << MPU_RASR_TEX_Pos )
92 #define MPU_TEX_B011 ( 0x01 << MPU_RASR_TEX_Pos )
93 #define MPU_TEX_B100 ( 0x01 << MPU_RASR_TEX_Pos )
94 #define MPU_TEX_B101 ( 0x01 << MPU_RASR_TEX_Pos )
95 #define MPU_TEX_B110 ( 0x01 << MPU_RASR_TEX_Pos )
96 #define MPU_TEX_B111 ( 0x01 << MPU_RASR_TEX_Pos )
97 
98 #define SHAREABLE 1
99 #define NON_SHAREABLE 0
100 
101 #define INNER_NORMAL_WB_RWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
102 #define INNER_NORMAL_WB_NWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
103 #define STRONGLY_ORDERED_SHAREABLE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos )) // DO not care //
104 #define SHAREABLE_DEVICE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos )) // DO not care //
105 
106 
107 /* Default memory map
108  Address range Memory region Memory type Shareability Cache policy
109  0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT
110  0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA
111  0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -
112  0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA
113  0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT
114  0xA0000000- 0xBFFFFFFF Device Device Shareable
115  0xC0000000- 0xDFFFFFFF Device Device Non Shareable
116  0xE0000000- 0xFFFFFFFF System - -
117  */
118 
119 /********* IFLASH memory macros *********************/
120 #define ITCM_START_ADDRESS 0x00000000UL
121 #define ITCM_END_ADDRESS 0x003FFFFFUL
122 #define IFLASH_START_ADDRESS 0x00400000UL
123 #define IFLASH_END_ADDRESS 0x005FFFFFUL
124 
125 
126 #define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
127 #define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF)
128 
129 #define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1)
130 #define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
131 
132 /**************** DTCM *******************************/
133 #define DTCM_START_ADDRESS 0x20000000UL
134 #define DTCM_END_ADDRESS 0x203FFFFFUL
135 
136 
137 /******* SRAM memory macros ***************************/
138 
139 #define SRAM_START_ADDRESS 0x20400000UL
140 #define SRAM_END_ADDRESS 0x2045FFFFUL
141 
142 #if defined MPU_HAS_NOCACHE_REGION
143 #define NOCACHE_SRAM_REGION_SIZE 0x1000
144 #endif
145 
146 /* Regions should be a 2^(N+1) where 4 < N < 31 */
147 #define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
148 #define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
149 
150 #if defined MPU_HAS_NOCACHE_REGION
151 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
152 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE ) // (2^17) 128 - 0x1000 KB
153 #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
154 #define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS )
155 #else
156 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
157 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB
158 #endif
159 /************** Peripherals memory region macros ********/
160 #define PERIPHERALS_START_ADDRESS 0x40000000UL
161 #define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
162 
163 /******* Ext EBI memory macros ***************************/
164 #define EXT_EBI_START_ADDRESS 0x60000000UL
165 #define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL
166 
167 /******* Ext-SRAM memory macros ***************************/
168 #define SDRAM_START_ADDRESS 0x70000000UL
169 #define SDRAM_END_ADDRESS 0x7FFFFFFFUL
170 
171 /******* QSPI macros ***************************/
172 #define QSPI_START_ADDRESS 0x80000000UL
173 #define QSPI_END_ADDRESS 0x9FFFFFFFUL
174 
175 /************** USBHS_RAM region macros ******************/
176 #define USBHSRAM_START_ADDRESS 0xA0100000UL
177 #define USBHSRAM_END_ADDRESS 0xA01FFFFFUL
178 
179 /*----------------------------------------------------------------------------
180  * Export functions
181  *----------------------------------------------------------------------------*/
182 void mpu_enable(uint32_t dw_mpu_enable);
183 void mpu_set_region(uint32_t dw_region_base_addr, uint32_t dw_region_attr);
184 void mpu_set_region_num(uint32_t dw_region_num);
185 void mpu_disable_region(void);
186 uint32_t mpu_cal_mpu_region_size(uint32_t dw_actual_size_in_bytes);
187 void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr);
188 
189 #endif /* #ifndef _MPU_H_ */
mpu_update_regions
void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr)
Update MPU regions.
Definition: mpu.c:149
mpu_disable_region
void mpu_disable_region(void)
Disable the current active region.
Definition: mpu.c:105
mpu_set_region
void mpu_set_region(uint32_t dw_region_base_addr, uint32_t dw_region_attr)
Setup a memory region.
Definition: mpu.c:116
compiler.h
Commonly used includes, types and macros.
mpu_cal_mpu_region_size
uint32_t mpu_cal_mpu_region_size(uint32_t dw_actual_size_in_bytes)
Calculate region size for the RASR.
Definition: mpu.c:126
mpu_enable
void mpu_enable(uint32_t dw_mpu_enable)
Enables the MPU module.
Definition: mpu.c:87
mpu_set_region_num
void mpu_set_region_num(uint32_t dw_region_num)
Set active memory region.
Definition: mpu.c:97

inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04