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Macros
#define	REG_SMC_CYCLE0 ((__IO uint32_t)0x40080008U)
	(SMC) SMC Cycle Register (CS_number = 0) More...

#define	REG_SMC_CYCLE1 ((__IO uint32_t)0x40080018U)
	(SMC) SMC Cycle Register (CS_number = 1) More...

#define	REG_SMC_CYCLE2 ((__IO uint32_t)0x40080028U)
	(SMC) SMC Cycle Register (CS_number = 2) More...

#define	REG_SMC_CYCLE3 ((__IO uint32_t)0x40080038U)
	(SMC) SMC Cycle Register (CS_number = 3) More...

#define	REG_SMC_KEY1 ((__O uint32_t)0x40080084U)
	(SMC) SMC Off-Chip Memory Scrambling KEY1 Register More...

#define	REG_SMC_KEY2 ((__O uint32_t)0x40080088U)
	(SMC) SMC Off-Chip Memory Scrambling KEY2 Register More...

#define	REG_SMC_MODE0 ((__IO uint32_t)0x4008000CU)
	(SMC) SMC Mode Register (CS_number = 0) More...

#define	REG_SMC_MODE1 ((__IO uint32_t)0x4008001CU)
	(SMC) SMC Mode Register (CS_number = 1) More...

#define	REG_SMC_MODE2 ((__IO uint32_t)0x4008002CU)
	(SMC) SMC Mode Register (CS_number = 2) More...

#define	REG_SMC_MODE3 ((__IO uint32_t)0x4008003CU)
	(SMC) SMC Mode Register (CS_number = 3) More...

#define	REG_SMC_OCMS ((__IO uint32_t)0x40080080U)
	(SMC) SMC Off-Chip Memory Scrambling Register More...

#define	REG_SMC_PULSE0 ((__IO uint32_t)0x40080004U)
	(SMC) SMC Pulse Register (CS_number = 0) More...

#define	REG_SMC_PULSE1 ((__IO uint32_t)0x40080014U)
	(SMC) SMC Pulse Register (CS_number = 1) More...

#define	REG_SMC_PULSE2 ((__IO uint32_t)0x40080024U)
	(SMC) SMC Pulse Register (CS_number = 2) More...

#define	REG_SMC_PULSE3 ((__IO uint32_t)0x40080034U)
	(SMC) SMC Pulse Register (CS_number = 3) More...

#define	REG_SMC_SETUP0 ((__IO uint32_t)0x40080000U)
	(SMC) SMC Setup Register (CS_number = 0) More...

#define	REG_SMC_SETUP1 ((__IO uint32_t)0x40080010U)
	(SMC) SMC Setup Register (CS_number = 1) More...

#define	REG_SMC_SETUP2 ((__IO uint32_t)0x40080020U)
	(SMC) SMC Setup Register (CS_number = 2) More...

#define	REG_SMC_SETUP3 ((__IO uint32_t)0x40080030U)
	(SMC) SMC Setup Register (CS_number = 3) More...

#define	REG_SMC_VERSION ((__I uint32_t)0x400800FCU)
	(SMC) SMC Version Register More...

#define	REG_SMC_WPMR ((__IO uint32_t)0x400800E4U)
	(SMC) SMC Write Protection Mode Register More...

#define	REG_SMC_WPSR ((__I uint32_t)0x400800E8U)
	(SMC) SMC Write Protection Status Register More...

Detailed Description

Definition in file instance/smc.h.

Macro Definition Documentation

◆ REG_SMC_CYCLE0

#define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U)

(SMC) SMC Cycle Register (CS_number = 0)

Definition at line 65 of file instance/smc.h.

◆ REG_SMC_CYCLE1

#define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U)

(SMC) SMC Cycle Register (CS_number = 1)

Definition at line 69 of file instance/smc.h.

◆ REG_SMC_CYCLE2

#define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U)

(SMC) SMC Cycle Register (CS_number = 2)

Definition at line 73 of file instance/smc.h.

◆ REG_SMC_CYCLE3

#define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U)

(SMC) SMC Cycle Register (CS_number = 3)

Definition at line 77 of file instance/smc.h.

◆ REG_SMC_KEY1

#define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U)

(SMC) SMC Off-Chip Memory Scrambling KEY1 Register

Definition at line 80 of file instance/smc.h.

◆ REG_SMC_KEY2

#define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U)

(SMC) SMC Off-Chip Memory Scrambling KEY2 Register

Definition at line 81 of file instance/smc.h.

◆ REG_SMC_MODE0

#define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU)

(SMC) SMC Mode Register (CS_number = 0)

Definition at line 66 of file instance/smc.h.

◆ REG_SMC_MODE1

#define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU)

(SMC) SMC Mode Register (CS_number = 1)

Definition at line 70 of file instance/smc.h.

◆ REG_SMC_MODE2

#define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU)

(SMC) SMC Mode Register (CS_number = 2)

Definition at line 74 of file instance/smc.h.

◆ REG_SMC_MODE3

#define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU)

(SMC) SMC Mode Register (CS_number = 3)

Definition at line 78 of file instance/smc.h.

◆ REG_SMC_OCMS

#define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U)

(SMC) SMC Off-Chip Memory Scrambling Register

Definition at line 79 of file instance/smc.h.

◆ REG_SMC_PULSE0

#define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U)

(SMC) SMC Pulse Register (CS_number = 0)

Definition at line 64 of file instance/smc.h.

◆ REG_SMC_PULSE1

#define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U)

(SMC) SMC Pulse Register (CS_number = 1)

Definition at line 68 of file instance/smc.h.

◆ REG_SMC_PULSE2

#define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U)

(SMC) SMC Pulse Register (CS_number = 2)

Definition at line 72 of file instance/smc.h.

◆ REG_SMC_PULSE3

#define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U)

(SMC) SMC Pulse Register (CS_number = 3)

Definition at line 76 of file instance/smc.h.

◆ REG_SMC_SETUP0

#define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U)

(SMC) SMC Setup Register (CS_number = 0)

Definition at line 63 of file instance/smc.h.

◆ REG_SMC_SETUP1

#define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U)

(SMC) SMC Setup Register (CS_number = 1)

Definition at line 67 of file instance/smc.h.

◆ REG_SMC_SETUP2

#define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U)

(SMC) SMC Setup Register (CS_number = 2)

Definition at line 71 of file instance/smc.h.

◆ REG_SMC_SETUP3

#define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U)

(SMC) SMC Setup Register (CS_number = 3)

Definition at line 75 of file instance/smc.h.

◆ REG_SMC_VERSION

#define REG_SMC_VERSION (*(__I uint32_t*)0x400800FCU)

(SMC) SMC Version Register

Definition at line 84 of file instance/smc.h.

◆ REG_SMC_WPMR

#define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U)

(SMC) SMC Write Protection Mode Register

Definition at line 82 of file instance/smc.h.

◆ REG_SMC_WPSR

#define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U)

(SMC) SMC Write Protection Status Register

Definition at line 83 of file instance/smc.h.

Macros