Classes
struct	I2sc
	I2sc hardware registers. More...

Macros
#define	I2SC_CR_CKDIS (0x1u << 3)
	(I2SC_CR) Clocks Disable More...

#define	I2SC_CR_CKEN (0x1u << 2)
	(I2SC_CR) Clocks Enable More...

#define	I2SC_CR_RXDIS (0x1u << 1)
	(I2SC_CR) Receiver Disable More...

#define	I2SC_CR_RXEN (0x1u << 0)
	(I2SC_CR) Receiver Enable More...

#define	I2SC_CR_SWRST (0x1u << 7)
	(I2SC_CR) Software Reset More...

#define	I2SC_CR_TXDIS (0x1u << 5)
	(I2SC_CR) Transmitter Disable More...

#define	I2SC_CR_TXEN (0x1u << 4)
	(I2SC_CR) Transmitter Enable More...

#define	I2SC_IDR_RXOR (0x1u << 2)
	(I2SC_IDR) Receiver Overrun Interrupt Disable More...

#define	I2SC_IDR_RXRDY (0x1u << 1)
	(I2SC_IDR) Receiver Ready Interrupt Disable More...

#define	I2SC_IDR_TXRDY (0x1u << 5)
	(I2SC_IDR) Transmit Ready Interrupt Disable More...

#define	I2SC_IDR_TXUR (0x1u << 6)
	(I2SC_IDR) Transmit Underflow Interrupt Disable More...

#define	I2SC_IER_RXOR (0x1u << 2)
	(I2SC_IER) Receiver Overrun Interrupt Enable More...

#define	I2SC_IER_RXRDY (0x1u << 1)
	(I2SC_IER) Receiver Ready Interrupt Enable More...

#define	I2SC_IER_TXRDY (0x1u << 5)
	(I2SC_IER) Transmit Ready Interrupt Enable More...

#define	I2SC_IER_TXUR (0x1u << 6)
	(I2SC_IER) Transmit Underflow Interrupt Enable More...

#define	I2SC_IMR_RXOR (0x1u << 2)
	(I2SC_IMR) Receiver Overrun Interrupt Disable More...

#define	I2SC_IMR_RXRDY (0x1u << 1)
	(I2SC_IMR) Receiver Ready Interrupt Disable More...

#define	I2SC_IMR_TXRDY (0x1u << 5)
	(I2SC_IMR) Transmit Ready Interrupt Disable More...

#define	I2SC_IMR_TXUR (0x1u << 6)
	(I2SC_IMR) Transmit Underflow Interrupt Disable More...

#define	I2SC_MR_DATALENGTH(value) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)))

#define	I2SC_MR_DATALENGTH_16_BITS (0x4u << 2)
	(I2SC_MR) Data length is set to 16 bits More...

#define	I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2)
	(I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. More...

#define	I2SC_MR_DATALENGTH_18_BITS (0x3u << 2)
	(I2SC_MR) Data length is set to 18 bits More...

#define	I2SC_MR_DATALENGTH_20_BITS (0x2u << 2)
	(I2SC_MR) Data length is set to 20 bits More...

#define	I2SC_MR_DATALENGTH_24_BITS (0x1u << 2)
	(I2SC_MR) Data length is set to 24 bits More...

#define	I2SC_MR_DATALENGTH_32_BITS (0x0u << 2)
	(I2SC_MR) Data length is set to 32 bits More...

#define	I2SC_MR_DATALENGTH_8_BITS (0x6u << 2)
	(I2SC_MR) Data length is set to 8 bits More...

#define	I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2)
	(I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. More...

#define	I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos)
	(I2SC_MR) Data Word Length More...

#define	I2SC_MR_DATALENGTH_Pos 2

#define	I2SC_MR_FORMAT(value) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos)))

#define	I2SC_MR_FORMAT_I2S (0x0u << 6)
	(I2SC_MR) I2S format, stereo with I2SWS low for left channel, and MSB of sample starting one I2SCK period after I2SWS edge More...

#define	I2SC_MR_FORMAT_LJ (0x1u << 6)
	(I2SC_MR) Left-justified format, stereo with I2SWS high for left channel, and MSB of sample starting on I2SWS edge More...

#define	I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos)
	(I2SC_MR) Data Format More...

#define	I2SC_MR_FORMAT_Pos 6

#define	I2SC_MR_IMCKDIV(value) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)))

#define	I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos)
	(I2SC_MR) Selected Clock to I2SC Master Clock Ratio More...

#define	I2SC_MR_IMCKDIV_Pos 16

#define	I2SC_MR_IMCKFS(value) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)))

#define	I2SC_MR_IMCKFS_M2SF1024 (0x1Fu << 24)
	(I2SC_MR) Sample frequency ratio set to 1024 More...

#define	I2SC_MR_IMCKFS_M2SF128 (0x3u << 24)
	(I2SC_MR) Sample frequency ratio set to 128 More...

#define	I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24)
	(I2SC_MR) Sample frequency ratio set to 1536 More...

#define	I2SC_MR_IMCKFS_M2SF192 (0x5u << 24)
	(I2SC_MR) Sample frequency ratio set to 192 More...

#define	I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24)
	(I2SC_MR) Sample frequency ratio set to 2048 More...

#define	I2SC_MR_IMCKFS_M2SF256 (0x7u << 24)
	(I2SC_MR) Sample frequency ratio set to 256 More...

#define	I2SC_MR_IMCKFS_M2SF32 (0x0u << 24)
	(I2SC_MR) Sample frequency ratio set to 32 More...

#define	I2SC_MR_IMCKFS_M2SF384 (0xBu << 24)
	(I2SC_MR) Sample frequency ratio set to 384 More...

#define	I2SC_MR_IMCKFS_M2SF512 (0xFu << 24)
	(I2SC_MR) Sample frequency ratio set to 512 More...

#define	I2SC_MR_IMCKFS_M2SF64 (0x1u << 24)
	(I2SC_MR) Sample frequency ratio set to 64 More...

#define	I2SC_MR_IMCKFS_M2SF768 (0x17u << 24)
	(I2SC_MR) Sample frequency ratio set to 768 More...

#define	I2SC_MR_IMCKFS_M2SF96 (0x2u << 24)
	(I2SC_MR) Sample frequency ratio set to 96 More...

#define	I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos)
	(I2SC_MR) Master Clock to fs Ratio More...

#define	I2SC_MR_IMCKFS_Pos 24

#define	I2SC_MR_IMCKMODE (0x1u << 30)
	(I2SC_MR) Master Clock Mode More...

#define	I2SC_MR_IWS (0x1u << 31)
	(I2SC_MR) I2SWS Slot Width More...

#define	I2SC_MR_MODE (0x1u << 0)
	(I2SC_MR) Inter-IC Sound Controller Mode More...

#define	I2SC_MR_MODE_MASTER (0x1u << 0)
	(I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set. More...

#define	I2SC_MR_MODE_SLAVE (0x0u << 0)
	(I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. More...

#define	I2SC_MR_RXDMA (0x1u << 9)
	(I2SC_MR) Single or Multiple DMA Controller Channels for Receiver More...

#define	I2SC_MR_RXLOOP (0x1u << 10)
	(I2SC_MR) Loop-back Test Mode More...

#define	I2SC_MR_RXMONO (0x1u << 8)
	(I2SC_MR) Receive Mono More...

#define	I2SC_MR_TXDMA (0x1u << 13)
	(I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter More...

#define	I2SC_MR_TXMONO (0x1u << 12)
	(I2SC_MR) Transmit Mono More...

#define	I2SC_MR_TXSAME (0x1u << 14)
	(I2SC_MR) Transmit Data when Underrun More...

#define	I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos)
	(I2SC_RHR) Receiver Holding Register More...

#define	I2SC_RHR_RHR_Pos 0

#define	I2SC_SCR_RXOR (0x1u << 2)
	(I2SC_SCR) Receive Overrun Status Clear More...

#define	I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)))

#define	I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos)
	(I2SC_SCR) Receive Overrun Per Channel Status Clear More...

#define	I2SC_SCR_RXORCH_Pos 8

#define	I2SC_SCR_TXUR (0x1u << 6)
	(I2SC_SCR) Transmit Underrun Status Clear More...

#define	I2SC_SCR_TXURCH(value) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)))

#define	I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos)
	(I2SC_SCR) Transmit Underrun Per Channel Status Clear More...

#define	I2SC_SCR_TXURCH_Pos 20

#define	I2SC_SR_RXEN (0x1u << 0)
	(I2SC_SR) Receiver Enabled More...

#define	I2SC_SR_RXOR (0x1u << 2)
	(I2SC_SR) Receive Overrun More...

#define	I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos)
	(I2SC_SR) Receive Overrun Channel More...

#define	I2SC_SR_RXORCH_Pos 8

#define	I2SC_SR_RXRDY (0x1u << 1)
	(I2SC_SR) Receive Ready More...

#define	I2SC_SR_TXEN (0x1u << 4)
	(I2SC_SR) Transmitter Enabled More...

#define	I2SC_SR_TXRDY (0x1u << 5)
	(I2SC_SR) Transmit Ready More...

#define	I2SC_SR_TXUR (0x1u << 6)
	(I2SC_SR) Transmit Underrun More...

#define	I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos)
	(I2SC_SR) Transmit Underrun Channel More...

#define	I2SC_SR_TXURCH_Pos 20

#define	I2SC_SSR_RXOR (0x1u << 2)
	(I2SC_SSR) Receive Overrun Status Set More...

#define	I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)))

#define	I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos)
	(I2SC_SSR) Receive Overrun Per Channel Status Set More...

#define	I2SC_SSR_RXORCH_Pos 8

#define	I2SC_SSR_TXUR (0x1u << 6)
	(I2SC_SSR) Transmit Underrun Status Set More...

#define	I2SC_SSR_TXURCH(value) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)))

#define	I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos)
	(I2SC_SSR) Transmit Underrun Per Channel Status Set More...

#define	I2SC_SSR_TXURCH_Pos 20

#define	I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)))

#define	I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos)
	(I2SC_THR) Transmitter Holding Register More...

#define	I2SC_THR_THR_Pos 0

#define	I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos)
	(I2SC_VERSION) Metal Fix Number More...

#define	I2SC_VERSION_MFN_Pos 16

#define	I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos)
	(I2SC_VERSION) Version of the Hardware Module More...

#define	I2SC_VERSION_VERSION_Pos 0

Detailed Description

SOFTWARE API DEFINITION FOR Inter-IC Sound Controller

Macro Definition Documentation

◆ I2SC_CR_CKDIS

#define I2SC_CR_CKDIS (0x1u << 3)

(I2SC_CR) Clocks Disable

Definition at line 64 of file i2sc.h.

◆ I2SC_CR_CKEN

#define I2SC_CR_CKEN (0x1u << 2)

(I2SC_CR) Clocks Enable

Definition at line 63 of file i2sc.h.

◆ I2SC_CR_RXDIS

#define I2SC_CR_RXDIS (0x1u << 1)

(I2SC_CR) Receiver Disable

Definition at line 62 of file i2sc.h.

◆ I2SC_CR_RXEN

#define I2SC_CR_RXEN (0x1u << 0)

(I2SC_CR) Receiver Enable

Definition at line 61 of file i2sc.h.

◆ I2SC_CR_SWRST

#define I2SC_CR_SWRST (0x1u << 7)

(I2SC_CR) Software Reset

Definition at line 67 of file i2sc.h.

◆ I2SC_CR_TXDIS

#define I2SC_CR_TXDIS (0x1u << 5)

(I2SC_CR) Transmitter Disable

Definition at line 66 of file i2sc.h.

◆ I2SC_CR_TXEN

#define I2SC_CR_TXEN (0x1u << 4)

(I2SC_CR) Transmitter Enable

Definition at line 65 of file i2sc.h.

◆ I2SC_IDR_RXOR

#define I2SC_IDR_RXOR (0x1u << 2)

(I2SC_IDR) Receiver Overrun Interrupt Disable

Definition at line 150 of file i2sc.h.

◆ I2SC_IDR_RXRDY

#define I2SC_IDR_RXRDY (0x1u << 1)

(I2SC_IDR) Receiver Ready Interrupt Disable

Definition at line 149 of file i2sc.h.

◆ I2SC_IDR_TXRDY

#define I2SC_IDR_TXRDY (0x1u << 5)

(I2SC_IDR) Transmit Ready Interrupt Disable

Definition at line 151 of file i2sc.h.

◆ I2SC_IDR_TXUR

#define I2SC_IDR_TXUR (0x1u << 6)

(I2SC_IDR) Transmit Underflow Interrupt Disable

Definition at line 152 of file i2sc.h.

◆ I2SC_IER_RXOR

#define I2SC_IER_RXOR (0x1u << 2)

(I2SC_IER) Receiver Overrun Interrupt Enable

Definition at line 145 of file i2sc.h.

◆ I2SC_IER_RXRDY

#define I2SC_IER_RXRDY (0x1u << 1)

(I2SC_IER) Receiver Ready Interrupt Enable

Definition at line 144 of file i2sc.h.

◆ I2SC_IER_TXRDY

#define I2SC_IER_TXRDY (0x1u << 5)

(I2SC_IER) Transmit Ready Interrupt Enable

Definition at line 146 of file i2sc.h.

◆ I2SC_IER_TXUR

#define I2SC_IER_TXUR (0x1u << 6)

(I2SC_IER) Transmit Underflow Interrupt Enable

Definition at line 147 of file i2sc.h.

◆ I2SC_IMR_RXOR

#define I2SC_IMR_RXOR (0x1u << 2)

(I2SC_IMR) Receiver Overrun Interrupt Disable

Definition at line 155 of file i2sc.h.

◆ I2SC_IMR_RXRDY

#define I2SC_IMR_RXRDY (0x1u << 1)

(I2SC_IMR) Receiver Ready Interrupt Disable

Definition at line 154 of file i2sc.h.

◆ I2SC_IMR_TXRDY

#define I2SC_IMR_TXRDY (0x1u << 5)

(I2SC_IMR) Transmit Ready Interrupt Disable

Definition at line 156 of file i2sc.h.

◆ I2SC_IMR_TXUR

#define I2SC_IMR_TXUR (0x1u << 6)

(I2SC_IMR) Transmit Underflow Interrupt Disable

Definition at line 157 of file i2sc.h.

◆ I2SC_MR_DATALENGTH

#define I2SC_MR_DATALENGTH ( value ) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)))

Definition at line 74 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_16_BITS

#define I2SC_MR_DATALENGTH_16_BITS (0x4u << 2)

(I2SC_MR) Data length is set to 16 bits

Definition at line 79 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_16_BITS_COMPACT

#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2)

(I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.

Definition at line 80 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_18_BITS

#define I2SC_MR_DATALENGTH_18_BITS (0x3u << 2)

(I2SC_MR) Data length is set to 18 bits

Definition at line 78 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_20_BITS

#define I2SC_MR_DATALENGTH_20_BITS (0x2u << 2)

(I2SC_MR) Data length is set to 20 bits

Definition at line 77 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_24_BITS

#define I2SC_MR_DATALENGTH_24_BITS (0x1u << 2)

(I2SC_MR) Data length is set to 24 bits

Definition at line 76 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_32_BITS

#define I2SC_MR_DATALENGTH_32_BITS (0x0u << 2)

(I2SC_MR) Data length is set to 32 bits

Definition at line 75 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_8_BITS

#define I2SC_MR_DATALENGTH_8_BITS (0x6u << 2)

(I2SC_MR) Data length is set to 8 bits

Definition at line 81 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_8_BITS_COMPACT

#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2)

(I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.

Definition at line 82 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_Msk

#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos)

(I2SC_MR) Data Word Length

Definition at line 73 of file i2sc.h.

◆ I2SC_MR_DATALENGTH_Pos

#define I2SC_MR_DATALENGTH_Pos 2

Definition at line 72 of file i2sc.h.

◆ I2SC_MR_FORMAT

#define I2SC_MR_FORMAT ( value ) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos)))

Definition at line 85 of file i2sc.h.

◆ I2SC_MR_FORMAT_I2S

#define I2SC_MR_FORMAT_I2S (0x0u << 6)

(I2SC_MR) I2S format, stereo with I2SWS low for left channel, and MSB of sample starting one I2SCK period after I2SWS edge

Definition at line 86 of file i2sc.h.

◆ I2SC_MR_FORMAT_LJ

#define I2SC_MR_FORMAT_LJ (0x1u << 6)

(I2SC_MR) Left-justified format, stereo with I2SWS high for left channel, and MSB of sample starting on I2SWS edge

Definition at line 87 of file i2sc.h.

◆ I2SC_MR_FORMAT_Msk

#define I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos)

(I2SC_MR) Data Format

Definition at line 84 of file i2sc.h.

◆ I2SC_MR_FORMAT_Pos

#define I2SC_MR_FORMAT_Pos 6

Definition at line 83 of file i2sc.h.

◆ I2SC_MR_IMCKDIV

#define I2SC_MR_IMCKDIV ( value ) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)))

Definition at line 96 of file i2sc.h.

◆ I2SC_MR_IMCKDIV_Msk

#define I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos)

(I2SC_MR) Selected Clock to I2SC Master Clock Ratio

Definition at line 95 of file i2sc.h.

◆ I2SC_MR_IMCKDIV_Pos

#define I2SC_MR_IMCKDIV_Pos 16

Definition at line 94 of file i2sc.h.

◆ I2SC_MR_IMCKFS

#define I2SC_MR_IMCKFS ( value ) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)))

Definition at line 99 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF1024

#define I2SC_MR_IMCKFS_M2SF1024 (0x1Fu << 24)

(I2SC_MR) Sample frequency ratio set to 1024

Definition at line 109 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF128

#define I2SC_MR_IMCKFS_M2SF128 (0x3u << 24)

(I2SC_MR) Sample frequency ratio set to 128

Definition at line 103 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF1536

#define I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24)

(I2SC_MR) Sample frequency ratio set to 1536

Definition at line 110 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF192

#define I2SC_MR_IMCKFS_M2SF192 (0x5u << 24)

(I2SC_MR) Sample frequency ratio set to 192

Definition at line 104 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF2048

#define I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24)

(I2SC_MR) Sample frequency ratio set to 2048

Definition at line 111 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF256

#define I2SC_MR_IMCKFS_M2SF256 (0x7u << 24)

(I2SC_MR) Sample frequency ratio set to 256

Definition at line 105 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF32

#define I2SC_MR_IMCKFS_M2SF32 (0x0u << 24)

(I2SC_MR) Sample frequency ratio set to 32

Definition at line 100 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF384

#define I2SC_MR_IMCKFS_M2SF384 (0xBu << 24)

(I2SC_MR) Sample frequency ratio set to 384

Definition at line 106 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF512

#define I2SC_MR_IMCKFS_M2SF512 (0xFu << 24)

(I2SC_MR) Sample frequency ratio set to 512

Definition at line 107 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF64

#define I2SC_MR_IMCKFS_M2SF64 (0x1u << 24)

(I2SC_MR) Sample frequency ratio set to 64

Definition at line 101 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF768

#define I2SC_MR_IMCKFS_M2SF768 (0x17u << 24)

(I2SC_MR) Sample frequency ratio set to 768

Definition at line 108 of file i2sc.h.

◆ I2SC_MR_IMCKFS_M2SF96

#define I2SC_MR_IMCKFS_M2SF96 (0x2u << 24)

(I2SC_MR) Sample frequency ratio set to 96

Definition at line 102 of file i2sc.h.

◆ I2SC_MR_IMCKFS_Msk

#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos)

(I2SC_MR) Master Clock to fs Ratio

Definition at line 98 of file i2sc.h.

◆ I2SC_MR_IMCKFS_Pos

#define I2SC_MR_IMCKFS_Pos 24

Definition at line 97 of file i2sc.h.

◆ I2SC_MR_IMCKMODE

#define I2SC_MR_IMCKMODE (0x1u << 30)

(I2SC_MR) Master Clock Mode

Definition at line 112 of file i2sc.h.

◆ I2SC_MR_IWS

#define I2SC_MR_IWS (0x1u << 31)

(I2SC_MR) I2SWS Slot Width

Definition at line 113 of file i2sc.h.

◆ I2SC_MR_MODE

#define I2SC_MR_MODE (0x1u << 0)

(I2SC_MR) Inter-IC Sound Controller Mode

Definition at line 69 of file i2sc.h.

◆ I2SC_MR_MODE_MASTER

#define I2SC_MR_MODE_MASTER (0x1u << 0)

(I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set.

Definition at line 71 of file i2sc.h.

◆ I2SC_MR_MODE_SLAVE

#define I2SC_MR_MODE_SLAVE (0x0u << 0)

(I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization.

Definition at line 70 of file i2sc.h.

◆ I2SC_MR_RXDMA

#define I2SC_MR_RXDMA (0x1u << 9)

(I2SC_MR) Single or Multiple DMA Controller Channels for Receiver

Definition at line 89 of file i2sc.h.

◆ I2SC_MR_RXLOOP

#define I2SC_MR_RXLOOP (0x1u << 10)

(I2SC_MR) Loop-back Test Mode

Definition at line 90 of file i2sc.h.

◆ I2SC_MR_RXMONO

#define I2SC_MR_RXMONO (0x1u << 8)

(I2SC_MR) Receive Mono

Definition at line 88 of file i2sc.h.

◆ I2SC_MR_TXDMA

#define I2SC_MR_TXDMA (0x1u << 13)

(I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter

Definition at line 92 of file i2sc.h.

◆ I2SC_MR_TXMONO

#define I2SC_MR_TXMONO (0x1u << 12)

(I2SC_MR) Transmit Mono

Definition at line 91 of file i2sc.h.

◆ I2SC_MR_TXSAME

#define I2SC_MR_TXSAME (0x1u << 14)

(I2SC_MR) Transmit Data when Underrun

Definition at line 93 of file i2sc.h.

◆ I2SC_RHR_RHR_Msk

#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos)

(I2SC_RHR) Receiver Holding Register

Definition at line 160 of file i2sc.h.

◆ I2SC_RHR_RHR_Pos

#define I2SC_RHR_RHR_Pos 0

Definition at line 159 of file i2sc.h.

◆ I2SC_SCR_RXOR

#define I2SC_SCR_RXOR (0x1u << 2)

(I2SC_SCR) Receive Overrun Status Clear

Definition at line 126 of file i2sc.h.

◆ I2SC_SCR_RXORCH

#define I2SC_SCR_RXORCH ( value ) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)))

Definition at line 130 of file i2sc.h.

◆ I2SC_SCR_RXORCH_Msk

#define I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos)

(I2SC_SCR) Receive Overrun Per Channel Status Clear

Definition at line 129 of file i2sc.h.

◆ I2SC_SCR_RXORCH_Pos

#define I2SC_SCR_RXORCH_Pos 8

Definition at line 128 of file i2sc.h.

◆ I2SC_SCR_TXUR

#define I2SC_SCR_TXUR (0x1u << 6)

(I2SC_SCR) Transmit Underrun Status Clear

Definition at line 127 of file i2sc.h.

◆ I2SC_SCR_TXURCH

#define I2SC_SCR_TXURCH ( value ) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)))

Definition at line 133 of file i2sc.h.

◆ I2SC_SCR_TXURCH_Msk

#define I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos)

(I2SC_SCR) Transmit Underrun Per Channel Status Clear

Definition at line 132 of file i2sc.h.

◆ I2SC_SCR_TXURCH_Pos

#define I2SC_SCR_TXURCH_Pos 20

Definition at line 131 of file i2sc.h.

◆ I2SC_SR_RXEN

#define I2SC_SR_RXEN (0x1u << 0)

(I2SC_SR) Receiver Enabled

Definition at line 115 of file i2sc.h.

◆ I2SC_SR_RXOR

#define I2SC_SR_RXOR (0x1u << 2)

(I2SC_SR) Receive Overrun

Definition at line 117 of file i2sc.h.

◆ I2SC_SR_RXORCH_Msk

#define I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos)

(I2SC_SR) Receive Overrun Channel

Definition at line 122 of file i2sc.h.

◆ I2SC_SR_RXORCH_Pos

#define I2SC_SR_RXORCH_Pos 8

Definition at line 121 of file i2sc.h.

◆ I2SC_SR_RXRDY

#define I2SC_SR_RXRDY (0x1u << 1)

(I2SC_SR) Receive Ready

Definition at line 116 of file i2sc.h.

◆ I2SC_SR_TXEN

#define I2SC_SR_TXEN (0x1u << 4)

(I2SC_SR) Transmitter Enabled

Definition at line 118 of file i2sc.h.

◆ I2SC_SR_TXRDY

#define I2SC_SR_TXRDY (0x1u << 5)

(I2SC_SR) Transmit Ready

Definition at line 119 of file i2sc.h.

◆ I2SC_SR_TXUR

#define I2SC_SR_TXUR (0x1u << 6)

(I2SC_SR) Transmit Underrun

Definition at line 120 of file i2sc.h.

◆ I2SC_SR_TXURCH_Msk

#define I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos)

(I2SC_SR) Transmit Underrun Channel

Definition at line 124 of file i2sc.h.

◆ I2SC_SR_TXURCH_Pos

#define I2SC_SR_TXURCH_Pos 20

Definition at line 123 of file i2sc.h.

◆ I2SC_SSR_RXOR

#define I2SC_SSR_RXOR (0x1u << 2)

(I2SC_SSR) Receive Overrun Status Set

Definition at line 135 of file i2sc.h.

◆ I2SC_SSR_RXORCH

#define I2SC_SSR_RXORCH ( value ) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)))

Definition at line 139 of file i2sc.h.

◆ I2SC_SSR_RXORCH_Msk

#define I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos)

(I2SC_SSR) Receive Overrun Per Channel Status Set

Definition at line 138 of file i2sc.h.

◆ I2SC_SSR_RXORCH_Pos

#define I2SC_SSR_RXORCH_Pos 8

Definition at line 137 of file i2sc.h.

◆ I2SC_SSR_TXUR

#define I2SC_SSR_TXUR (0x1u << 6)

(I2SC_SSR) Transmit Underrun Status Set

Definition at line 136 of file i2sc.h.

◆ I2SC_SSR_TXURCH

#define I2SC_SSR_TXURCH ( value ) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)))

Definition at line 142 of file i2sc.h.

◆ I2SC_SSR_TXURCH_Msk

#define I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos)

(I2SC_SSR) Transmit Underrun Per Channel Status Set

Definition at line 141 of file i2sc.h.

◆ I2SC_SSR_TXURCH_Pos

#define I2SC_SSR_TXURCH_Pos 20

Definition at line 140 of file i2sc.h.

◆ I2SC_THR_THR

#define I2SC_THR_THR ( value ) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)))

Definition at line 164 of file i2sc.h.

◆ I2SC_THR_THR_Msk

#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos)

(I2SC_THR) Transmitter Holding Register

Definition at line 163 of file i2sc.h.

◆ I2SC_THR_THR_Pos

#define I2SC_THR_THR_Pos 0

Definition at line 162 of file i2sc.h.

◆ I2SC_VERSION_MFN_Msk

#define I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos)

(I2SC_VERSION) Metal Fix Number

Definition at line 169 of file i2sc.h.

◆ I2SC_VERSION_MFN_Pos

#define I2SC_VERSION_MFN_Pos 16

Definition at line 168 of file i2sc.h.

◆ I2SC_VERSION_VERSION_Msk

#define I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos)

(I2SC_VERSION) Version of the Hardware Module

Definition at line 167 of file i2sc.h.

◆ I2SC_VERSION_VERSION_Pos

#define I2SC_VERSION_VERSION_Pos 0

Definition at line 166 of file i2sc.h.

Classes

Macros