component/rstc.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_RSTC_COMPONENT_
36 #define _SAME70_RSTC_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __O uint32_t RSTC_CR;
48  __I uint32_t RSTC_SR;
49  __IO uint32_t RSTC_MR;
50 } Rstc;
51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
52 /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
53 #define RSTC_CR_PROCRST (0x1u << 0)
54 #define RSTC_CR_EXTRST (0x1u << 3)
55 #define RSTC_CR_KEY_Pos 24
56 #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos)
57 #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
58 #define RSTC_CR_KEY_PASSWD (0xA5u << 24)
59 /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
60 #define RSTC_SR_URSTS (0x1u << 0)
61 #define RSTC_SR_RSTTYP_Pos 8
62 #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos)
63 #define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8)
64 #define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8)
65 #define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8)
66 #define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8)
67 #define RSTC_SR_RSTTYP_USER_RST (0x4u << 8)
68 #define RSTC_SR_NRSTL (0x1u << 16)
69 #define RSTC_SR_SRCMP (0x1u << 17)
70 /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
71 #define RSTC_MR_URSTEN (0x1u << 0)
72 #define RSTC_MR_URSTIEN (0x1u << 4)
73 #define RSTC_MR_ERSTL_Pos 8
74 #define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos)
75 #define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
76 #define RSTC_MR_KEY_Pos 24
77 #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos)
78 #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
79 #define RSTC_MR_KEY_PASSWD (0xA5u << 24)
82 
83 
84 #endif /* _SAME70_RSTC_COMPONENT_ */
__IO uint32_t RSTC_MR
(Rstc Offset: 0x08) Mode Register
#define __IO
Definition: core_cm7.h:266
#define __O
Definition: core_cm7.h:265
__I uint32_t RSTC_SR
(Rstc Offset: 0x04) Status Register
Rstc hardware registers.
__O uint32_t RSTC_CR
(Rstc Offset: 0x00) Control Register
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04