component/matrix.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_MATRIX_COMPONENT_
36 #define _SAME70_MATRIX_COMPONENT_
37 
38 /* ============================================================================= */
40 /* ============================================================================= */
43 
44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
45 
46 typedef struct {
47  __IO uint32_t MATRIX_PRAS;
48  __IO uint32_t MATRIX_PRBS;
49 } MatrixPr;
51 #define MATRIXPR_NUMBER 9
52 typedef struct {
53  __IO uint32_t MATRIX_MCFG0;
54  __IO uint32_t MATRIX_MCFG1;
55  __IO uint32_t MATRIX_MCFG2;
56  __IO uint32_t MATRIX_MCFG3;
57  __IO uint32_t MATRIX_MCFG4;
58  __IO uint32_t MATRIX_MCFG5;
59  __IO uint32_t MATRIX_MCFG6;
60  __I uint32_t Reserved1[1];
61  __IO uint32_t MATRIX_MCFG8;
62  __IO uint32_t MATRIX_MCFG9;
63  __IO uint32_t MATRIX_MCFG10;
64  __IO uint32_t MATRIX_MCFG11;
65  __IO uint32_t MATRIX_MCFG12;
66  __I uint32_t Reserved2[3];
67  __IO uint32_t MATRIX_SCFG[9];
68  __I uint32_t Reserved3[7];
70  __I uint32_t Reserved4[14];
71  __IO uint32_t MATRIX_MRCR;
72  __I uint32_t Reserved5[3];
73  __IO uint32_t CCFG_CAN0;
74  __IO uint32_t CCFG_SYSIO;
75  __IO uint32_t CCFG_PCCR;
76  __IO uint32_t CCFG_DYNCFG;
77  __I uint32_t Reserved6[1];
78  __IO uint32_t CCFG_SMCNFCS;
79  __I uint32_t Reserved7[47];
80  __IO uint32_t MATRIX_WPMR;
81  __I uint32_t MATRIX_WPSR;
82  __I uint32_t Reserved8[4];
83  __I uint32_t MATRIX_VERSION;
84 } Matrix;
85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
86 /* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
87 #define MATRIX_MCFG0_ULBT_Pos 0
88 #define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos)
89 #define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
90 #define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0)
91 #define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0)
92 #define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0)
93 #define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0)
94 #define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0)
95 #define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0)
96 #define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0)
97 #define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0)
98 /* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
99 #define MATRIX_MCFG1_ULBT_Pos 0
100 #define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos)
101 #define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
102 #define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0)
103 #define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0)
104 #define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0)
105 #define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0)
106 #define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0)
107 #define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0)
108 #define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0)
109 #define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0)
110 /* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
111 #define MATRIX_MCFG2_ULBT_Pos 0
112 #define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos)
113 #define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
114 #define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0)
115 #define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0)
116 #define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0)
117 #define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0)
118 #define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0)
119 #define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0)
120 #define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0)
121 #define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0)
122 /* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
123 #define MATRIX_MCFG3_ULBT_Pos 0
124 #define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos)
125 #define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
126 #define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0)
127 #define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0)
128 #define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0)
129 #define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0)
130 #define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0)
131 #define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0)
132 #define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0)
133 #define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0)
134 /* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
135 #define MATRIX_MCFG4_ULBT_Pos 0
136 #define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos)
137 #define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
138 #define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0)
139 #define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0)
140 #define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0)
141 #define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0)
142 #define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0)
143 #define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0)
144 #define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0)
145 #define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0)
146 /* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
147 #define MATRIX_MCFG5_ULBT_Pos 0
148 #define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos)
149 #define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
150 #define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0)
151 #define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0)
152 #define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0)
153 #define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0)
154 #define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0)
155 #define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0)
156 #define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0)
157 #define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0)
158 /* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
159 #define MATRIX_MCFG6_ULBT_Pos 0
160 #define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos)
161 #define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
162 #define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0)
163 #define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0)
164 #define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0)
165 #define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0)
166 #define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0)
167 #define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0)
168 #define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0)
169 #define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0)
170 /* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
171 #define MATRIX_MCFG8_ULBT_Pos 0
172 #define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos)
173 #define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
174 #define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0)
175 #define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0)
176 #define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0)
177 #define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0)
178 #define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0)
179 #define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0)
180 #define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0)
181 #define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0)
182 /* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */
183 #define MATRIX_MCFG9_ULBT_Pos 0
184 #define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos)
185 #define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos)))
186 #define MATRIX_MCFG9_ULBT_UNLTD_LENGTH (0x0u << 0)
187 #define MATRIX_MCFG9_ULBT_SINGLE_ACCESS (0x1u << 0)
188 #define MATRIX_MCFG9_ULBT_4BEAT_BURST (0x2u << 0)
189 #define MATRIX_MCFG9_ULBT_8BEAT_BURST (0x3u << 0)
190 #define MATRIX_MCFG9_ULBT_16BEAT_BURST (0x4u << 0)
191 #define MATRIX_MCFG9_ULBT_32BEAT_BURST (0x5u << 0)
192 #define MATRIX_MCFG9_ULBT_64BEAT_BURST (0x6u << 0)
193 #define MATRIX_MCFG9_ULBT_128BEAT_BURST (0x7u << 0)
194 /* -------- MATRIX_MCFG10 : (MATRIX Offset: 0x0028) Master Configuration Register 10 -------- */
195 #define MATRIX_MCFG10_ULBT_Pos 0
196 #define MATRIX_MCFG10_ULBT_Msk (0x7u << MATRIX_MCFG10_ULBT_Pos)
197 #define MATRIX_MCFG10_ULBT(value) ((MATRIX_MCFG10_ULBT_Msk & ((value) << MATRIX_MCFG10_ULBT_Pos)))
198 #define MATRIX_MCFG10_ULBT_UNLTD_LENGTH (0x0u << 0)
199 #define MATRIX_MCFG10_ULBT_SINGLE_ACCESS (0x1u << 0)
200 #define MATRIX_MCFG10_ULBT_4BEAT_BURST (0x2u << 0)
201 #define MATRIX_MCFG10_ULBT_8BEAT_BURST (0x3u << 0)
202 #define MATRIX_MCFG10_ULBT_16BEAT_BURST (0x4u << 0)
203 #define MATRIX_MCFG10_ULBT_32BEAT_BURST (0x5u << 0)
204 #define MATRIX_MCFG10_ULBT_64BEAT_BURST (0x6u << 0)
205 #define MATRIX_MCFG10_ULBT_128BEAT_BURST (0x7u << 0)
206 /* -------- MATRIX_MCFG11 : (MATRIX Offset: 0x002C) Master Configuration Register 11 -------- */
207 #define MATRIX_MCFG11_ULBT_Pos 0
208 #define MATRIX_MCFG11_ULBT_Msk (0x7u << MATRIX_MCFG11_ULBT_Pos)
209 #define MATRIX_MCFG11_ULBT(value) ((MATRIX_MCFG11_ULBT_Msk & ((value) << MATRIX_MCFG11_ULBT_Pos)))
210 #define MATRIX_MCFG11_ULBT_UNLTD_LENGTH (0x0u << 0)
211 #define MATRIX_MCFG11_ULBT_SINGLE_ACCESS (0x1u << 0)
212 #define MATRIX_MCFG11_ULBT_4BEAT_BURST (0x2u << 0)
213 #define MATRIX_MCFG11_ULBT_8BEAT_BURST (0x3u << 0)
214 #define MATRIX_MCFG11_ULBT_16BEAT_BURST (0x4u << 0)
215 #define MATRIX_MCFG11_ULBT_32BEAT_BURST (0x5u << 0)
216 #define MATRIX_MCFG11_ULBT_64BEAT_BURST (0x6u << 0)
217 #define MATRIX_MCFG11_ULBT_128BEAT_BURST (0x7u << 0)
218 /* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
219 #define MATRIX_SCFG_SLOT_CYCLE_Pos 0
220 #define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos)
221 #define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
222 #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
223 #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos)
224 #define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
225 #define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16)
226 #define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16)
227 #define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16)
228 #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
229 #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos)
230 #define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
231 /* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */
232 #define MATRIX_PRAS_M0PR_Pos 0
233 #define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos)
234 #define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
235 #define MATRIX_PRAS_M1PR_Pos 4
236 #define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos)
237 #define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
238 #define MATRIX_PRAS_M2PR_Pos 8
239 #define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos)
240 #define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
241 #define MATRIX_PRAS_M3PR_Pos 12
242 #define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos)
243 #define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
244 #define MATRIX_PRAS_M4PR_Pos 16
245 #define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos)
246 #define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
247 #define MATRIX_PRAS_M5PR_Pos 20
248 #define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos)
249 #define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
250 #define MATRIX_PRAS_M6PR_Pos 24
251 #define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos)
252 #define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
253 /* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */
254 #define MATRIX_PRBS_M8PR_Pos 0
255 #define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos)
256 #define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
257 #define MATRIX_PRBS_M9PR_Pos 4
258 #define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos)
259 #define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
260 #define MATRIX_PRBS_M10PR_Pos 8
261 #define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos)
262 #define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
263 #define MATRIX_PRBS_M11PR_Pos 12
264 #define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos)
265 #define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
266 #define MATRIX_PRBS_M12PR_Pos 16
267 #define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos)
268 #define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)))
269 /* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
270 #define MATRIX_MRCR_RCB0 (0x1u << 0)
271 #define MATRIX_MRCR_RCB1 (0x1u << 1)
272 #define MATRIX_MRCR_RCB2 (0x1u << 2)
273 #define MATRIX_MRCR_RCB3 (0x1u << 3)
274 #define MATRIX_MRCR_RCB4 (0x1u << 4)
275 #define MATRIX_MRCR_RCB5 (0x1u << 5)
276 #define MATRIX_MRCR_RCB6 (0x1u << 6)
277 #define MATRIX_MRCR_RCB8 (0x1u << 8)
278 #define MATRIX_MRCR_RCB9 (0x1u << 9)
279 #define MATRIX_MRCR_RCB10 (0x1u << 10)
280 #define MATRIX_MRCR_RCB11 (0x1u << 11)
281 #define MATRIX_MRCR_RCB12 (0x1u << 12)
282 /* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */
283 #define CCFG_CAN0_CAN0DMABA_Pos 16
284 #define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos)
285 #define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)))
286 /* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */
287 #define CCFG_SYSIO_SYSIO4 (0x1u << 4)
288 #define CCFG_SYSIO_SYSIO5 (0x1u << 5)
289 #define CCFG_SYSIO_SYSIO6 (0x1u << 6)
290 #define CCFG_SYSIO_SYSIO7 (0x1u << 7)
291 #define CCFG_SYSIO_SYSIO12 (0x1u << 12)
292 #define CCFG_SYSIO_CAN1DMABA_Pos 16
293 #define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos)
294 #define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)))
295 /* -------- CCFG_PCCR : (MATRIX Offset: 0x0118) Peripheral Clock Configuration Register -------- */
296 #define CCFG_PCCR_TC0CC (0x1u << 20)
297 #define CCFG_PCCR_I2SC0CC (0x1u << 21)
298 #define CCFG_PCCR_I2SC1CC (0x1u << 22)
299 /* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */
300 #define CCFG_DYNCKG_MATCKG (0x1u << 0)
301 #define CCFG_DYNCKG_BRIDCKG (0x1u << 1)
302 #define CCFG_DYNCKG_EFCCKG (0x1u << 2)
303 /* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
304 #define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0)
305 #define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1)
306 #define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2)
307 #define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3)
308 #define CCFG_SMCNFCS_SDRAMEN (0x1u << 4)
309 /* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
310 #define MATRIX_WPMR_WPEN (0x1u << 0)
311 #define MATRIX_WPMR_WPKEY_Pos 8
312 #define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos)
313 #define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
314 #define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8)
315 /* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
316 #define MATRIX_WPSR_WPVS (0x1u << 0)
317 #define MATRIX_WPSR_WPVSRC_Pos 8
318 #define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos)
319 /* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */
320 #define MATRIX_VERSION_VERSION_Pos 0
321 #define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos)
322 #define MATRIX_VERSION_MFN_Pos 16
323 #define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos)
326 
327 
328 #endif /* _SAME70_MATRIX_COMPONENT_ */
MatrixPr hardware registers.
__IO uint32_t MATRIX_MCFG5
(Matrix Offset: 0x0014) Master Configuration Register 5
__IO uint32_t MATRIX_MRCR
(Matrix Offset: 0x0100) Master Remap Control Register
__IO uint32_t CCFG_CAN0
(Matrix Offset: 0x0110) CAN0 Configuration Register
__IO uint32_t CCFG_PCCR
(Matrix Offset: 0x0118) Peripheral Clock Configuration Register
__IO uint32_t MATRIX_MCFG11
(Matrix Offset: 0x002C) Master Configuration Register 11
__IO uint32_t CCFG_DYNCFG
(Matrix Offset: 0x011C) Dynamic Clock Gating Register
#define __IO
Definition: core_cm7.h:266
__IO uint32_t MATRIX_MCFG6
(Matrix Offset: 0x0018) Master Configuration Register 6
__IO uint32_t MATRIX_MCFG4
(Matrix Offset: 0x0010) Master Configuration Register 4
#define MATRIXPR_NUMBER
Matrix hardware registers.
__IO uint32_t CCFG_SYSIO
(Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register
__IO uint32_t MATRIX_MCFG9
(Matrix Offset: 0x0024) Master Configuration Register 9
__IO uint32_t MATRIX_PRBS
(MatrixPr Offset: 0x4) Priority Register B for Slave 0
__IO uint32_t MATRIX_MCFG3
(Matrix Offset: 0x000C) Master Configuration Register 3
__I uint32_t MATRIX_WPSR
(Matrix Offset: 0x01E8) Write Protection Status Register
__IO uint32_t MATRIX_WPMR
(Matrix Offset: 0x01E4) Write Protection Mode Register
__IO uint32_t MATRIX_PRAS
(MatrixPr Offset: 0x0) Priority Register A for Slave 0
__IO uint32_t MATRIX_MCFG2
(Matrix Offset: 0x0008) Master Configuration Register 2
__IO uint32_t MATRIX_MCFG1
(Matrix Offset: 0x0004) Master Configuration Register 1
__IO uint32_t MATRIX_MCFG8
(Matrix Offset: 0x0020) Master Configuration Register 8
__I uint32_t MATRIX_VERSION
(Matrix Offset: 0x01FC) Version Register
__IO uint32_t MATRIX_MCFG10
(Matrix Offset: 0x0028) Master Configuration Register 10
__IO uint32_t MATRIX_MCFG12
(Matrix Offset: 0x0030) Master Configuration Register 12
__IO uint32_t CCFG_SMCNFCS
(Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register
__IO uint32_t MATRIX_MCFG0
(Matrix Offset: 0x0000) Master Configuration Register 0
#define __I
Definition: core_cm7.h:263


inertial_sense_ros
Author(s):
autogenerated on Sat Sep 19 2020 03:19:04