stm32f30x_hrtim.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F30x_HRTIM_H
31 #define __STM32F30x_HRTIM_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f30x.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
53 typedef struct
54 {
55  uint32_t Period;
58  uint32_t RepetitionCounter;
60  uint32_t PrescalerRatio;
62  uint32_t Mode;
64 } HRTIM_BaseInitTypeDef;
68 typedef struct {
69  uint32_t HalfModeEnable;
71  uint32_t StartOnSync;
73  uint32_t ResetOnSync;
75  uint32_t DACSynchro;
77  uint32_t PreloadEnable;
79  uint32_t UpdateGating;
82  uint32_t BurstMode;
84  uint32_t RepetitionUpdate;
86 } HRTIM_TimerInitTypeDef;
87 
91 typedef struct {
92  uint32_t Mode;
94  uint32_t Pulse;
96  uint32_t Polarity;
98  uint32_t IdleState;
100 } HRTIM_BasicOCChannelCfgTypeDef;
101 
105 typedef struct {
106  uint32_t Pulse;
108  uint32_t Polarity;
110  uint32_t IdleState;
112 } HRTIM_BasicPWMChannelCfgTypeDef;
113 
117 typedef struct {
118  uint32_t CaptureUnit;
120  uint32_t Event;
122  uint32_t EventPolarity;
124  uint32_t EventSensitivity;
126  uint32_t EventFilter;
128 } HRTIM_BasicCaptureChannelCfgTypeDef;
129 
133 typedef struct {
134  uint32_t Pulse;
136  uint32_t OutputPolarity;
138  uint32_t OutputIdleState;
140  uint32_t Event;
142  uint32_t EventPolarity;
144  uint32_t EventSensitivity;
146  uint32_t EventFilter;
148 } HRTIM_BasicOnePulseChannelCfgTypeDef;
149 
153 typedef struct {
154  uint32_t PushPull;
156  uint32_t FaultEnable;
158  uint32_t FaultLock;
160  uint32_t DeadTimeInsertion;
162  uint32_t DelayedProtectionMode;
164  uint32_t UpdateTrigger;
166  uint32_t ResetTrigger;
168  uint32_t ResetUpdate;
170 } HRTIM_TimerCfgTypeDef;
171 
175 typedef struct {
176  uint32_t CompareValue;
179  uint32_t AutoDelayedMode;
181  uint32_t AutoDelayedTimeout;
183 } HRTIM_CompareCfgTypeDef;
184 
188 typedef struct {
189  uint32_t Trigger;
191 } HRTIM_CaptureCfgTypeDef;
192 
196 typedef struct {
197  uint32_t Polarity;
199  uint32_t SetSource;
201  uint32_t ResetSource;
203  uint32_t IdleMode;
205  uint32_t IdleState;
207  uint32_t FaultState;
209  uint32_t ChopperModeEnable;
211  uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
212  during a burst mode operation
213  This parameters can be any value of @ref HRTIM_OutputBurstModeEntryDelayed */
214 } HRTIM_OutputCfgTypeDef;
215 
219 typedef struct {
220  uint32_t Filter;
222  uint32_t Latch;
224 } HRTIM_TimerEventFilteringCfgTypeDef;
225 
229 typedef struct {
230  uint32_t Prescaler;
232  uint32_t RisingValue;
234  uint32_t RisingSign;
236  uint32_t RisingLock;
238  uint32_t RisingSignLock;
240  uint32_t FallingValue;
242  uint32_t FallingSign;
244  uint32_t FallingLock;
246  uint32_t FallingSignLock;
248 } HRTIM_DeadTimeCfgTypeDef;
249 
253 typedef struct {
254  uint32_t CarrierFreq;
256  uint32_t DutyCycle;
258  uint32_t StartPulse;
260 } HRTIM_ChopperModeCfgTypeDef;
261 
265 typedef struct {
266  uint32_t SyncInputSource;
268  uint32_t SyncOutputSource;
270  uint32_t SyncOutputPolarity;
272 } HRTIM_SynchroCfgTypeDef;
273 
277 typedef struct {
278  uint32_t Source;
280  uint32_t Polarity;
282  uint32_t Sensitivity;
284  uint32_t Filter;
286  uint32_t FastMode;
288 } HRTIM_EventCfgTypeDef;
289 
293 typedef struct {
294  uint32_t Source;
296  uint32_t Polarity;
298  uint32_t Filter;
300  uint32_t Lock;
302 } HRTIM_FaultCfgTypeDef;
303 
307 typedef struct {
308  uint32_t Mode;
310  uint32_t ClockSource;
312  uint32_t Prescaler;
314  uint32_t PreloadEnable;
316  uint32_t Trigger;
318  uint32_t IdleDuration;
320  uint32_t Period;
322 } HRTIM_BurstModeCfgTypeDef;
323 
327 typedef struct {
328  uint32_t UpdateSource;
330  uint32_t Trigger;
332 } HRTIM_ADCTriggerCfgTypeDef;
333 
334 
335 /* Exported constants --------------------------------------------------------*/
344 #define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0
345 #define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1
346 #define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2
347 #define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3
348 #define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4
349 #define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5
350 #define HRTIM_COMMONINDEX (uint32_t)0x6
352 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
353  (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
354  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
355  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
356  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
357  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
358  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
359 
360 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
361  (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
362  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
363  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
364  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
365  ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
366 
374 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN)
375 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)
376 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)
377 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)
378 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)
379 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)
381 #define IS_HRTIM_TIMERID(TIMERID)\
382  (((TIMERID) == HRTIM_TIMERID_MASTER) || \
383  ((TIMERID) == HRTIM_TIMERID_TIMER_A) || \
384  ((TIMERID) == HRTIM_TIMERID_TIMER_B) || \
385  ((TIMERID) == HRTIM_TIMERID_TIMER_C) || \
386  ((TIMERID) == HRTIM_TIMERID_TIMER_D) || \
387  ((TIMERID) == HRTIM_TIMERID_TIMER_E))
388 
396 #define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001
397 #define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002
398 #define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004
399 #define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008
401 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
402  (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
403  ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
404  ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
405  ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
406 
414 #define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001
415 #define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002
417 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
418  (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
419  ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
420 
428 #define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001
429 #define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002
430 #define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004
431 #define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008
432 #define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010
433 #define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020
434 #define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040
435 #define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080
436 #define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100
437 #define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200
439 #define IS_HRTIM_OUTPUT(OUTPUT)\
440  (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
441  ((OUTPUT) == HRTIM_OUTPUT_TA2) || \
442  ((OUTPUT) == HRTIM_OUTPUT_TB1) || \
443  ((OUTPUT) == HRTIM_OUTPUT_TB2) || \
444  ((OUTPUT) == HRTIM_OUTPUT_TC1) || \
445  ((OUTPUT) == HRTIM_OUTPUT_TC2) || \
446  ((OUTPUT) == HRTIM_OUTPUT_TD1) || \
447  ((OUTPUT) == HRTIM_OUTPUT_TD2) || \
448  ((OUTPUT) == HRTIM_OUTPUT_TE1) || \
449  ((OUTPUT) == HRTIM_OUTPUT_TE2))
450 
451 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
452  ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
453  (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
454  ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
455  || \
456  (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
457  (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
458  ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
459  || \
460  (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
461  (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
462  ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
463  || \
464  (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
465  (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
466  ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
467  || \
468  (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
469  (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
470  ((OUTPUT) == HRTIM_OUTPUT_TE2))))
471 
479 #define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001
480 #define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002
481 #define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004
482 #define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008
484 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
485  (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
486  ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
487  ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
488  ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
489 
497 #define HRTIM_EVENT_NONE ((uint32_t)0x00000000)
498 #define HRTIM_EVENT_1 ((uint32_t)0x00000001)
499 #define HRTIM_EVENT_2 ((uint32_t)0x00000002)
500 #define HRTIM_EVENT_3 ((uint32_t)0x00000004)
501 #define HRTIM_EVENT_4 ((uint32_t)0x00000008)
502 #define HRTIM_EVENT_5 ((uint32_t)0x00000010)
503 #define HRTIM_EVENT_6 ((uint32_t)0x00000020)
504 #define HRTIM_EVENT_7 ((uint32_t)0x00000040)
505 #define HRTIM_EVENT_8 ((uint32_t)0x00000080)
506 #define HRTIM_EVENT_9 ((uint32_t)0x00000100)
507 #define HRTIM_EVENT_10 ((uint32_t)0x00000200)
509 #define IS_HRTIM_EVENT(EVENT)\
510  (((EVENT) == HRTIM_EVENT_1) || \
511  ((EVENT) == HRTIM_EVENT_2) || \
512  ((EVENT) == HRTIM_EVENT_3) || \
513  ((EVENT) == HRTIM_EVENT_4) || \
514  ((EVENT) == HRTIM_EVENT_5) || \
515  ((EVENT) == HRTIM_EVENT_6) || \
516  ((EVENT) == HRTIM_EVENT_7) || \
517  ((EVENT) == HRTIM_EVENT_8) || \
518  ((EVENT) == HRTIM_EVENT_9) || \
519  ((EVENT) == HRTIM_EVENT_10))
520 
528 #define HRTIM_FAULT_1 ((uint32_t)0x01)
529 #define HRTIM_FAULT_2 ((uint32_t)0x02)
530 #define HRTIM_FAULT_3 ((uint32_t)0x04)
531 #define HRTIM_FAULT_4 ((uint32_t)0x08)
532 #define HRTIM_FAULT_5 ((uint32_t)0x10)
534 #define IS_HRTIM_FAULT(FAULT)\
535  (((FAULT) == HRTIM_FAULT_1) || \
536  ((FAULT) == HRTIM_FAULT_2) || \
537  ((FAULT) == HRTIM_FAULT_3) || \
538  ((FAULT) == HRTIM_FAULT_4) || \
539  ((FAULT) == HRTIM_FAULT_5))
540 
549 #define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000)
550 #define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001)
551 #define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002)
552 #define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003)
553 #define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004)
554 #define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005)
555 #define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006)
556 #define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007)
558 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
559  (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
560  ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
561  ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
562  ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
563  ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
564  ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
565  ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
566  ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
567 
575 #define HRTIM_MODE_CONTINOUS ((uint32_t)0x00000008)
576 #define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000)
577 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010)
579 #define IS_HRTIM_MODE(MODE)\
580  (((MODE) == HRTIM_MODE_CONTINOUS) || \
581  ((MODE) == HRTIM_MODE_SINGLESHOT) || \
582  ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
583 
584 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
585  (((MODE) == HRTIM_MODE_SINGLESHOT) || \
586  ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
587 
596 #define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000)
597 #define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020)
599 #define IS_HRTIM_HALFMODE(HALFMODE)\
600  (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
601  ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
602 
610 #define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000)
611 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM)
613 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
614  (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
615  ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
616 
624 #define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000)
625 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM)
627 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
628  (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
629  ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
630 
638 #define HRTIM_DACSYNC_NONE (uint32_t)0x00000000
639 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0)
640 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1)
641 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0)
643 #define IS_HRTIM_DACSYNC(DACSYNC)\
644  (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
645  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
646  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
647  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
648 
657 #define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000)
658 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN)
660 #define IS_HRTIM_PRELOAD(PRELOAD)\
661  (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
662  ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
663 
672 #define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000
673 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0)
674 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)
675 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)
676 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2)
677 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)
678 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)
679 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)
680 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3)
682 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
683  (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
684  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
685  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
686 
687 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
688  (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
689  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
690  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
691  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
692  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
693  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
694  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
695  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
696  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
697 
706 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000
707 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM)
709 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
710  (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
711  ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
712 
722 #define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000
723 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU)
725 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
726  (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
727  ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
728 
738 #define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000)
739 #define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL)
741 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
742  (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
743  ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
744 
752 #define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000
753 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN)
754 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN)
755 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN)
756 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN)
757 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN)
759 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
760 
770 #define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000)
771 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTCLK)
773 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
774  (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
775  ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
776 
785 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000)
786 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN
788 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION)\
789  (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
790  ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
791 
801 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000)
802 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN)
803 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
804 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
805 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
806 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)
807 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
808 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)
809 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)
811 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION)\
812  (((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) || \
813  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) || \
814  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) || \
815  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) || \
816  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) || \
817  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) || \
818  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) || \
819  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79) || \
820  ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79))
821 
830 #define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000
831 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU)
832 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU)
833 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU)
834 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU)
835 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU)
836 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU)
838 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
839 
848 #define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000
849 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE)
850 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2)
851 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4)
852 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER)
853 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)
854 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)
855 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)
856 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)
857 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1)
858 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2)
859 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3)
860 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4)
861 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5)
862 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6)
863 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7)
864 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8)
865 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9)
866 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10)
867 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)
868 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)
869 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)
870 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)
871 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)
872 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)
873 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)
874 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)
875 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)
876 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)
877 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)
878 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)
880 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
881 
892 #define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000
893 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)
895 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
896  (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
897  ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
898 
908 #define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000)
909 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0)
910 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)
911 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0)
913 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
914  (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
915  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
916  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
917  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
918 
919 /* Auto delayed mode is only available for compare units 2 and 4 */
920 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
921  ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) && \
922  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
923  || \
924  (((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
925  (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
926  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
927  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
928  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
929  || \
930  (((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) && \
931  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \
932  || \
933  (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
934  (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
935  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
936  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
937  ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
938 
947 #define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001)
948 #define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002)
949 #define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003)
951 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
952  (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
953  ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
954  ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
955 
963 #define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
964 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1)
966 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
967  (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
968  ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
969 
978 #define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000
979 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC)
980 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER)
981 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1)
982 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2)
983 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3)
984 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4)
985 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER)
986 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)
987 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)
988 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)
989 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)
990 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
991 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
992 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
993 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
994 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
995 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
996 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
997 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
998 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
999 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1)
1000 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2)
1001 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3)
1002 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4)
1003 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5)
1004 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6)
1005 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7)
1006 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8)
1007 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9)
1008 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10)
1009 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE)
1011 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
1012  (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
1013  ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
1014  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
1015  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
1016  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
1017  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
1018  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
1019  ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
1020  ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
1021  ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
1022  ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
1023  ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
1024  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
1025  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
1026  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
1027  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
1028  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
1029  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
1030  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
1031  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
1032  ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
1033  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
1034  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
1035  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
1036  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
1037  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
1038  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
1039  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
1040  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
1041  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
1042  ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
1043  ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
1044 
1053 #define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000
1054 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC)
1055 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER)
1056 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1)
1057 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2)
1058 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3)
1059 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4)
1060 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER)
1061 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)
1062 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)
1063 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)
1064 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)
1065 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
1066 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
1067 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
1068 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
1069 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
1070 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
1071 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
1072 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
1073 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
1074 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1)
1075 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2)
1076 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3)
1077 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4)
1078 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5)
1079 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6)
1080 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7)
1081 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8)
1082 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9)
1083 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10)
1084 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE)
1086 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
1087  (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
1088  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
1089  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
1090  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
1091  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
1092  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
1093  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
1094  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
1095  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
1096  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
1097  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
1098  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
1099  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
1100  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
1101  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
1102  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
1103  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
1104  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
1105  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
1106  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
1107  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
1108  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
1109  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
1110  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
1111  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
1112  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
1113  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
1114  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
1115  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
1116  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
1117  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
1118  ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
1119 
1128 #define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000
1129 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1)
1131 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
1132  (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
1133  ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
1134 
1142 #define HRTIM_OUTPUTIDLESTATE_INACTIVE (uint32_t)0x00000000
1143 #define HRTIM_OUTPUTIDLESTATE_ACTIVE (HRTIM_OUTR_IDLES1)
1145 #define IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE)\
1146  (((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_INACTIVE) || \
1147  ((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_ACTIVE))
1148 
1156 #define HRTIM_OUTPUTFAULTSTATE_NONE (uint32_t)0x00000000
1157 #define HRTIM_OUTPUTFAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0)
1158 #define HRTIM_OUTPUTFAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1)
1159 #define HRTIM_OUTPUTFAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)
1161 #define IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE)\
1162  (((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_NONE) || \
1163  ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_ACTIVE) || \
1164  ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_INACTIVE) || \
1165  ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_HIGHZ))
1166 
1175 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000
1176 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1)
1178 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
1179  (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
1180  ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
1181 
1190 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000
1191 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1)
1193 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
1194  (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
1195  ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
1196 
1205 #define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000
1206 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT)
1207 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT)
1208 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT)
1209 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT)
1210 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT)
1211 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT)
1212 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT)
1213 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT)
1214 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT)
1215 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT)
1216 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT)
1217 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET)
1218 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST)
1219 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TA1CMP1)
1220 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TA1CMP2)
1221 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET)
1222 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST)
1223 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TB1CMP1)
1224 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TB1CMP2)
1225 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET)
1226 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST)
1227 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TC1CMP1)
1228 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TC1CMP2)
1229 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET)
1230 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST)
1231 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TD1CMP1)
1232 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TD1CMP2)
1233 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET)
1234 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST)
1235 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TE1CMP1)
1236 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TE1CMP2)
1238 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
1239  (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
1240  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
1241  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
1242  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
1243  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
1244  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
1245  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
1246  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
1247  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
1248  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
1249  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
1250  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
1251  || \
1252  (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
1253  (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
1254  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
1255  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
1256  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2))) \
1257  || \
1258  (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
1259  (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
1260  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
1261  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
1262  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2))) \
1263  || \
1264  (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
1265  (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
1266  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
1267  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
1268  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2))) \
1269  || \
1270  (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
1271  (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
1272  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
1273  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
1274  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \
1275  || \
1276  (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
1277  (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
1278  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
1279  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
1280  ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
1281 
1290 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
1291 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
1292 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
1293 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
1294 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
1295 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
1296 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
1297 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
1298 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
1299 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
1300 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
1301 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
1302 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
1303 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
1304 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
1305 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
1307 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
1308  (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
1309  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
1310  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
1311  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
1312  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
1313  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
1314  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
1315  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
1316  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
1317  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
1318  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
1319  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
1320  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
1321  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
1322  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
1323  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
1324 
1334 #define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000)
1335 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH
1337 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
1338  (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
1339  ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
1340 
1349 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000)
1350 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR)
1352 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
1353  (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
1354  ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
1355 
1364 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000)
1365 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)
1367 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
1368  (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
1369  ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
1370 
1379 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000)
1380 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)
1382 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
1383  (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
1384  ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
1385 
1394 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000)
1395 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF)
1397 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
1398  (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
1399  ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
1400 
1409 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000)
1410 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)
1412 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
1413  (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
1414  ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
1415 
1424 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000)
1425 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)
1427 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
1428  (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
1429  ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
1430 
1438 #define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000
1439 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1
1440 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)
1442 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
1443  (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
1444  ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
1445  ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
1446 
1455 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000
1456 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0)
1457 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1)
1458 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)
1460 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
1461  (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
1462  ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
1463  ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
1464  ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
1465 
1473 #define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000
1474 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_0)
1475 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0)
1477 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
1478  (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
1479  ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
1480  ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
1481 
1489 #define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000)
1490 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
1491 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
1492 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
1494 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
1495  (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
1496  ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
1497  ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
1498  ((EVENTSRC) == HRTIM_EVENTSRC_4))
1499 
1507 #define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000)
1508 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL)
1510 #define IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY)\
1511  (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
1512  ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))
1513 
1522 #define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000)
1523 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0)
1524 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1)
1525 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)
1527 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
1528  (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
1529  ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
1530  ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
1531  ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
1532 
1541 #define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000)
1542 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST)
1544 #define IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE)\
1545  (((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
1546  ((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))
1547 
1548 #define IS_HRTIM_FASTMODE_AVAILABLE(EVENT)\
1549  (((EVENT) == HRTIM_EVENT_1) || \
1550  ((EVENT) == HRTIM_EVENT_2) || \
1551  ((EVENT) == HRTIM_EVENT_3) || \
1552  ((EVENT) == HRTIM_EVENT_4) || \
1553  ((EVENT) == HRTIM_EVENT_5))
1554 
1563 #define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000)
1564 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0)
1565 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1)
1566 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
1567 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2)
1568 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)
1569 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)
1570 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
1571 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3)
1572 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)
1573 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)
1574 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
1575 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)
1576 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)
1577 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)
1578 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)
1580 #define IS_HRTIM_EVENTFILTER(EVENTFILTER)\
1581  (((EVENTFILTER) == HRTIM_EVENTFILTER_NONE) || \
1582  ((EVENTFILTER) == HRTIM_EVENTFILTER_1) || \
1583  ((EVENTFILTER) == HRTIM_EVENTFILTER_2) || \
1584  ((EVENTFILTER) == HRTIM_EVENTFILTER_3) || \
1585  ((EVENTFILTER) == HRTIM_EVENTFILTER_4) || \
1586  ((EVENTFILTER) == HRTIM_EVENTFILTER_5) || \
1587  ((EVENTFILTER) == HRTIM_EVENTFILTER_6) || \
1588  ((EVENTFILTER) == HRTIM_EVENTFILTER_7) || \
1589  ((EVENTFILTER) == HRTIM_EVENTFILTER_8) || \
1590  ((EVENTFILTER) == HRTIM_EVENTFILTER_9) || \
1591  ((EVENTFILTER) == HRTIM_EVENTFILTER_10) || \
1592  ((EVENTFILTER) == HRTIM_EVENTFILTER_11) || \
1593  ((EVENTFILTER) == HRTIM_EVENTFILTER_12) || \
1594  ((EVENTFILTER) == HRTIM_EVENTFILTER_13) || \
1595  ((EVENTFILTER) == HRTIM_EVENTFILTER_14) || \
1596  ((EVENTFILTER) == HRTIM_EVENTFILTER_15))
1597 
1607 #define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000)
1608 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0)
1609 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1)
1610 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)
1612 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
1613  (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
1614  ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
1615  ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
1616  ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
1617 
1626 #define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000)
1627 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC)
1630 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
1631  (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
1632  ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
1633 
1641 #define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000)
1642 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P)
1644 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
1645  (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
1646  ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
1647 
1656 #define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000)
1657 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0)
1658 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1)
1659 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
1660 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2)
1661 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)
1662 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)
1663 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
1664 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3)
1665 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)
1666 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)
1667 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
1668 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)
1669 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)
1670 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)
1671 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)
1673 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
1674  (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
1675  ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
1676  ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
1677  ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
1678  ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
1679  ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
1680  ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
1681  ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
1682  ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
1683  ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
1684  ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
1685  ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
1686  ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
1687  ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
1688  ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
1689  ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
1690 
1699 #define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000)
1700 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK)
1702 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
1703  (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
1704  ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
1705 
1715 #define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000)
1716 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0)
1717 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1)
1718 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)
1720 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
1721  (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
1722  ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
1723  ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
1724  ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
1725 
1734 #define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000)
1735 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM)
1737 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
1738  (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
1739  ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
1740 
1748 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000)
1749 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0)
1750 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1)
1751 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)
1752 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2)
1753 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)
1754 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)
1755 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)
1756 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3 (HRTIM_BMCR_BMCLK_3)
1757 #define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4 (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_0)
1758 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)
1760 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
1761  (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
1762  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
1763  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
1764  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
1765  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
1766  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
1767  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1) || \
1768  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2) || \
1769  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3) || \
1770  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4) || \
1771  ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
1772 
1781 #define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000)
1782 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPSC_0)
1783 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPSC_1)
1784 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0)
1785 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPSC_2)
1786 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0)
1787 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1)
1788 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0)
1789 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPSC_3)
1790 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_0)
1791 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1)
1792 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0)
1793 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2)
1794 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0)
1795 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1)
1796 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0)
1798 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
1799  (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
1800  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
1801  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
1802  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
1803  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
1804  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
1805  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
1806  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
1807  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
1808  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
1809  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
1810  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
1811  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
1812  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
1813  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
1814  ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
1815 
1825 #define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000)
1826 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN)
1828 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
1829  (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
1830  ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
1831 
1840 #define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000
1841 #define HRTIM_BURSTMODETRIGGER_SOFTWARE (HRTIM_BMTRGR_SW)
1842 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST)
1843 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP)
1844 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1)
1845 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2)
1846 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3)
1847 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4)
1848 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST)
1849 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP)
1850 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1)
1851 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2)
1852 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST)
1853 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP)
1854 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1)
1855 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2)
1856 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST)
1857 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP)
1858 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1)
1859 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2)
1860 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST)
1861 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP)
1862 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1)
1863 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2)
1864 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST)
1865 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP)
1866 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1)
1867 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2)
1868 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7)
1869 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8)
1870 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7)
1871 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8)
1872 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV)
1874 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
1875  (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
1876  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
1877  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
1878  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
1879  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
1880  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
1881  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
1882  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
1883  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
1884  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
1885  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
1886  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
1887  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
1888  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
1889  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
1890  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
1891  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
1892  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
1893  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
1894  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
1895  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
1896  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
1897  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
1898  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
1899  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
1900  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
1901  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
1902  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
1903  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
1904  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
1905  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
1906  ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
1907 
1916 #define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000
1917 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)
1918 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)
1919 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0)
1920 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)
1921 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0)
1923 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
1924  (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
1925  ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
1926  ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
1927  ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
1928  ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
1929  ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
1930 
1940 #define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000
1941 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1)
1942 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2)
1943 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3)
1944 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4)
1945 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER)
1946 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1)
1947 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2)
1948 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3)
1949 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4)
1950 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5)
1951 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2)
1952 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3)
1953 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4)
1954 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER)
1955 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST)
1956 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2)
1957 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3)
1958 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4)
1959 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER)
1960 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST)
1961 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2)
1962 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3)
1963 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4)
1964 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER)
1965 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2)
1966 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3)
1967 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4)
1968 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER)
1969 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2)
1970 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3)
1971 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4)
1972 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER)
1974 #define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000
1975 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1)
1976 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2)
1977 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3)
1978 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4)
1979 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER)
1980 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6)
1981 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7)
1982 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8)
1983 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9)
1984 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10)
1985 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2)
1986 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3)
1987 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4)
1988 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER)
1989 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2)
1990 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3)
1991 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4)
1992 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER)
1993 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2)
1994 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3)
1995 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4)
1996 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER)
1997 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST)
1998 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2)
1999 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3)
2000 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4)
2001 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER)
2002 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST)
2003 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2)
2004 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3)
2005 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4)
2006 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST)
2017 #define HRTIM_SINGLE_CALIBRATION (uint32_t)0xFFFFFFFF
2018 #define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000
2019 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
2020 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
2021 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
2023 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
2024  (((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
2025  ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
2026  ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
2027  ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
2028 
2037 #define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000
2038 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR)
2039 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR)
2040 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER)
2041 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT)
2042 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER)
2043 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP)
2044 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1)
2045 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2)
2046 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3)
2047 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4)
2048 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR)
2049 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)
2050 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)
2051 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)
2052 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)
2053 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)
2054 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)
2055 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR)
2056 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR)
2057 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR)
2058 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR)
2060 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
2061  ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
2062  || \
2063  (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2064  || \
2065  (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2066  || \
2067  (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2068  || \
2069  (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2070  || \
2071  (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
2072 
2080 #define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000
2081 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME)
2083 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
2084  (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
2085  ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
2086 
2094 #define HRTIM_FAULT_DISABLED (uint32_t)0x00000000
2095 #define HRTIM_FAULT_ENABLED (HRTIM_FLTINR1_FLT1E)
2097 #define IS_HRTIM_FAULTCTL(FAULTCTL)\
2098  (((FAULTCTL) == HRTIM_FAULT_DISABLED) || \
2099  ((FAULTCTL) == HRTIM_FAULT_ENABLED))
2100 
2108 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU)
2109 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU)
2110 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU)
2111 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU)
2112 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU)
2113 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU)
2115 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
2116 
2124 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST)
2125 #define HRTIM_TIMERRESET_A (HRTIM_CR2_TARST)
2126 #define HRTIM_TIMERRESET_B (HRTIM_CR2_TBRST)
2127 #define HRTIM_TIMERRESET_C (HRTIM_CR2_TCRST)
2128 #define HRTIM_TIMERRESET_D (HRTIM_CR2_TDRST)
2129 #define HRTIM_TIMERRESET_E (HRTIM_CR2_TERST)
2131 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
2132 
2140 #define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001
2141 #define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002
2143 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
2144  (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
2145  ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
2146 
2154 #define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001
2156 #define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002
2158 #define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003
2168 #define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000
2169 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)
2179 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000
2180 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT)
2191 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000
2192 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT)
2200 #define HRTIM_IT_FLT1 HRTIM_ISR_FLT1
2201 #define HRTIM_IT_FLT2 HRTIM_ISR_FLT2
2202 #define HRTIM_IT_FLT3 HRTIM_ISR_FLT3
2203 #define HRTIM_IT_FLT4 HRTIM_ISR_FLT4
2204 #define HRTIM_IT_FLT5 HRTIM_ISR_FLT5
2205 #define HRTIM_IT_SYSFLT HRTIM_ISR_SYSFLT
2206 #define HRTIM_IT_DLLRDY HRTIM_ISR_DLLRDY
2207 #define HRTIM_IT_BMPER HRTIM_ISR_BMPER
2209 #define IS_HRTIM_IT(IT)\
2210  (((IT) == HRTIM_ISR_FLT1) || \
2211  ((IT) == HRTIM_ISR_FLT2) || \
2212  ((IT) == HRTIM_ISR_FLT3) || \
2213  ((IT) == HRTIM_ISR_FLT4) || \
2214  ((IT) == HRTIM_ISR_FLT5) || \
2215  ((IT) == HRTIM_ISR_SYSFLT) || \
2216  ((IT) == HRTIM_ISR_DLLRDY) || \
2217  ((IT) == HRTIM_ISR_BMPER))
2218 
2225 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1
2226 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2
2227 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3
2228 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4
2229 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5
2230 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT
2231 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY
2232 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER
2234 #define IS_HRTIM_FLAG(FLAG)\
2235  (((FLAG) == HRTIM_ISR_FLT1) || \
2236  ((FLAG) == HRTIM_ISR_FLT2) || \
2237  ((FLAG) == HRTIM_ISR_FLT3) || \
2238  ((FLAG) == HRTIM_ISR_FLT4) || \
2239  ((FLAG) == HRTIM_ISR_FLT5) || \
2240  ((FLAG) == HRTIM_ISR_SYSFLT) || \
2241  ((FLAG) == HRTIM_ISR_DLLRDY) || \
2242  ((FLAG) == HRTIM_ISR_BMPER))
2243 
2250 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE
2251 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE
2252 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE
2253 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE
2254 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE
2255 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE
2256 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE
2258 #define IS_HRTIM_MASTER_IT(IT)\
2259  (((IT) == HRTIM_MDIER_MCMP1IE) || \
2260  ((IT) == HRTIM_MDIER_MCMP2IE) || \
2261  ((IT) == HRTIM_MDIER_MCMP3IE) || \
2262  ((IT) == HRTIM_MDIER_MCMP4IE) || \
2263  ((IT) == HRTIM_MDIER_MREPIE) || \
2264  ((IT) == HRTIM_MDIER_SYNCIE) || \
2265  ((IT) == HRTIM_MDIER_MUPDIE))
2266 
2270 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1
2271 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2
2272 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3
2273 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4
2274 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP
2275 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC
2276 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD
2278 #define IS_HRTIM_MASTER_FLAG(FLAG)\
2279  (((FLAG) == HRTIM_MISR_MCMP1) || \
2280  ((FLAG) == HRTIM_MISR_MCMP2) || \
2281  ((FLAG) == HRTIM_MISR_MCMP3) || \
2282  ((FLAG) == HRTIM_MISR_MCMP4) || \
2283  ((FLAG) == HRTIM_MISR_MREP) || \
2284  ((FLAG) == HRTIM_MISR_SYNC) || \
2285  ((FLAG) == HRTIM_MISR_MUPD))
2286 
2293 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE
2294 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE
2295 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE
2296 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE
2297 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE
2298 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE
2299 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE
2300 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE
2301 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE
2302 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE
2303 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE
2304 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE
2305 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE
2306 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE
2308 #define IS_HRTIM_TIM_IT(IT)\
2309  (((IT) == HRTIM_TIMDIER_CMP1IE) || \
2310  ((IT) == HRTIM_TIMDIER_CMP2IE) || \
2311  ((IT) == HRTIM_TIMDIER_CMP3IE) || \
2312  ((IT) == HRTIM_TIMDIER_CMP4IE) || \
2313  ((IT) == HRTIM_TIMDIER_REPIE) || \
2314  ((IT) == HRTIM_TIMDIER_UPDIE) || \
2315  ((IT) == HRTIM_TIMDIER_CPT1IE) || \
2316  ((IT) == HRTIM_TIMDIER_CPT2IE) || \
2317  ((IT) == HRTIM_TIMDIER_SET1IE) || \
2318  ((IT) == HRTIM_TIMDIER_RST1IE) || \
2319  ((IT) == HRTIM_TIMDIER_SET2IE) || \
2320  ((IT) == HRTIM_TIMDIER_RST2IE) || \
2321  ((IT) == HRTIM_TIMDIER_RSTIE) || \
2322  ((IT) == HRTIM_TIMDIER_DLYPRTIE))
2323 
2331 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1
2332 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2
2333 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3
2334 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4
2335 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP
2336 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD
2337 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1
2338 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2
2339 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1
2340 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1
2341 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2
2342 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2
2343 #define HRTIM_TIM_FLAG_RST HRTIM_TIMDIER_RSTIE
2344 #define HRTIM_TIM_FLAG_DLYPRT1 HRTIM_TIMISR_DLYPRT
2346 #define IS_HRTIM_TIM_FLAG(FLAG)\
2347  (((FLAG) == HRTIM_TIM_FLAG_CMP1) || \
2348  ((FLAG) == HRTIM_TIM_FLAG_CMP2) || \
2349  ((FLAG) == HRTIM_TIM_FLAG_CMP3) || \
2350  ((FLAG) == HRTIM_TIM_FLAG_CMP4) || \
2351  ((FLAG) == HRTIM_TIM_FLAG_REP) || \
2352  ((FLAG) == HRTIM_TIM_FLAG_UPD) || \
2353  ((FLAG) == HRTIM_TIM_FLAG_CPT1) || \
2354  ((FLAG) == HRTIM_TIM_FLAG_CPT2) || \
2355  ((FLAG) == HRTIM_TIM_FLAG_SET1) || \
2356  ((FLAG) == HRTIM_TIM_FLAG_RST1) || \
2357  ((FLAG) == HRTIM_TIM_FLAG_SET2) || \
2358  ((FLAG) == HRTIM_TIM_FLAG_RST2) || \
2359  ((FLAG) == HRTIM_TIM_FLAG_RST) || \
2360  ((FLAG) == HRTIM_TIM_FLAG_DLYPRT1))
2361 
2369 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE
2370 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE
2371 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE
2372 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE
2373 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE
2374 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE
2375 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE
2377 #define IS_HRTIM_MASTER_DMA(DMA)\
2378  (((DMA) == HRTIM_MDIER_MCMP1DE) || \
2379  ((DMA) == HRTIM_MDIER_MCMP2DE) || \
2380  ((DMA) == HRTIM_MDIER_MCMP3DE) || \
2381  ((DMA) == HRTIM_MDIER_MCMP4DE) || \
2382  ((DMA) == HRTIM_MDIER_MREPDE) || \
2383  ((DMA) == HRTIM_MDIER_SYNCDE) || \
2384  ((DMA) == HRTIM_MDIER_MUPDDE))
2385 
2392 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE
2393 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE
2394 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE
2395 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE
2396 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE
2397 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE
2398 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE
2399 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE
2400 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE
2401 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE
2402 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE
2403 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE
2404 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE
2405 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE
2407 #define IS_HRTIM_TIM_DMA(DMA)\
2408  (((DMA) == HRTIM_TIMDIER_CMP1DE) || \
2409  ((DMA) == HRTIM_TIMDIER_CMP2DE) || \
2410  ((DMA) == HRTIM_TIMDIER_CMP3DE) || \
2411  ((DMA) == HRTIM_TIMDIER_CMP4DE) || \
2412  ((DMA) == HRTIM_TIMDIER_REPDE) || \
2413  ((DMA) == HRTIM_TIMDIER_UPDDE) || \
2414  ((DMA) == HRTIM_TIMDIER_CPT1DE) || \
2415  ((DMA) == HRTIM_TIMDIER_CPT2DE) || \
2416  ((DMA) == HRTIM_TIMDIER_SET1DE) || \
2417  ((DMA) == HRTIM_TIMDIER_RST1DE) || \
2418  ((DMA) == HRTIM_TIMDIER_SET2DE) || \
2419  ((DMA) == HRTIM_TIMDIER_RST2DE) || \
2420  ((DMA) == HRTIM_TIMDIER_RSTDE) || \
2421  ((DMA) == HRTIM_TIMDIER_DLYPRTDE))
2422 
2434 #define IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1)
2435 
2443 /* Exported macro ------------------------------------------------------------*/
2444 
2445 
2458 #define __HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->HRTIM_MASTER.MCR |= (__TIMERS__))
2459 
2460 /* The counter of a timing unit is disabled only if all the timer outputs */
2461 /* are disabled and no capture is configured */
2462 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
2463 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
2464 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
2465 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
2466 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
2467 #define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
2468  do {\
2469  if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
2470  {\
2471  ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_MASTER);\
2472  }\
2473  if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
2474  {\
2475  if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TAOEN_MASK) == RESET)\
2476  {\
2477  ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_A);\
2478  }\
2479  }\
2480  if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
2481  {\
2482  if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TBOEN_MASK) == RESET)\
2483  {\
2484  ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_B);\
2485  }\
2486  }\
2487  if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
2488  {\
2489  if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TCOEN_MASK) == RESET)\
2490  {\
2491  ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_C);\
2492  }\
2493  }\
2494  if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
2495  {\
2496  if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TDOEN_MASK) == RESET)\
2497  {\
2498  ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_D);\
2499  }\
2500  }\
2501  if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
2502  {\
2503  if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TEOEN_MASK) == RESET)\
2504  {\
2505  ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_E);\
2506  }\
2507  }\
2508  } while(0)
2509 
2510 /* Exported functions --------------------------------------------------------*/
2511 
2512 /* Simple time base related functions *****************************************/
2513 void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2514 
2515 void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
2516 
2517 void HRTIM_SimpleBaseStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx);
2518 void HRTIM_SimpleBaseStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx);
2519 
2520 /* Simple output compare related functions ************************************/
2521 void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2522 
2523 void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *HRTIMx,
2524  uint32_t TimerIdx,
2525  uint32_t OCChannel,
2526  HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg);
2527 
2528 void HRTIM_SimpleOCStart(HRTIM_TypeDef *HRTIMx,
2529  uint32_t TimerIdx,
2530  uint32_t OCChannel);
2531 void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
2532  uint32_t TimerIdx,
2533  uint32_t OCChannel);
2534 /* Simple PWM output related functions ****************************************/
2535 void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2536 
2537 void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *HRTIMx,
2538  uint32_t TimerIdx,
2539  uint32_t PWMChannel,
2540  HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg);
2541 
2542 void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
2543  uint32_t TimerIdx,
2544  uint32_t PWMChannel);
2545 void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
2546  uint32_t TimerIdx,
2547  uint32_t PWMChannel);
2548 /* Simple capture related functions *******************************************/
2549 void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2550 
2551 void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *HRTIMx,
2552  uint32_t TimerIdx,
2553  uint32_t CaptureChannel,
2554  HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg);
2555 
2556 void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
2557  uint32_t TimerIdx,
2558  uint32_t CaptureChannel);
2559 void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
2560  uint32_t TimerIdx,
2561  uint32_t CaptureChannel);
2562 /* SImple one pulse related functions *****************************************/
2563 void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
2564 
2565 void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *HRTIMx,
2566  uint32_t TimerIdx,
2567  uint32_t OnePulseChannel,
2568  HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg);
2569 
2570 void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
2571  uint32_t TimerIdx,
2572  uint32_t OnePulseChannel);
2573 void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIM_,
2574  uint32_t TimerIdx,
2575  uint32_t OnePulseChannel);
2576 /* Waveform related functions *************************************************/
2577 void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
2578  uint32_t TimerIdx,
2579  HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
2580  HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct);
2581 
2582 void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *HRTIMx,
2583  uint32_t TimerIdx,
2584  HRTIM_TimerCfgTypeDef * HRTIM_TimerCfgStruct);
2585 
2586 void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *HRTIMx,
2587  uint32_t TimerIdx,
2588  uint32_t CompareUnit,
2589  HRTIM_CompareCfgTypeDef* pCompareCfg);
2590 
2591 void HRTIM_SlaveSetCompare(HRTIM_TypeDef * HRTIMx,
2592  uint32_t TimerIdx,
2593  uint32_t CompareUnit,
2594  uint32_t Compare);
2595 
2596 void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
2597  uint32_t CompareUnit,
2598  uint32_t Compare);
2599 
2600 void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *HRTIMx,
2601  uint32_t TimerIdx,
2602  uint32_t CaptureUnit,
2603  HRTIM_CaptureCfgTypeDef* pCaptureCfg);
2604 
2605 void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *HRTIMx,
2606  uint32_t TimerIdx,
2607  uint32_t Output,
2608  HRTIM_OutputCfgTypeDef * pOutputCfg);
2609 
2610 void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *HRTIMx,
2611  uint32_t TimerIdx,
2612  uint32_t Event,
2613  HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
2614 
2615 void HRTIM_DeadTimeConfig(HRTIM_TypeDef *HRTIMx,
2616  uint32_t TimerIdx,
2617  HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
2618 
2619 void HRTIM_ChopperModeConfig(HRTIM_TypeDef *HRTIMx,
2620  uint32_t TimerIdx,
2621  HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
2622 
2623 void HRTIM_BurstDMAConfig(HRTIM_TypeDef *HRTIMx,
2624  uint32_t TimerIdx,
2625  uint32_t RegistersToUpdate);
2626 
2627 void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx,
2628  HRTIM_SynchroCfgTypeDef * pSynchroCfg);
2629 
2630 void HRTIM_BurstModeConfig(HRTIM_TypeDef *HRTIMx,
2631  HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
2632 
2633 void HRTIM_EventConfig(HRTIM_TypeDef *HRTIMx,
2634  uint32_t Event,
2635  HRTIM_EventCfgTypeDef* pEventCfg);
2636 
2637 void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *HRTIMx,
2638  uint32_t Prescaler);
2639 
2640 void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim,
2641  HRTIM_FaultCfgTypeDef* pFaultCfg,
2642  uint32_t Fault);
2643 
2644 void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *HRTIMx,
2645  uint32_t Prescaler);
2646 void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable);
2647 
2648 void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *HRTIMx,
2649  uint32_t ADCTrigger,
2650  HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
2651 
2652 void HRTIM_WaveformCounterStart(HRTIM_TypeDef *HRTIMx,
2653  uint32_t TimersToStart);
2654 
2655 void HRTIM_WaveformCounterStop(HRTIM_TypeDef *HRTIMx,
2656  uint32_t TimersToStop);
2657 
2658 void HRTIM_WaveformOutputStart(HRTIM_TypeDef *HRTIMx,
2659  uint32_t OuputsToStart);
2660 void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIM_,
2661  uint32_t OuputsToStop);
2662 
2663 void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *HRTIMx,
2664  uint32_t CalibrationRate);
2665 
2666 /* Interrupt/flags and DMA management */
2667 void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState);
2668 void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState);
2669 
2670 void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
2671 void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
2672 
2673 void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
2674 void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
2675 
2676 FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
2677 FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
2678 
2679 ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
2680 ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
2681 
2682 
2683 void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState);
2684 
2685 void HRTIM_BurstModeCtl(HRTIM_TypeDef *HRTIMx,
2686  uint32_t Enable);
2687 
2688 void HRTIM_SoftwareCapture(HRTIM_TypeDef *HRTIMx,
2689  uint32_t TimerIdx,
2690  uint32_t CaptureUnit);
2691 
2692 void HRTIM_SoftwareUpdate(HRTIM_TypeDef *HRTIMx,
2693  uint32_t TimersToUpdate);
2694 
2695 void HRTIM_SoftwareReset(HRTIM_TypeDef *HRTIMx,
2696  uint32_t TimersToReset);
2697 
2698 
2699 uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *HRTIMx,
2700  uint32_t TimerIdx,
2701  uint32_t CaptureUnit);
2702 
2703 void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIMx,
2704  uint32_t TimerIdx,
2705  uint32_t Output,
2706  HRTIM_OutputCfgTypeDef * pOutputCfg);
2707 
2708 void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *HRTIMx,
2709  uint32_t TimerIdx,
2710  uint32_t Output,
2711  uint32_t OutputLevel);
2712 
2713 uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *HRTIMx,
2714  uint32_t TimerIdx,
2715  uint32_t Output);
2716 
2717 uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
2718  uint32_t TimerIdx,
2719  uint32_t Output);
2720 
2721 uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *HRTIMx,
2722  uint32_t TimerIdx,
2723  uint32_t Output);
2724 
2725 uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *HRTIMx);
2726 
2727 uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx,
2728  uint32_t TimerIdx);
2729 
2730 uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx,
2731  uint32_t TimerIdx);
2740 #ifdef __cplusplus
2741 }
2742 #endif
2743 
2744 #endif /* __STM32F30x_HRTIM_H */
2745 
2746 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HRTIM_BaseInitTypeDef::Mode
uint32_t Mode
Definition: stm32f30x_hrtim.h:62
HRTIM_ITCommonConfig
void HRTIM_ITCommonConfig(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
Enables or disables the common interrupt request.
Definition: stm32f30x_hrtim.c:951
HRTIM_FaultCfgTypeDef::Polarity
uint32_t Polarity
Definition: stm32f30x_hrtim.h:296
HRTIM_GetIdlePushPullStatus
uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Indicates on which output the signal was applied, in push-pull mode balanced fault mode or delayed id...
Definition: stm32f30x_hrtim.c:3444
HRTIM_GetBurstStatus
uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *HRTIMx)
Returns the actual status (active or inactive) of the burst mode controller.
Definition: stm32f30x_hrtim.c:3401
FlagStatus
FlagStatus
Definition: stm32f4xx.h:706
HRTIM_SimpleOnePulseChannelConfig
void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OnePulseChannel, HRTIM_BasicOnePulseChannelCfgTypeDef *pBasicOnePulseChannelCfg)
Configures an output basic one pulse mode.
Definition: stm32f30x_hrtim.c:1742
HRTIM_TimerCfgTypeDef::PushPull
uint32_t PushPull
Definition: stm32f30x_hrtim.h:154
HRTIM_GetDelayedProtectionStatus
uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output)
Returns the level (active or inactive) of the designated output when the delayed protection was trigg...
Definition: stm32f30x_hrtim.c:3341
HRTIM_BurstDMAConfig
void HRTIM_BurstDMAConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t RegistersToUpdate)
Configures the burst DMA controller for a timer.
Definition: stm32f30x_hrtim.c:2428
HRTIM_SimpleBaseStop
void HRTIM_SimpleBaseStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Stops the counter of a timer operating in basic time base mode.
Definition: stm32f30x_hrtim.c:478
HRTIM_CaptureCfgTypeDef::Trigger
uint32_t Trigger
Definition: stm32f30x_hrtim.h:189
HRTIM_DeadTimeCfgTypeDef
Dead time feature configuration definition.
Definition: stm32f30x_hrtim.h:229
HRTIM_WaveformCaptureConfig
void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit, HRTIM_CaptureCfgTypeDef *pCaptureCfg)
Configures the capture unit of a timer operating in waveform mode.
Definition: stm32f30x_hrtim.c:2128
HRTIM_TimerInitTypeDef::PreloadEnable
uint32_t PreloadEnable
Definition: stm32f30x_hrtim.h:77
FunctionalState
FunctionalState
Definition: stm32f4xx.h:708
HRTIM_BasicOnePulseChannelCfgTypeDef::OutputIdleState
uint32_t OutputIdleState
Definition: stm32f30x_hrtim.h:138
HRTIM_BasicOnePulseChannelCfgTypeDef::EventPolarity
uint32_t EventPolarity
Definition: stm32f30x_hrtim.h:142
HRTIM_TimerInitTypeDef::BurstMode
uint32_t BurstMode
Definition: stm32f30x_hrtim.h:82
HRTIM_ClearCommonFlag
void HRTIM_ClearCommonFlag(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonFLAG)
Clears the common interrupt flags.
Definition: stm32f30x_hrtim.c:1035
HRTIM_FaultCfgTypeDef::Filter
uint32_t Filter
Definition: stm32f30x_hrtim.h:298
HRTIM_CaptureCfgTypeDef
Capture unit configuration definition.
Definition: stm32f30x_hrtim.h:188
HRTIM_TimerInitTypeDef
Waveform mode initialization parameters definition.
Definition: stm32f30x_hrtim.h:68
HRTIM_WaveformOutputStart
void HRTIM_WaveformOutputStart(HRTIM_TypeDef *HRTIMx, uint32_t OuputsToStart)
Enables the generation of the waveform signal on the designated output(s) Outputs can be combined (OR...
Definition: stm32f30x_hrtim.c:829
HRTIM_BurstModeCfgTypeDef::PreloadEnable
uint32_t PreloadEnable
Definition: stm32f30x_hrtim.h:314
HRTIM_TimerCfgTypeDef
Timer configuration definition.
Definition: stm32f30x_hrtim.h:153
HRTIM_BasicCaptureChannelCfgTypeDef::Event
uint32_t Event
Definition: stm32f30x_hrtim.h:120
HRTIM_SimpleOnePulse_Init
void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic one pulse mode.
Definition: stm32f30x_hrtim.c:334
HRTIM_SimplePWM_Init
void HRTIM_SimplePWM_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic PWM mode.
Definition: stm32f30x_hrtim.c:295
HRTIM_BasicPWMChannelCfgTypeDef::IdleState
uint32_t IdleState
Definition: stm32f30x_hrtim.h:110
HRTIM_BasicOnePulseChannelCfgTypeDef::OutputPolarity
uint32_t OutputPolarity
Definition: stm32f30x_hrtim.h:136
HRTIM_TimerInitTypeDef::StartOnSync
uint32_t StartOnSync
Definition: stm32f30x_hrtim.h:71
HRTIM_BasicOCChannelCfgTypeDef::Mode
uint32_t Mode
Definition: stm32f30x_hrtim.h:92
HRTIM_FaultCfgTypeDef::Lock
uint32_t Lock
Definition: stm32f30x_hrtim.h:300
HRTIM_BurstModeCfgTypeDef::Period
uint32_t Period
Definition: stm32f30x_hrtim.h:320
HRTIM_GetCapturedValue
uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit)
Returns actual value of the capture register of the designated capture unit.
Definition: stm32f30x_hrtim.c:3101
HRTIM_BaseInitTypeDef
HRTIM Configuration Structure definition - Time base related parameters.
Definition: stm32f30x_hrtim.h:53
HRTIM_TimerCfgTypeDef::FaultLock
uint32_t FaultLock
Definition: stm32f30x_hrtim.h:158
HRTIM_BurstModeCfgTypeDef::Trigger
uint32_t Trigger
Definition: stm32f30x_hrtim.h:316
HRTIM_SynchroCfgTypeDef
Master synchronization configuration definition.
Definition: stm32f30x_hrtim.h:265
HRTIM_BasicCaptureChannelCfgTypeDef::EventPolarity
uint32_t EventPolarity
Definition: stm32f30x_hrtim.h:122
HRTIM_BaseInitTypeDef::PrescalerRatio
uint32_t PrescalerRatio
Definition: stm32f30x_hrtim.h:60
HRTIM_TimerInitTypeDef::HalfModeEnable
uint32_t HalfModeEnable
Definition: stm32f30x_hrtim.h:69
HRTIM_EventPrescalerConfig
void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
Configures the external event conditioning block prescaler.
Definition: stm32f30x_hrtim.c:2599
HRTIM_EventCfgTypeDef::Source
uint32_t Source
Definition: stm32f30x_hrtim.h:278
HRTIM_EventCfgTypeDef::Sensitivity
uint32_t Sensitivity
Definition: stm32f30x_hrtim.h:282
HRTIM_BurstModeCfgTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32f30x_hrtim.h:312
HRTIM_DMACmd
void HRTIM_DMACmd(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
Enables or disables the HRTIMx&#39;s DMA Requests.
Definition: stm32f30x_hrtim.c:1373
HRTIM_ChopperModeCfgTypeDef
Chopper mode configuration definition.
Definition: stm32f30x_hrtim.h:253
HRTIM_WaveformOutputStop
void HRTIM_WaveformOutputStop(HRTIM_TypeDef *HRTIM_, uint32_t OuputsToStop)
Disables the generation of the waveform signal on the designated output(s) Outputs can be combined (O...
Definition: stm32f30x_hrtim.c:854
HRTIM_CompareCfgTypeDef::AutoDelayedTimeout
uint32_t AutoDelayedTimeout
Definition: stm32f30x_hrtim.h:181
HRTIM_OutputCfgTypeDef::ChopperModeEnable
uint32_t ChopperModeEnable
Definition: stm32f30x_hrtim.h:209
HRTIM_DeadTimeCfgTypeDef::RisingLock
uint32_t RisingLock
Definition: stm32f30x_hrtim.h:236
HRTIM_FaultModeCtl
void HRTIM_FaultModeCtl(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Enable)
Enables or disables the HRTIMx Fault mode.
Definition: stm32f30x_hrtim.c:2747
HRTIM_WaveformSetOutputLevel
void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel)
Forces the timer output to its active or inactive state.
Definition: stm32f30x_hrtim.c:3016
HRTIM_TimerCfgTypeDef::ResetTrigger
uint32_t ResetTrigger
Definition: stm32f30x_hrtim.h:166
HRTIM_WaveformCompareConfig
void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg)
Configures the compare unit of a timer operating in waveform mode.
Definition: stm32f30x_hrtim.c:1932
HRTIM_DeadTimeConfig
void HRTIM_DeadTimeConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
Configures the dead time insertion feature for a timer.
Definition: stm32f30x_hrtim.c:2327
HRTIM_ClearITPendingBit
void HRTIM_ClearITPendingBit(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
Clears the Master and slaves interrupt request pending bits.
Definition: stm32f30x_hrtim.c:1071
HRTIM_EventCfgTypeDef::Filter
uint32_t Filter
Definition: stm32f30x_hrtim.h:284
HRTIM_ADCTriggerCfgTypeDef::Trigger
uint32_t Trigger
Definition: stm32f30x_hrtim.h:330
HRTIM_SoftwareCapture
void HRTIM_SoftwareCapture(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit)
Triggers a software capture on the designed capture unit.
Definition: stm32f30x_hrtim.c:2912
HRTIM_ChopperModeCfgTypeDef::DutyCycle
uint32_t DutyCycle
Definition: stm32f30x_hrtim.h:256
HRTIM_DeadTimeCfgTypeDef::RisingSignLock
uint32_t RisingSignLock
Definition: stm32f30x_hrtim.h:238
HRTIM_EventCfgTypeDef
External event channel configuration definition.
Definition: stm32f30x_hrtim.h:277
HRTIM_SimpleOCStart
void HRTIM_SimpleOCStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output.
Definition: stm32f30x_hrtim.c:507
HRTIM_OutputCfgTypeDef::IdleMode
uint32_t IdleMode
Definition: stm32f30x_hrtim.h:203
HRTIM_SimpleBaseStart
void HRTIM_SimpleBaseStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Starts the counter of a timer operating in basic time base mode.
Definition: stm32f30x_hrtim.c:460
HRTIM_ADCTriggerCfgTypeDef::UpdateSource
uint32_t UpdateSource
Definition: stm32f30x_hrtim.h:328
HRTIM_GetCurrentPushPullStatus
uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Indicates on which output the signal is currently active (when the push pull mode is enabled) ...
Definition: stm32f30x_hrtim.c:3420
HRTIM_TimerEventFilteringCfgTypeDef::Latch
uint32_t Latch
Definition: stm32f30x_hrtim.h:222
HRTIM_ClearCommonITPendingBit
void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT)
Clears the common interrupt pending bits.
Definition: stm32f30x_hrtim.c:1112
HRTIM_TimerEventFilteringCfgTypeDef::Filter
uint32_t Filter
Definition: stm32f30x_hrtim.h:220
HRTIM_BurstModeCfgTypeDef::Mode
uint32_t Mode
Definition: stm32f30x_hrtim.h:308
HRTIM_CompareCfgTypeDef::CompareValue
uint32_t CompareValue
Definition: stm32f30x_hrtim.h:176
HRTIM_DeadTimeCfgTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32f30x_hrtim.h:230
HRTIM_DeadTimeCfgTypeDef::FallingLock
uint32_t FallingLock
Definition: stm32f30x_hrtim.h:244
HRTIM_SimpleCaptureStop
void HRTIM_SimpleCaptureStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit.
Definition: stm32f30x_hrtim.c:667
HRTIM_BurstModeCtl
void HRTIM_BurstModeCtl(HRTIM_TypeDef *HRTIMx, uint32_t Enable)
Enables or disables the HRTIMx burst mode controller.
Definition: stm32f30x_hrtim.c:2882
HRTIM_BasicOnePulseChannelCfgTypeDef::EventSensitivity
uint32_t EventSensitivity
Definition: stm32f30x_hrtim.h:144
HRTIM_BasicCaptureChannelCfgTypeDef::EventSensitivity
uint32_t EventSensitivity
Definition: stm32f30x_hrtim.h:124
HRTIM_ChopperModeCfgTypeDef::StartPulse
uint32_t StartPulse
Definition: stm32f30x_hrtim.h:258
HRTIM_TimerInitTypeDef::DACSynchro
uint32_t DACSynchro
Definition: stm32f30x_hrtim.h:75
HRTIM_FaultPrescalerConfig
void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
Configures the fault conditioning block prescaler.
Definition: stm32f30x_hrtim.c:2714
HRTIM_ClearFlag
void HRTIM_ClearFlag(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
Clears the Master and slaves interrupt flags.
Definition: stm32f30x_hrtim.c:994
ITStatus
enum FlagStatus ITStatus
HRTIM_OutputCfgTypeDef::ResetSource
uint32_t ResetSource
Definition: stm32f30x_hrtim.h:201
HRTIM_BasicPWMChannelCfgTypeDef::Pulse
uint32_t Pulse
Definition: stm32f30x_hrtim.h:106
HRTIM_ChopperModeConfig
void HRTIM_ChopperModeConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
Configures the chopper mode feature for a timer.
Definition: stm32f30x_hrtim.c:2373
HRTIM_OutputCfgTypeDef::SetSource
uint32_t SetSource
Definition: stm32f30x_hrtim.h:199
HRTIM_GetFlagStatus
FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
Checks whether the specified HRTIM flag is set or not.
Definition: stm32f30x_hrtim.c:1149
HRTIM_SimpleCaptureChannelConfig
void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel, HRTIM_BasicCaptureChannelCfgTypeDef *pBasicCaptureChannelCfg)
Configures a basic capture.
Definition: stm32f30x_hrtim.c:1678
HRTIM_OutputCfgTypeDef
Output configuration definition.
Definition: stm32f30x_hrtim.h:196
HRTIM_SimpleOCChannelConfig
void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel, HRTIM_BasicOCChannelCfgTypeDef *pBasicOCChannelCfg)
Configures an output in basic output compare mode.
Definition: stm32f30x_hrtim.c:1460
HRTIM_TimerInitTypeDef::RepetitionUpdate
uint32_t RepetitionUpdate
Definition: stm32f30x_hrtim.h:84
HRTIM_BaseInitTypeDef::Period
uint32_t Period
Definition: stm32f30x_hrtim.h:55
HRTIM_FaultCfgTypeDef::Source
uint32_t Source
Definition: stm32f30x_hrtim.h:294
HRTIM_ITConfig
void HRTIM_ITConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState)
Enables or disables the Master and slaves interrupt request.
Definition: stm32f30x_hrtim.c:894
HRTIM_CompareCfgTypeDef
Compare unit configuration definition.
Definition: stm32f30x_hrtim.h:175
HRTIM_SoftwareReset
void HRTIM_SoftwareReset(HRTIM_TypeDef *HRTIMx, uint32_t TimersToReset)
Triggers the reset of one or several timers.
Definition: stm32f30x_hrtim.c:2979
HRTIM_BasicOnePulseChannelCfgTypeDef::Event
uint32_t Event
Definition: stm32f30x_hrtim.h:140
HRTIM_BasicCaptureChannelCfgTypeDef::CaptureUnit
uint32_t CaptureUnit
Definition: stm32f30x_hrtim.h:118
HRTIM_BasicOnePulseChannelCfgTypeDef::Pulse
uint32_t Pulse
Definition: stm32f30x_hrtim.h:134
HRTIM_TimerEventFilteringConfig
void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Event, HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
Configures the event filtering capabilities of a timer (blanking, windowing)
Definition: stm32f30x_hrtim.c:2211
HRTIM_CompareCfgTypeDef::AutoDelayedMode
uint32_t AutoDelayedMode
Definition: stm32f30x_hrtim.h:179
HRTIM_MasterSetCompare
void HRTIM_MasterSetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareUnit, uint32_t Compare)
Sets the HRTIMx Master Comparex Register value.
Definition: stm32f30x_hrtim.c:2025
HRTIM_ADCTriggerCfgTypeDef
ADC trigger configuration definition.
Definition: stm32f30x_hrtim.h:327
HRTIM_TimerInitTypeDef::ResetOnSync
uint32_t ResetOnSync
Definition: stm32f30x_hrtim.h:73
HRTIM_WaveformGetOutputLevel
uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output)
Returns actual level (active or inactive) of the designated output.
Definition: stm32f30x_hrtim.c:3153
HRTIM_TimerCfgTypeDef::FaultEnable
uint32_t FaultEnable
Definition: stm32f30x_hrtim.h:156
HRTIM_SimplePWMStop
void HRTIM_SimplePWMStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output.
Definition: stm32f30x_hrtim.c:610
HRTIM_SimpleOnePulseStop
void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef *HRTIM_, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the basic one pulse signal generation on the designed output.
Definition: stm32f30x_hrtim.c:755
HRTIM_WaveformCounterStart
void HRTIM_WaveformCounterStart(HRTIM_TypeDef *HRTIMx, uint32_t TimersToStart)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed...
Definition: stm32f30x_hrtim.c:783
HRTIM_DeadTimeCfgTypeDef::RisingValue
uint32_t RisingValue
Definition: stm32f30x_hrtim.h:232
HRTIM_BurstModeCfgTypeDef
Burst mode configuration definition.
Definition: stm32f30x_hrtim.h:307
HRTIM_BaseInitTypeDef::RepetitionCounter
uint32_t RepetitionCounter
Definition: stm32f30x_hrtim.h:58
HRTIM_BasicOnePulseChannelCfgTypeDef::EventFilter
uint32_t EventFilter
Definition: stm32f30x_hrtim.h:146
HRTIM_TimerInitTypeDef::UpdateGating
uint32_t UpdateGating
Definition: stm32f30x_hrtim.h:79
HRTIM_BasicOCChannelCfgTypeDef
Basic output compare mode configuration definition.
Definition: stm32f30x_hrtim.h:91
HRTIM_DeInit
void HRTIM_DeInit(HRTIM_TypeDef *HRTIMx)
De-initializes a timer operating in all mode.
Definition: stm32f30x_hrtim.c:255
HRTIM_BasicPWMChannelCfgTypeDef
Basic PWM output mode configuration definition.
Definition: stm32f30x_hrtim.h:105
HRTIM_TimerEventFilteringCfgTypeDef
External event filtering in timing units configuration definition.
Definition: stm32f30x_hrtim.h:219
HRTIM_BasicCaptureChannelCfgTypeDef::EventFilter
uint32_t EventFilter
Definition: stm32f30x_hrtim.h:126
HRTIM_ADCTriggerConfig
void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrigger, HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
Configures both the ADC trigger register update source and the ADC trigger source.
Definition: stm32f30x_hrtim.c:2814
HRTIM_SynchronizationConfig
void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef *pSynchroCfg)
Configures the external input/output synchronization of the HRTIMx.
Definition: stm32f30x_hrtim.c:2479
HRTIM_SimplePWMStart
void HRTIM_SimplePWMStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output.
Definition: stm32f30x_hrtim.c:576
HRTIM_OutputCfgTypeDef::BurstModeEntryDelayed
uint32_t BurstModeEntryDelayed
Definition: stm32f30x_hrtim.h:211
HRTIM_DLLCalibrationStart
void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *HRTIMx, uint32_t CalibrationRate)
Starts the DLL calibration.
Definition: stm32f30x_hrtim.c:424
HRTIM_OutputCfgTypeDef::FaultState
uint32_t FaultState
Definition: stm32f30x_hrtim.h:207
HRTIM_SimpleCapture_Init
void HRTIM_SimpleCapture_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes a timer operating in basic capture mode.
Definition: stm32f30x_hrtim.c:313
HRTIM_TimerCfgTypeDef::DeadTimeInsertion
uint32_t DeadTimeInsertion
Definition: stm32f30x_hrtim.h:160
HRTIM_WaveformCounterStop
void HRTIM_WaveformCounterStop(HRTIM_TypeDef *HRTIMx, uint32_t TimersToStop)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed)...
Definition: stm32f30x_hrtim.c:804
HRTIM_GetCommonFlagStatus
FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonFLAG)
Checks whether the specified HRTIM common flag is set or not.
Definition: stm32f30x_hrtim.c:1208
HRTIM_BasicOnePulseChannelCfgTypeDef
Basic One Pulse mode configuration definition.
Definition: stm32f30x_hrtim.h:133
HRTIM_WaveformTimerConfig
void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *HRTIM_TimerCfgStruct)
Configures the general behavior of a timer operating in waveform mode.
Definition: stm32f30x_hrtim.c:1846
HRTIM_EventCfgTypeDef::Polarity
uint32_t Polarity
Definition: stm32f30x_hrtim.h:280
HRTIM_TimerCfgTypeDef::DelayedProtectionMode
uint32_t DelayedProtectionMode
Definition: stm32f30x_hrtim.h:162
HRTIM_GetCommonITStatus
ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT)
Checks whether the specified HRTIM common interrupt has occurred or not.
Definition: stm32f30x_hrtim.c:1320
HRTIM_BurstModeConfig
void HRTIM_BurstModeConfig(HRTIM_TypeDef *HRTIMx, HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
Configures the burst mode feature of the HRTIMx.
Definition: stm32f30x_hrtim.c:2512
HRTIM_BasicOCChannelCfgTypeDef::Polarity
uint32_t Polarity
Definition: stm32f30x_hrtim.h:96
HRTIM_DeadTimeCfgTypeDef::RisingSign
uint32_t RisingSign
Definition: stm32f30x_hrtim.h:234
HRTIM_SimpleBase_Init
void HRTIM_SimpleBase_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic time base mode.
Definition: stm32f30x_hrtim.c:228
HRTIM_SynchroCfgTypeDef::SyncInputSource
uint32_t SyncInputSource
Definition: stm32f30x_hrtim.h:266
HRTIM_GetITStatus
ITStatus HRTIM_GetITStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
Checks whether the specified HRTIM interrupt has occurred or not.
Definition: stm32f30x_hrtim.c:1254
HRTIM_SynchroCfgTypeDef::SyncOutputSource
uint32_t SyncOutputSource
Definition: stm32f30x_hrtim.h:268
HRTIM_ChopperModeCfgTypeDef::CarrierFreq
uint32_t CarrierFreq
Definition: stm32f30x_hrtim.h:254
HRTIM_SlaveSetCompare
void HRTIM_SlaveSetCompare(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, uint32_t Compare)
Sets the HRTIMx Slave Comparex Register value.
Definition: stm32f30x_hrtim.c:2076
HRTIM_WaveformGetOutputState
uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output)
Returns actual state (RUN, IDLE, FAULT) of the designated output.
Definition: stm32f30x_hrtim.c:3228
HRTIM_SimpleOC_Init
void HRTIM_SimpleOC_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic output compare mode.
Definition: stm32f30x_hrtim.c:275
HRTIM_TimerCfgTypeDef::ResetUpdate
uint32_t ResetUpdate
Definition: stm32f30x_hrtim.h:168
HRTIM_BasicPWMChannelCfgTypeDef::Polarity
uint32_t Polarity
Definition: stm32f30x_hrtim.h:108
HRTIM_FaultCfgTypeDef
Fault channel configuration definition.
Definition: stm32f30x_hrtim.h:293
HRTIM_BurstModeCfgTypeDef::IdleDuration
uint32_t IdleDuration
Definition: stm32f30x_hrtim.h:318
HRTIM_BasicOCChannelCfgTypeDef::IdleState
uint32_t IdleState
Definition: stm32f30x_hrtim.h:98
HRTIM_BurstModeCfgTypeDef::ClockSource
uint32_t ClockSource
Definition: stm32f30x_hrtim.h:310
HRTIM_EventCfgTypeDef::FastMode
uint32_t FastMode
Definition: stm32f30x_hrtim.h:286
HRTIM_SoftwareUpdate
void HRTIM_SoftwareUpdate(HRTIM_TypeDef *HRTIMx, uint32_t TimersToUpdate)
Triggers the update of the registers of one or several timers.
Definition: stm32f30x_hrtim.c:2953
HRTIM_SynchroCfgTypeDef::SyncOutputPolarity
uint32_t SyncOutputPolarity
Definition: stm32f30x_hrtim.h:270
HRTIM_OutputCfgTypeDef::IdleState
uint32_t IdleState
Definition: stm32f30x_hrtim.h:205
HRTIM_DeadTimeCfgTypeDef::FallingSignLock
uint32_t FallingSignLock
Definition: stm32f30x_hrtim.h:246
HRTIM_BasicCaptureChannelCfgTypeDef
Basic capture mode configuration definition.
Definition: stm32f30x_hrtim.h:117
HRTIM_BasicOCChannelCfgTypeDef::Pulse
uint32_t Pulse
Definition: stm32f30x_hrtim.h:94
HRTIM_TimerCfgTypeDef::UpdateTrigger
uint32_t UpdateTrigger
Definition: stm32f30x_hrtim.h:164
HRTIM_DeadTimeCfgTypeDef::FallingSign
uint32_t FallingSign
Definition: stm32f30x_hrtim.h:242
HRTIM_DeadTimeCfgTypeDef::FallingValue
uint32_t FallingValue
Definition: stm32f30x_hrtim.h:240
HRTIM_WaveformOutputConfig
void HRTIM_WaveformOutputConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
Configures the output of a timer operating in waveform mode.
Definition: stm32f30x_hrtim.c:2172
HRTIM_FaultConfig
void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim, HRTIM_FaultCfgTypeDef *pFaultCfg, uint32_t Fault)
Configures the conditioning of fault input.
Definition: stm32f30x_hrtim.c:2629
HRTIM_OutputCfgTypeDef::Polarity
uint32_t Polarity
Definition: stm32f30x_hrtim.h:197
HRTIM_WaveformOuputConfig
void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
HRTIM_EventConfig
void HRTIM_EventConfig(HRTIM_TypeDef *HRTIMx, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg)
Configures the conditioning of an external event.
Definition: stm32f30x_hrtim.c:2572
HRTIM_SimpleOnePulseStart
void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the basic one pulse signal generation on the designed output.
Definition: stm32f30x_hrtim.c:721
HRTIM_SimplePWMChannelConfig
void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel, HRTIM_BasicPWMChannelCfgTypeDef *pBasicPWMChannelCfg)
Configures an output in basic PWM mode.
Definition: stm32f30x_hrtim.c:1592
HRTIM_SimpleCaptureStart
void HRTIM_SimpleCaptureStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a basic capture on the designed capture unit.
Definition: stm32f30x_hrtim.c:643
HRTIM_SimpleOCStop
void HRTIM_SimpleOCStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output.
Definition: stm32f30x_hrtim.c:542
HRTIM_Waveform_Init
void HRTIM_Waveform_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct, HRTIM_TimerInitTypeDef *HRTIM_TimerInitStruct)
Initializes a timer operating in waveform mode.
Definition: stm32f30x_hrtim.c:354

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Wed Jul 3 2019 19:59:25