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#define | IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81906E00) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC880CC) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFC886CC) == 0x00) && ((PERIPH) != 0x00)) |
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#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
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#define | IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) |
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#define | IS_RCC_FLAG(FLAG) |
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#define | IS_RCC_GET_IT(IT) |
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#define | IS_RCC_HCLK(HCLK) |
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#define | IS_RCC_HSE(HSE) |
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#define | IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) |
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#define | IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) |
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#define | IS_RCC_LSE(LSE) |
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#define | IS_RCC_MCO1DIV(DIV) |
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#define | IS_RCC_MCO1SOURCE(SOURCE) |
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#define | IS_RCC_MCO2DIV(DIV) |
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#define | IS_RCC_MCO2SOURCE(SOURCE) |
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#define | IS_RCC_PCLK(PCLK) |
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#define | IS_RCC_PLL_SOURCE(SOURCE) |
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#define | IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
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#define | IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
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#define | IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) |
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#define | IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
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#define | IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) |
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#define | IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) |
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#define | IS_RCC_RTCCLK_SOURCE(SOURCE) |
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#define | IS_RCC_SYSCLK_SOURCE(SOURCE) |
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#define | IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) |
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#define | RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) |
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#define | RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) |
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#define | RCC_AHB1Periph_CRC ((uint32_t)0x00001000) |
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#define | RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) |
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#define | RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) |
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#define | RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) |
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#define | RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) |
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#define | RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) |
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#define | RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) |
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#define | RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) |
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#define | RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) |
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#define | RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) |
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#define | RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) |
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#define | RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) |
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#define | RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) |
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#define | RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) |
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#define | RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) |
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#define | RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) |
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#define | RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) |
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#define | RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) |
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#define | RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) |
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#define | RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) |
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#define | RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) |
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#define | RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) |
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#define | RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) |
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#define | RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) |
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#define | RCC_AHB2Periph_HASH ((uint32_t)0x00000020) |
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#define | RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) |
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#define | RCC_AHB2Periph_RNG ((uint32_t)0x00000040) |
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#define | RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) |
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#define | RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
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#define | RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
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#define | RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
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#define | RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
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#define | RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
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#define | RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) |
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#define | RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
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#define | RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
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#define | RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
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#define | RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
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#define | RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
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#define | RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
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#define | RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
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#define | RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
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#define | RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
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#define | RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
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#define | RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
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#define | RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
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#define | RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
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#define | RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
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#define | RCC_APB1Periph_UART7 ((uint32_t)0x40000000) |
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#define | RCC_APB1Periph_UART8 ((uint32_t)0x80000000) |
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#define | RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
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#define | RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
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#define | RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
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#define | RCC_APB2Periph_ADC ((uint32_t)0x00000100) |
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#define | RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) |
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#define | RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) |
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#define | RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) |
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#define | RCC_APB2Periph_SDIO ((uint32_t)0x00000800) |
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#define | RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
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#define | RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) |
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#define | RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) |
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#define | RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) |
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#define | RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) |
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#define | RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) |
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#define | RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) |
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#define | RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) |
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#define | RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) |
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#define | RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) |
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#define | RCC_APB2Periph_USART1 ((uint32_t)0x00000010) |
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#define | RCC_APB2Periph_USART6 ((uint32_t)0x00000020) |
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#define | RCC_FLAG_BORRST ((uint8_t)0x79) |
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#define | RCC_FLAG_HSERDY ((uint8_t)0x31) |
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#define | RCC_FLAG_HSIRDY ((uint8_t)0x21) |
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#define | RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
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#define | RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
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#define | RCC_FLAG_LSERDY ((uint8_t)0x41) |
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#define | RCC_FLAG_LSIRDY ((uint8_t)0x61) |
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#define | RCC_FLAG_PINRST ((uint8_t)0x7A) |
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#define | RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) |
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#define | RCC_FLAG_PLLRDY ((uint8_t)0x39) |
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#define | RCC_FLAG_PORRST ((uint8_t)0x7B) |
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#define | RCC_FLAG_SFTRST ((uint8_t)0x7C) |
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#define | RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
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#define | RCC_HCLK_Div1 ((uint32_t)0x00000000) |
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#define | RCC_HCLK_Div16 ((uint32_t)0x00001C00) |
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#define | RCC_HCLK_Div2 ((uint32_t)0x00001000) |
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#define | RCC_HCLK_Div4 ((uint32_t)0x00001400) |
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#define | RCC_HCLK_Div8 ((uint32_t)0x00001800) |
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#define | RCC_HSE_Bypass ((uint8_t)0x05) |
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#define | RCC_HSE_OFF ((uint8_t)0x00) |
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#define | RCC_HSE_ON ((uint8_t)0x01) |
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#define | RCC_I2S2CLKSource_Ext ((uint8_t)0x01) |
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#define | RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) |
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#define | RCC_IT_CSS ((uint8_t)0x80) |
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#define | RCC_IT_HSERDY ((uint8_t)0x08) |
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#define | RCC_IT_HSIRDY ((uint8_t)0x04) |
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#define | RCC_IT_LSERDY ((uint8_t)0x02) |
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#define | RCC_IT_LSIRDY ((uint8_t)0x01) |
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#define | RCC_IT_PLLI2SRDY ((uint8_t)0x20) |
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#define | RCC_IT_PLLRDY ((uint8_t)0x10) |
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#define | RCC_LSE_Bypass ((uint8_t)0x04) |
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#define | RCC_LSE_OFF ((uint8_t)0x00) |
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#define | RCC_LSE_ON ((uint8_t)0x01) |
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#define | RCC_MCO1Div_1 ((uint32_t)0x00000000) |
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#define | RCC_MCO1Div_2 ((uint32_t)0x04000000) |
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#define | RCC_MCO1Div_3 ((uint32_t)0x05000000) |
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#define | RCC_MCO1Div_4 ((uint32_t)0x06000000) |
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#define | RCC_MCO1Div_5 ((uint32_t)0x07000000) |
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#define | RCC_MCO1Source_HSE ((uint32_t)0x00400000) |
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#define | RCC_MCO1Source_HSI ((uint32_t)0x00000000) |
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#define | RCC_MCO1Source_LSE ((uint32_t)0x00200000) |
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#define | RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) |
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#define | RCC_MCO2Div_1 ((uint32_t)0x00000000) |
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#define | RCC_MCO2Div_2 ((uint32_t)0x20000000) |
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#define | RCC_MCO2Div_3 ((uint32_t)0x28000000) |
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#define | RCC_MCO2Div_4 ((uint32_t)0x30000000) |
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#define | RCC_MCO2Div_5 ((uint32_t)0x38000000) |
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#define | RCC_MCO2Source_HSE ((uint32_t)0x80000000) |
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#define | RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) |
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#define | RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) |
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#define | RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) |
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#define | RCC_PLLSource_HSE ((uint32_t)0x00400000) |
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#define | RCC_PLLSource_HSI ((uint32_t)0x00000000) |
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#define | RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) |
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#define | RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) |
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#define | RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) |
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#define | RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) |
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#define | RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) |
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#define | RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) |
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#define | RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) |
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#define | RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) |
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#define | RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) |
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#define | RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) |
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#define | RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) |
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#define | RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) |
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#define | RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) |
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#define | RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) |
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#define | RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) |
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#define | RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) |
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#define | RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) |
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#define | RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) |
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#define | RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) |
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#define | RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) |
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#define | RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) |
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#define | RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) |
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#define | RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) |
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#define | RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) |
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#define | RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) |
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#define | RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) |
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#define | RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) |
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#define | RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) |
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#define | RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) |
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#define | RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) |
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#define | RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
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#define | RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
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#define | RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
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#define | RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
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#define | RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
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#define | RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
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#define | RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
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#define | RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
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#define | RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
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#define | RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
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#define | RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
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#define | RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
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#define | RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
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#define | RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
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#define | RCC_TIMPrescActivated ((uint8_t)0x01) |
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#define | RCC_TIMPrescDesactivated ((uint8_t)0x00) |
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