stm32f10x_sdio.c
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1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_sdio.h"
24 #include "stm32f10x_rcc.h"
25 
39 /* ------------ SDIO registers bit address in the alias region ----------- */
40 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
41 
42 /* --- CLKCR Register ---*/
43 
44 /* Alias word address of CLKEN bit */
45 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
46 #define CLKEN_BitNumber 0x08
47 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
48 
49 /* --- CMD Register ---*/
50 
51 /* Alias word address of SDIOSUSPEND bit */
52 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
53 #define SDIOSUSPEND_BitNumber 0x0B
54 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
55 
56 /* Alias word address of ENCMDCOMPL bit */
57 #define ENCMDCOMPL_BitNumber 0x0C
58 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
59 
60 /* Alias word address of NIEN bit */
61 #define NIEN_BitNumber 0x0D
62 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
63 
64 /* Alias word address of ATACMD bit */
65 #define ATACMD_BitNumber 0x0E
66 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
67 
68 /* --- DCTRL Register ---*/
69 
70 /* Alias word address of DMAEN bit */
71 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
72 #define DMAEN_BitNumber 0x03
73 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
74 
75 /* Alias word address of RWSTART bit */
76 #define RWSTART_BitNumber 0x08
77 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
78 
79 /* Alias word address of RWSTOP bit */
80 #define RWSTOP_BitNumber 0x09
81 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
82 
83 /* Alias word address of RWMOD bit */
84 #define RWMOD_BitNumber 0x0A
85 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
86 
87 /* Alias word address of SDIOEN bit */
88 #define SDIOEN_BitNumber 0x0B
89 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
90 
91 /* ---------------------- SDIO registers bit mask ------------------------ */
92 
93 /* --- CLKCR Register ---*/
94 
95 /* CLKCR register clear mask */
96 #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
97 
98 /* --- PWRCTRL Register ---*/
99 
100 /* SDIO PWRCTRL Mask */
101 #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
102 
103 /* --- DCTRL Register ---*/
104 
105 /* SDIO DCTRL Clear Mask */
106 #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
107 
108 /* --- CMD Register ---*/
109 
110 /* CMD Register clear mask */
111 #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
112 
113 /* SDIO RESP Registers Address */
114 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
115 
161 void SDIO_DeInit(void)
162 {
163  SDIO->POWER = 0x00000000;
164  SDIO->CLKCR = 0x00000000;
165  SDIO->ARG = 0x00000000;
166  SDIO->CMD = 0x00000000;
167  SDIO->DTIMER = 0x00000000;
168  SDIO->DLEN = 0x00000000;
169  SDIO->DCTRL = 0x00000000;
170  SDIO->ICR = 0x00C007FF;
171  SDIO->MASK = 0x00000000;
172 }
173 
181 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
182 {
183  uint32_t tmpreg = 0;
184 
185  /* Check the parameters */
189  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
191 
192 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
193  /* Get the SDIO CLKCR value */
194  tmpreg = SDIO->CLKCR;
195 
196  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
197  tmpreg &= CLKCR_CLEAR_MASK;
198 
199  /* Set CLKDIV bits according to SDIO_ClockDiv value */
200  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
201  /* Set BYPASS bit according to SDIO_ClockBypass value */
202  /* Set WIDBUS bits according to SDIO_BusWide value */
203  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
204  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
205  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
206  SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
207  SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
208 
209  /* Write to SDIO CLKCR */
210  SDIO->CLKCR = tmpreg;
211 }
212 
219 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
220 {
221  /* SDIO_InitStruct members default value */
222  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
223  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
224  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
226  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
228 }
229 
236 {
237  /* Check the parameters */
239 
240  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
241 }
242 
251 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
252 {
253  /* Check the parameters */
254  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
255 
256  SDIO->POWER &= PWR_PWRCTRL_MASK;
257  SDIO->POWER |= SDIO_PowerState;
258 }
259 
269 uint32_t SDIO_GetPowerState(void)
270 {
271  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
272 }
273 
307 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
308 {
309  /* Check the parameters */
310  assert_param(IS_SDIO_IT(SDIO_IT));
312 
313  if (NewState != DISABLE)
314  {
315  /* Enable the SDIO interrupts */
316  SDIO->MASK |= SDIO_IT;
317  }
318  else
319  {
320  /* Disable the SDIO interrupts */
321  SDIO->MASK &= ~SDIO_IT;
322  }
323 }
324 
332 {
333  /* Check the parameters */
335 
336  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
337 }
338 
346 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
347 {
348  uint32_t tmpreg = 0;
349 
350  /* Check the parameters */
351  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
352  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
353  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
354  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
355 
356 /*---------------------------- SDIO ARG Configuration ------------------------*/
357  /* Set the SDIO Argument value */
358  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
359 
360 /*---------------------------- SDIO CMD Configuration ------------------------*/
361  /* Get the SDIO CMD value */
362  tmpreg = SDIO->CMD;
363  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
364  tmpreg &= CMD_CLEAR_MASK;
365  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
366  /* Set WAITRESP bits according to SDIO_Response value */
367  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
368  /* Set CPSMEN bits according to SDIO_CPSM value */
369  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
370  | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
371 
372  /* Write to SDIO CMD */
373  SDIO->CMD = tmpreg;
374 }
375 
382 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
383 {
384  /* SDIO_CmdInitStruct members default value */
385  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
386  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
387  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
388  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
389  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
390 }
391 
398 {
399  return (uint8_t)(SDIO->RESPCMD);
400 }
401 
412 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
413 {
414  __IO uint32_t tmp = 0;
415 
416  /* Check the parameters */
417  assert_param(IS_SDIO_RESP(SDIO_RESP));
418 
419  tmp = SDIO_RESP_ADDR + SDIO_RESP;
420 
421  return (*(__IO uint32_t *) tmp);
422 }
423 
431 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
432 {
433  uint32_t tmpreg = 0;
434 
435  /* Check the parameters */
436  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
437  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
438  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
440  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
441 
442 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
443  /* Set the SDIO Data TimeOut value */
444  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
445 
446 /*---------------------------- SDIO DLEN Configuration -----------------------*/
447  /* Set the SDIO DataLength value */
448  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
449 
450 /*---------------------------- SDIO DCTRL Configuration ----------------------*/
451  /* Get the SDIO DCTRL value */
452  tmpreg = SDIO->DCTRL;
453  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
454  tmpreg &= DCTRL_CLEAR_MASK;
455  /* Set DEN bit according to SDIO_DPSM value */
456  /* Set DTMODE bit according to SDIO_TransferMode value */
457  /* Set DTDIR bit according to SDIO_TransferDir value */
458  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
459  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
460  | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
461 
462  /* Write to SDIO DCTRL */
463  SDIO->DCTRL = tmpreg;
464 }
465 
472 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
473 {
474  /* SDIO_DataInitStruct members default value */
475  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
476  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
477  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
478  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
479  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
480  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
481 }
482 
488 uint32_t SDIO_GetDataCounter(void)
489 {
490  return SDIO->DCOUNT;
491 }
492 
498 uint32_t SDIO_ReadData(void)
499 {
500  return SDIO->FIFO;
501 }
502 
508 void SDIO_WriteData(uint32_t Data)
509 {
510  SDIO->FIFO = Data;
511 }
512 
518 uint32_t SDIO_GetFIFOCount(void)
519 {
520  return SDIO->FIFOCNT;
521 }
522 
530 {
531  /* Check the parameters */
533 
534  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
535 }
536 
544 {
545  /* Check the parameters */
547 
548  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
549 }
550 
559 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
560 {
561  /* Check the parameters */
562  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
563 
564  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
565 }
566 
574 {
575  /* Check the parameters */
577 
578  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
579 }
580 
588 {
589  /* Check the parameters */
591 
592  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
593 }
594 
602 {
603  /* Check the parameters */
605 
606  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
607 }
608 
615 {
616  /* Check the parameters */
618 
619  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
620 }
621 
628 {
629  /* Check the parameters */
631 
632  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
633 }
634 
666 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
667 {
668  FlagStatus bitstatus = RESET;
669 
670  /* Check the parameters */
671  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
672 
673  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
674  {
675  bitstatus = SET;
676  }
677  else
678  {
679  bitstatus = RESET;
680  }
681  return bitstatus;
682 }
683 
704 void SDIO_ClearFlag(uint32_t SDIO_FLAG)
705 {
706  /* Check the parameters */
707  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
708 
709  SDIO->ICR = SDIO_FLAG;
710 }
711 
743 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
744 {
745  ITStatus bitstatus = RESET;
746 
747  /* Check the parameters */
748  assert_param(IS_SDIO_GET_IT(SDIO_IT));
749  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
750  {
751  bitstatus = SET;
752  }
753  else
754  {
755  bitstatus = RESET;
756  }
757  return bitstatus;
758 }
759 
779 void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
780 {
781  /* Check the parameters */
782  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
783 
784  SDIO->ICR = SDIO_IT;
785 }
786 
799 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
#define IS_SDIO_TRANSFER_MODE(MODE)
FlagStatus
Definition: stm32f4xx.h:706
FunctionalState
Definition: stm32f4xx.h:708
#define IS_SDIO_CLEAR_FLAG(FLAG)
#define IS_SDIO_GET_IT(IT)
#define IS_SDIO_CLOCK_EDGE(EDGE)
void SDIO_SendCEATACmd(FunctionalState NewState)
Sends CE-ATA command (CMD61).
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
uint32_t SDIO_ClockPowerSave
#define SDIO_DPSM_Disable
#define IS_SDIO_DATA_LENGTH(LENGTH)
#define IS_SDIO_IT(IT)
#define IS_SDIO_RESP(RESP)
void SDIO_SetSDIOOperation(FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
#define DCTRL_CLEAR_MASK
void assert_param(int val)
void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
#define CLKCR_CLKEN_BB
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
#define SDIO_DataBlockSize_1b
void SDIO_DMACmd(FunctionalState NewState)
Enables or disables the SDIO DMA request.
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
#define IS_SDIO_READWAIT_MODE(MODE)
#define SDIO_TransferDir_ToCard
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
#define IS_SDIO_TRANSFER_DIR(DIR)
#define IS_SDIO_CLEAR_IT(IT)
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
#define SDIO_BusWide_1b
void SDIO_DeInit(void)
Deinitializes the SDIO peripheral registers to their default reset values.
uint32_t SDIO_GetPowerState(void)
Gets the power status of the controller.
#define DCTRL_RWMOD_BB
Definition: stm32f4xx.h:706
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
#define IS_SDIO_CMD_INDEX(INDEX)
void SDIO_StopSDIOReadWait(FunctionalState NewState)
Stops the SD I/O Read Wait operation.
#define SDIO
Definition: stm32f4xx.h:2086
enum FlagStatus ITStatus
#define IS_SDIO_CPSM(CPSM)
#define IS_SDIO_BLOCK_SIZE(SIZE)
#define CLKCR_CLEAR_MASK
#define __IO
Definition: core_cm0.h:198
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE)
void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
#define SDIO_ClockEdge_Rising
#define SDIO_Wait_No
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
Sets the power status of the controller.
uint32_t SDIO_BusWide
#define IS_SDIO_FLAG(FLAG)
#define IS_SDIO_BUS_WIDE(WIDE)
#define SDIO_ClockPowerSave_Disable
This file contains all the functions prototypes for the RCC firmware library.
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send...
uint32_t SDIO_ClockBypass
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
Returns response received from the card for the last command.
uint32_t SDIO_GetFIFOCount(void)
Returns the number of words left to be written to or read from FIFO.
#define IS_SDIO_POWER_STATE(STATE)
void SDIO_CEATAITCmd(FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
void SDIO_CommandCompletionCmd(FunctionalState NewState)
Enables or disables the command completion signal.
#define SDIO_CPSM_Disable
uint32_t SDIO_HardwareFlowControl
#define CMD_NIEN_BB
#define CMD_ENCMDCOMPL_BB
uint8_t SDIO_GetCommandResponse(void)
Returns command index of last command for which response received.
#define DCTRL_DMAEN_BB
This file contains all the functions prototypes for the SDIO firmware library.
#define CMD_CLEAR_MASK
uint32_t SDIO_ClockEdge
#define SDIO_ClockBypass_Disable
#define DCTRL_RWSTART_BB
#define IS_SDIO_RESPONSE(RESPONSE)
#define SDIO_TransferMode_Block
#define CMD_ATACMD_BB
#define IS_SDIO_CLOCK_BYPASS(BYPASS)
void SDIO_ClockCmd(FunctionalState NewState)
Enables or disables the SDIO Clock.
void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
uint32_t SDIO_GetDataCounter(void)
Returns number of remaining data bytes to be transferred.
#define IS_SDIO_DPSM(DPSM)
#define SDIO_HardwareFlowControl_Disable
#define SDIO_Response_No
void SDIO_WriteData(uint32_t Data)
Write one data word to Tx FIFO.
#define IS_SDIO_WAIT(WAIT)
#define SDIO_RESP_ADDR
#define DCTRL_SDIOEN_BB
void SDIO_StartSDIOReadWait(FunctionalState NewState)
Starts the SD I/O Read Wait operation.
#define DCTRL_RWSTOP_BB
uint32_t SDIO_ReadData(void)
Read one data word from Rx FIFO.
#define CMD_SDIOSUSPEND_BB
#define PWR_PWRCTRL_MASK


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19