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00002 #ifndef _TMR_GEN2_H
00003 #define _TMR_GEN2_H
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00033 #ifdef __cplusplus
00034 extern "C" {
00035 #endif
00036
00038 typedef enum TMR_GEN2_LockBits
00039 {
00041 TMR_GEN2_LOCK_BITS_USER_PERM = (1 << 0),
00043 TMR_GEN2_LOCK_BITS_USER = (1 << 1),
00045 TMR_GEN2_LOCK_BITS_TID_PERM = (1 << 2),
00047 TMR_GEN2_LOCK_BITS_TID = (1 << 3),
00049 TMR_GEN2_LOCK_BITS_EPC_PERM = (1 << 4),
00051 TMR_GEN2_LOCK_BITS_EPC = (1 << 5),
00053 TMR_GEN2_LOCK_BITS_ACCESS_PERM = (1 << 6),
00055 TMR_GEN2_LOCK_BITS_ACCESS = (1 << 7),
00057 TMR_GEN2_LOCK_BITS_KILL_PERM = (1 << 8),
00059 TMR_GEN2_LOCK_BITS_KILL = (1 << 9)
00060 } TMR_GEN2_LockBits;
00061
00065 typedef struct TMR_GEN2_LockAction
00066 {
00068 uint16_t mask;
00070 uint16_t action;
00071 }TMR_GEN2_LockAction;
00072
00077 typedef uint32_t TMR_GEN2_Password;
00078
00083 typedef struct TMR_GEN2_DENATRAN_IAV_WriteCredentials
00084 {
00085 uint8_t value[16];
00086 uint8_t tagId[8];
00087 uint8_t credentialLength;
00088 uint8_t tagIdLength;
00089 }TMR_GEN2_DENATRAN_IAV_WriteCredentials;
00090
00095 typedef struct TMR_GEN2_DENATRAN_IAV_WriteSecCredentials
00096 {
00097 uint8_t value[16];
00098 uint8_t data[6];
00099 uint8_t credentialLength;
00100 uint8_t dataLength;
00101 }TMR_GEN2_DENATRAN_IAV_WriteSecCredentials;
00102
00104 typedef enum TMR_GEN2_Bank
00105 {
00107 TMR_GEN2_BANK_RESERVED = 0x0,
00109 TMR_GEN2_BANK_EPC = 0x1,
00111 TMR_GEN2_BANK_TID = 0x2,
00113 TMR_GEN2_BANK_USER = 0x3,
00115 TMR_GEN2_BANK_RESERVED_ENABLED = 0x4,
00117 TMR_GEN2_EPC_LENGTH_FILTER = 0x6,
00119 TMR_GEN2_EPC_TRUNCATE = 0x7,
00121 TMR_GEN2_BANK_EPC_ENABLED = 0x8,
00123 TMR_GEN2_BANK_TID_ENABLED = 0x10,
00125 TMR_GEN2_BANK_USER_ENABLED = 0x20
00126 } TMR_GEN2_Bank;
00127
00132 typedef struct TMR_GEN2_Select
00133 {
00135 bool invert;
00137 TMR_GEN2_Bank bank;
00139 uint32_t bitPointer;
00141 uint16_t maskBitLength;
00143 uint8_t *mask;
00144 } TMR_GEN2_Select;
00145
00147 typedef enum TMR_GEN2_Session
00148 {
00149 TMR_GEN2_SESSION_MIN= 0x00,
00151 TMR_GEN2_SESSION_S0 = 0x00,
00153 TMR_GEN2_SESSION_S1 = 0x01,
00155 TMR_GEN2_SESSION_S2 = 0x02,
00157 TMR_GEN2_SESSION_S3 = 0x03,
00158 TMR_GEN2_SESSION_MAX = TMR_GEN2_SESSION_S3,
00159 TMR_GEN2_SESSION_INVALID = TMR_GEN2_SESSION_MAX + 1
00160 } TMR_GEN2_Session;
00161
00163 typedef enum TMR_GEN2_DivideRatio
00164 {
00166 TMR_GEN2_DIVIDE_RATIO_8 = 0,
00168 TMR_GEN2_DIVIDE_RATIO_64_3 = 1
00169 } TMR_GEN2_DivideRatio;
00170
00172 typedef enum TMR_GEN2_TrExt
00173 {
00175 TMR_GEN2_TR_EXT_NO_PILOT_TONE = 0,
00177 TMR_GEN2_TR_EXT_PILOT_TONE = 1
00178 } TMR_GEN2_TrExt;
00179
00181 typedef enum TMR_GEN2_Target
00182 {
00183 TMR_GEN2_TARGET_MIN= 0,
00185 TMR_GEN2_TARGET_A = 0,
00187 TMR_GEN2_TARGET_B = 1,
00189 TMR_GEN2_TARGET_AB = 2,
00191 TMR_GEN2_TARGET_BA = 3,
00192 TMR_GEN2_TARGET_MAX = TMR_GEN2_TARGET_BA,
00193 TMR_GEN2_TARGET_INVALID = TMR_GEN2_TARGET_MAX+1
00194 }TMR_GEN2_Target;
00195
00197 typedef enum TMR_GEN2_TagEncoding
00198 {
00200 TMR_GEN2_FM0 = 0,
00201
00202 TMR_GEN2_MILLER_MIN = 1,
00204 TMR_GEN2_MILLER_M_2 = 1,
00206 TMR_GEN2_MILLER_M_4 = 2,
00208 TMR_GEN2_MILLER_M_8 = 3,
00209 TMR_GEN2_MILLER_MAX = TMR_GEN2_MILLER_M_8,
00210 TMR_GEN2_MILLER_INVALID = TMR_GEN2_MILLER_MAX+1
00211 }TMR_GEN2_TagEncoding;
00212
00214 typedef enum TMR_GEN2_LinkFrequency
00215 {
00217 TMR_GEN2_LINKFREQUENCY_250KHZ = 250,
00219 TMR_GEN2_LINKFREQUENCY_320KHZ = 320,
00221 TMR_GEN2_LINKFREQUENCY_640KHZ = 640,
00222 TMR_GEN2_LINKFREQUENCY_MAX = 640,
00223 TMR_GEN2_LINKFREQUENCY_INVALID = TMR_GEN2_LINKFREQUENCY_MAX + 1,
00224 } TMR_GEN2_LinkFrequency;
00225
00227 typedef enum TMR_GEN2_ProtocolExtension
00228 {
00229 TMR_GEN2_PROTOCOLEXTENSION_LICENSE_NONE = 0,
00230 TMR_GEN2_PROTOCOLEXTENSION_LICENSE_IAV_DENATRAN = 1
00231 }TMR_GEN2_ProtocolExtension;
00232
00234 typedef struct TMR_GEN2_Bap
00235 {
00236
00237 int32_t powerUpDelayUs;
00238
00239 int32_t freqHopOfftimeUs;
00240 }TMR_GEN2_Bap;
00241
00243 typedef enum TMR_GEN2_UNTRACEABLE_Epc
00244 {
00245
00246 EPC_SHOW = 0,
00247
00248 EPC_HIDE = 1
00249 }TMR_GEN2_UNTRACEABLE_Epc;
00250
00252 typedef enum TMR_GEN2_UNTRACEABLE_Tid
00253 {
00254
00255 HIDE_NONE = 0,
00256
00257 HIDE_ALL = 1,
00258
00259
00260
00261
00262 HIDE_SOME = 2,
00263
00264 TID_RFU = 3
00265 }TMR_GEN2_UNTRACEABLE_Tid;
00266
00268 typedef enum TMR_GEN2_UNTRACEABLE_UserMemory
00269 {
00270
00271 SHOW = 0,
00272
00273 HIDE = 1
00274 }TMR_GEN2_UNTRACEABLE_UserMemory;
00275
00277 typedef enum TMR_GEN2_UNTRACEABLE_Range
00278 {
00279
00280 NORMAL = 0,
00281
00282 REDUCED = 1,
00283
00284 TOGGLE_TEMPORARLY = 2,
00285
00286 RFU = 3
00287 }TMR_GEN2_UNTRACEABLE_Range;
00288
00290 typedef enum TMR_NXP_KeyId
00291 {
00292
00293 KEY0 = 0,
00294
00295 KEY1 = 1
00296 }TMR_NXP_KeyId;
00297
00299 typedef enum TMR_NXP_Profile
00300 {
00301
00302 EPC = 0,
00303
00304 TID = 1,
00305
00306 USER = 2
00307 }TMR_NXP_Profile;
00308
00310 typedef enum TMR_GEN2_Tari
00311 {
00313 TMR_GEN2_TARI_25US = 0,
00315 TMR_GEN2_TARI_12_5US = 1,
00317 TMR_GEN2_TARI_6_25US = 2,
00318 TMR_GEN2_TARI_MAX = 2,
00319 TMR_GEN2_TARI_INVALID = TMR_GEN2_TARI_MAX + 1,
00320 } TMR_GEN2_Tari;
00321
00323 typedef enum TMR_GEN2_WriteMode
00324 {
00326 TMR_GEN2_WORD_ONLY = 0,
00328 TMR_GEN2_BLOCK_ONLY = 1,
00330 TMR_GEN2_BLOCK_FALLBACK = 2,
00331
00332 } TMR_GEN2_WriteMode;
00333
00337 typedef enum TMR_SR_GEN2_SiliconType
00338 {
00339 TMR_SR_GEN2_SILICON_ANY = 0x00,
00340 TMR_SR_GEN2_ALIEN_HIGGS_SILICON = 0x01,
00341 TMR_SR_GEN2_NXP_G2X_SILICON = 0x02,
00342 TMR_SR_GEN2_ALIEN_HIGGS3_SILICON = 0x05,
00343 TMR_SR_GEN2_NXP_G2I_SILICON = 0x07,
00344 TMR_SR_GEN2_IMPINJ_MONZA4_SILICON = 0x08,
00345 TMR_SR_GEN2_IDS_SL900A_SILICON = 0x0A,
00346 TMR_SR_GEN2_DENATRAN_IAV_SILICON = 0x0B,
00347 TMR_SR_GEN2_NXP_AES_UCODE = 0x0C,
00348 }TMR_SR_GEN2_SiliconType;
00349
00358 typedef union TMR_NXP_ConfigWord
00359 {
00360 uint16_t data;
00361
00362
00363
00364
00365 struct
00366 {
00369 unsigned psfAlarm:1;
00371 unsigned readProtectTID:1;
00373 unsigned readProtectEPC:1;
00375 unsigned readProtectUser:1;
00377 unsigned privacyMode:1;
00379 unsigned digitalOutput:1;
00381 unsigned maxBackscatterStrength:1;
00383 unsigned conditionalReadRangeReduction_openShort:1;
00385 unsigned conditionalReadRangeReduction_onOff:1;
00387 unsigned dataMode:1;
00389 unsigned transparentMode:1;
00391 unsigned invertDigitalOutput:1;
00393 unsigned RFU3:1;
00395 unsigned RFU2:1;
00397 unsigned externalSupply:1;
00399 unsigned tamperAlarm:1;
00401 }bits;
00402 }TMR_NXP_ConfigWord;
00403
00412 typedef union TMR_Monza4_ControlByte
00413 {
00414
00415 uint8_t data;
00416
00417
00418
00419
00420 struct
00421 {
00427 unsigned RFU_TM0:1;
00428 unsigned RFU_TM1:1;
00429 unsigned RFU_TM2:1;
00430 unsigned RFU_TM3:1;
00431 unsigned RFU_Impinj4:1;
00432 unsigned RFU_Impinj5:1;
00439 unsigned persistence:1;
00445 unsigned readWrite:1;
00446 }bits;
00447 }TMR_Monza4_ControlByte;
00448
00459 typedef union TMR_Monza4_Payload
00460 {
00462 uint16_t data;
00463
00464
00465
00466
00467 struct
00468 {
00474 unsigned RFU0:1;
00475 unsigned RFU1:1;
00476 unsigned RFU2:1;
00477 unsigned RFU3:1;
00478 unsigned RFU4:1;
00479 unsigned RFU5:1;
00480 unsigned RFU6:1;
00481 unsigned RFU7:1;
00482 unsigned RFU8:1;
00483 unsigned RFU9:1;
00484 unsigned RFU10:1;
00485 unsigned RFU11:1;
00486 unsigned RFU12:1;
00487 unsigned RFU13:1;
00493 unsigned QT_MEM:1;
00500 unsigned QT_SR:1;
00501 }bits;
00502 }TMR_Monza4_Payload;
00503
00504 typedef struct TMR_GEN2_HibikiSystemInformation
00505 {
00506 uint16_t infoFlags;
00507 uint8_t reservedMemory;
00508 uint8_t epcMemory;
00509 uint8_t tidMemory;
00510 uint8_t userMemory;
00511 uint8_t setAttenuate;
00512 uint16_t bankLock;
00513 uint16_t blockReadLock;
00514 uint16_t blockRwLock;
00515 uint16_t blockWriteLock;
00516 } TMR_GEN2_HibikiSystemInformation;
00517
00519 #define TMR_GEN2_MAX_PC_BYTE_COUNT (6)
00520
00523 typedef struct TMR_GEN2_TagData
00524 {
00526 uint8_t pcByteCount;
00528 uint8_t pc[TMR_GEN2_MAX_PC_BYTE_COUNT];
00529 } TMR_GEN2_TagData;
00530
00531
00532
00533 #ifdef __cplusplus
00534 }
00535 #endif
00536
00537 #endif