initvals.c
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00001 /*------------------------------------------------------------------------------
00002  *-------------------------        ATH5K Driver          -----------------------
00003  *------------------------------------------------------------------------------
00004  *                                                           V1.0  08/02/2010
00005  *
00006  *
00007  *  Feb 2010 - Samuel Cabrero <samuelcabrero@gmail.com>
00008  *              Initial release
00009  *
00010  *  ----------------------------------------------------------------------------
00011  *  Copyright (C) 2000-2010, Universidad de Zaragoza, SPAIN
00012  *
00013  *  Autors:
00014  *              Samuel Cabrero        <samuelcabrero@gmail.com>
00015  *              Danilo Tardioli       <dantard@unizar.es>
00016  *              Jose Luis Villarroel  <jlvilla@unizar.es>
00017  *
00018  *  This is a simplified version of the original ath5k driver. It should work 
00019  *  with all Atheros 5xxx WLAN cards. The 802.11 layer have been removed so it
00020  *  just send and receive frames over the air, as if it were an Ethernet bus
00021  *  interface.
00022  *
00023  *  Please read ath5k_interface.h for instructions.
00024  *
00025  *  This program is distributed under the terms of GPL version 2 and in the 
00026  *  hope that it will be useful, but WITHOUT ANY WARRANTY; without even the 
00027  *  implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
00028  *  See the GNU General Public License for more details.
00029  *
00030  *----------------------------------------------------------------------------*/
00031 
00032 /*
00033  * Initial register settings functions
00034  *
00035  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
00036  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
00037  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
00038  *
00039  * Permission to use, copy, modify, and distribute this software for any
00040  * purpose with or without fee is hereby granted, provided that the above
00041  * copyright notice and this permission notice appear in all copies.
00042  *
00043  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00044  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00045  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00046  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00047  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00048  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00049  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00050  *
00051  */
00052 
00053 #include "ath5k.h"
00054 #include "reg.h"
00055 #include "debug.h"
00056 #include "base.h"
00057 
00058 /*
00059  * Mode-independent initial register writes
00060  */
00061 
00062 struct ath5k_ini {
00063         u16     ini_register;
00064         u32     ini_value;
00065 
00066         enum {
00067                 AR5K_INI_WRITE = 0,     /* Default */
00068                 AR5K_INI_READ = 1,      /* Cleared on read */
00069         } ini_mode;
00070 };
00071 
00072 /*
00073  * Mode specific initial register values
00074  */
00075 
00076 struct ath5k_ini_mode {
00077         u16     mode_register;
00078         u32     mode_value[5];
00079 };
00080 
00081 /* Initial register settings for AR5210 */
00082 static const struct ath5k_ini ar5210_ini[] = {
00083         /* PCU and MAC registers */
00084         { AR5K_NOQCU_TXDP0,     0 },
00085         { AR5K_NOQCU_TXDP1,     0 },
00086         { AR5K_RXDP,            0 },
00087         { AR5K_CR,              0 },
00088         { AR5K_ISR,             0, AR5K_INI_READ },
00089         { AR5K_IMR,             0 },
00090         { AR5K_IER,             AR5K_IER_DISABLE },
00091         { AR5K_BSR,             0, AR5K_INI_READ },
00092         { AR5K_TXCFG,           AR5K_DMASIZE_128B },
00093         { AR5K_RXCFG,           AR5K_DMASIZE_128B },
00094         { AR5K_CFG,             AR5K_INIT_CFG },
00095         { AR5K_TOPS,            8 },
00096         { AR5K_RXNOFRM,         8 },
00097         { AR5K_RPGTO,           0 },
00098         { AR5K_TXNOFRM,         0 },
00099         { AR5K_SFR,             0 },
00100         { AR5K_MIBC,            0 },
00101         { AR5K_MISC,            0 },
00102         { AR5K_RX_FILTER_5210,  0 },
00103         { AR5K_MCAST_FILTER0_5210, 0 },
00104         { AR5K_MCAST_FILTER1_5210, 0 },
00105         { AR5K_TX_MASK0,        0 },
00106         { AR5K_TX_MASK1,        0 },
00107         { AR5K_CLR_TMASK,       0 },
00108         { AR5K_TRIG_LVL,        AR5K_TUNE_MIN_TX_FIFO_THRES },
00109         { AR5K_DIAG_SW_5210,    0 },
00110         { AR5K_RSSI_THR,        AR5K_TUNE_RSSI_THRES },
00111         { AR5K_TSF_L32_5210,    0 },
00112         { AR5K_TIMER0_5210,     0 },
00113         { AR5K_TIMER1_5210,     0xffffffff },
00114         { AR5K_TIMER2_5210,     0xffffffff },
00115         { AR5K_TIMER3_5210,     1 },
00116         { AR5K_CFP_DUR_5210,    0 },
00117         { AR5K_CFP_PERIOD_5210, 0 },
00118         /* PHY registers */
00119         { AR5K_PHY(0),  0x00000047 },
00120         { AR5K_PHY_AGC, 0x00000000 },
00121         { AR5K_PHY(3),  0x09848ea6 },
00122         { AR5K_PHY(4),  0x3d32e000 },
00123         { AR5K_PHY(5),  0x0000076b },
00124         { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE },
00125         { AR5K_PHY(8),  0x02020200 },
00126         { AR5K_PHY(9),  0x00000e0e },
00127         { AR5K_PHY(10), 0x0a020201 },
00128         { AR5K_PHY(11), 0x00036ffc },
00129         { AR5K_PHY(12), 0x00000000 },
00130         { AR5K_PHY(13), 0x00000e0e },
00131         { AR5K_PHY(14), 0x00000007 },
00132         { AR5K_PHY(15), 0x00020100 },
00133         { AR5K_PHY(16), 0x89630000 },
00134         { AR5K_PHY(17), 0x1372169c },
00135         { AR5K_PHY(18), 0x0018b633 },
00136         { AR5K_PHY(19), 0x1284613c },
00137         { AR5K_PHY(20), 0x0de8b8e0 },
00138         { AR5K_PHY(21), 0x00074859 },
00139         { AR5K_PHY(22), 0x7e80beba },
00140         { AR5K_PHY(23), 0x313a665e },
00141         { AR5K_PHY_AGCCTL, 0x00001d08 },
00142         { AR5K_PHY(25), 0x0001ce00 },
00143         { AR5K_PHY(26), 0x409a4190 },
00144         { AR5K_PHY(28), 0x0000000f },
00145         { AR5K_PHY(29), 0x00000080 },
00146         { AR5K_PHY(30), 0x00000004 },
00147         { AR5K_PHY(31), 0x00000018 },   /* 0x987c */
00148         { AR5K_PHY(64), 0x00000000 },   /* 0x9900 */
00149         { AR5K_PHY(65), 0x00000000 },
00150         { AR5K_PHY(66), 0x00000000 },
00151         { AR5K_PHY(67), 0x00800000 },
00152         { AR5K_PHY(68), 0x00000003 },
00153         /* BB gain table (64bytes) */
00154         { AR5K_BB_GAIN(0), 0x00000000 },
00155         { AR5K_BB_GAIN(1), 0x00000020 },
00156         { AR5K_BB_GAIN(2), 0x00000010 },
00157         { AR5K_BB_GAIN(3), 0x00000030 },
00158         { AR5K_BB_GAIN(4), 0x00000008 },
00159         { AR5K_BB_GAIN(5), 0x00000028 },
00160         { AR5K_BB_GAIN(6), 0x00000028 },
00161         { AR5K_BB_GAIN(7), 0x00000004 },
00162         { AR5K_BB_GAIN(8), 0x00000024 },
00163         { AR5K_BB_GAIN(9), 0x00000014 },
00164         { AR5K_BB_GAIN(10), 0x00000034 },
00165         { AR5K_BB_GAIN(11), 0x0000000c },
00166         { AR5K_BB_GAIN(12), 0x0000002c },
00167         { AR5K_BB_GAIN(13), 0x00000002 },
00168         { AR5K_BB_GAIN(14), 0x00000022 },
00169         { AR5K_BB_GAIN(15), 0x00000012 },
00170         { AR5K_BB_GAIN(16), 0x00000032 },
00171         { AR5K_BB_GAIN(17), 0x0000000a },
00172         { AR5K_BB_GAIN(18), 0x0000002a },
00173         { AR5K_BB_GAIN(19), 0x00000001 },
00174         { AR5K_BB_GAIN(20), 0x00000021 },
00175         { AR5K_BB_GAIN(21), 0x00000011 },
00176         { AR5K_BB_GAIN(22), 0x00000031 },
00177         { AR5K_BB_GAIN(23), 0x00000009 },
00178         { AR5K_BB_GAIN(24), 0x00000029 },
00179         { AR5K_BB_GAIN(25), 0x00000005 },
00180         { AR5K_BB_GAIN(26), 0x00000025 },
00181         { AR5K_BB_GAIN(27), 0x00000015 },
00182         { AR5K_BB_GAIN(28), 0x00000035 },
00183         { AR5K_BB_GAIN(29), 0x0000000d },
00184         { AR5K_BB_GAIN(30), 0x0000002d },
00185         { AR5K_BB_GAIN(31), 0x00000003 },
00186         { AR5K_BB_GAIN(32), 0x00000023 },
00187         { AR5K_BB_GAIN(33), 0x00000013 },
00188         { AR5K_BB_GAIN(34), 0x00000033 },
00189         { AR5K_BB_GAIN(35), 0x0000000b },
00190         { AR5K_BB_GAIN(36), 0x0000002b },
00191         { AR5K_BB_GAIN(37), 0x00000007 },
00192         { AR5K_BB_GAIN(38), 0x00000027 },
00193         { AR5K_BB_GAIN(39), 0x00000017 },
00194         { AR5K_BB_GAIN(40), 0x00000037 },
00195         { AR5K_BB_GAIN(41), 0x0000000f },
00196         { AR5K_BB_GAIN(42), 0x0000002f },
00197         { AR5K_BB_GAIN(43), 0x0000002f },
00198         { AR5K_BB_GAIN(44), 0x0000002f },
00199         { AR5K_BB_GAIN(45), 0x0000002f },
00200         { AR5K_BB_GAIN(46), 0x0000002f },
00201         { AR5K_BB_GAIN(47), 0x0000002f },
00202         { AR5K_BB_GAIN(48), 0x0000002f },
00203         { AR5K_BB_GAIN(49), 0x0000002f },
00204         { AR5K_BB_GAIN(50), 0x0000002f },
00205         { AR5K_BB_GAIN(51), 0x0000002f },
00206         { AR5K_BB_GAIN(52), 0x0000002f },
00207         { AR5K_BB_GAIN(53), 0x0000002f },
00208         { AR5K_BB_GAIN(54), 0x0000002f },
00209         { AR5K_BB_GAIN(55), 0x0000002f },
00210         { AR5K_BB_GAIN(56), 0x0000002f },
00211         { AR5K_BB_GAIN(57), 0x0000002f },
00212         { AR5K_BB_GAIN(58), 0x0000002f },
00213         { AR5K_BB_GAIN(59), 0x0000002f },
00214         { AR5K_BB_GAIN(60), 0x0000002f },
00215         { AR5K_BB_GAIN(61), 0x0000002f },
00216         { AR5K_BB_GAIN(62), 0x0000002f },
00217         { AR5K_BB_GAIN(63), 0x0000002f },
00218         /* 5110 RF gain table (64btes) */
00219         { AR5K_RF_GAIN(0), 0x0000001d },
00220         { AR5K_RF_GAIN(1), 0x0000005d },
00221         { AR5K_RF_GAIN(2), 0x0000009d },
00222         { AR5K_RF_GAIN(3), 0x000000dd },
00223         { AR5K_RF_GAIN(4), 0x0000011d },
00224         { AR5K_RF_GAIN(5), 0x00000021 },
00225         { AR5K_RF_GAIN(6), 0x00000061 },
00226         { AR5K_RF_GAIN(7), 0x000000a1 },
00227         { AR5K_RF_GAIN(8), 0x000000e1 },
00228         { AR5K_RF_GAIN(9), 0x00000031 },
00229         { AR5K_RF_GAIN(10), 0x00000071 },
00230         { AR5K_RF_GAIN(11), 0x000000b1 },
00231         { AR5K_RF_GAIN(12), 0x0000001c },
00232         { AR5K_RF_GAIN(13), 0x0000005c },
00233         { AR5K_RF_GAIN(14), 0x00000029 },
00234         { AR5K_RF_GAIN(15), 0x00000069 },
00235         { AR5K_RF_GAIN(16), 0x000000a9 },
00236         { AR5K_RF_GAIN(17), 0x00000020 },
00237         { AR5K_RF_GAIN(18), 0x00000019 },
00238         { AR5K_RF_GAIN(19), 0x00000059 },
00239         { AR5K_RF_GAIN(20), 0x00000099 },
00240         { AR5K_RF_GAIN(21), 0x00000030 },
00241         { AR5K_RF_GAIN(22), 0x00000005 },
00242         { AR5K_RF_GAIN(23), 0x00000025 },
00243         { AR5K_RF_GAIN(24), 0x00000065 },
00244         { AR5K_RF_GAIN(25), 0x000000a5 },
00245         { AR5K_RF_GAIN(26), 0x00000028 },
00246         { AR5K_RF_GAIN(27), 0x00000068 },
00247         { AR5K_RF_GAIN(28), 0x0000001f },
00248         { AR5K_RF_GAIN(29), 0x0000001e },
00249         { AR5K_RF_GAIN(30), 0x00000018 },
00250         { AR5K_RF_GAIN(31), 0x00000058 },
00251         { AR5K_RF_GAIN(32), 0x00000098 },
00252         { AR5K_RF_GAIN(33), 0x00000003 },
00253         { AR5K_RF_GAIN(34), 0x00000004 },
00254         { AR5K_RF_GAIN(35), 0x00000044 },
00255         { AR5K_RF_GAIN(36), 0x00000084 },
00256         { AR5K_RF_GAIN(37), 0x00000013 },
00257         { AR5K_RF_GAIN(38), 0x00000012 },
00258         { AR5K_RF_GAIN(39), 0x00000052 },
00259         { AR5K_RF_GAIN(40), 0x00000092 },
00260         { AR5K_RF_GAIN(41), 0x000000d2 },
00261         { AR5K_RF_GAIN(42), 0x0000002b },
00262         { AR5K_RF_GAIN(43), 0x0000002a },
00263         { AR5K_RF_GAIN(44), 0x0000006a },
00264         { AR5K_RF_GAIN(45), 0x000000aa },
00265         { AR5K_RF_GAIN(46), 0x0000001b },
00266         { AR5K_RF_GAIN(47), 0x0000001a },
00267         { AR5K_RF_GAIN(48), 0x0000005a },
00268         { AR5K_RF_GAIN(49), 0x0000009a },
00269         { AR5K_RF_GAIN(50), 0x000000da },
00270         { AR5K_RF_GAIN(51), 0x00000006 },
00271         { AR5K_RF_GAIN(52), 0x00000006 },
00272         { AR5K_RF_GAIN(53), 0x00000006 },
00273         { AR5K_RF_GAIN(54), 0x00000006 },
00274         { AR5K_RF_GAIN(55), 0x00000006 },
00275         { AR5K_RF_GAIN(56), 0x00000006 },
00276         { AR5K_RF_GAIN(57), 0x00000006 },
00277         { AR5K_RF_GAIN(58), 0x00000006 },
00278         { AR5K_RF_GAIN(59), 0x00000006 },
00279         { AR5K_RF_GAIN(60), 0x00000006 },
00280         { AR5K_RF_GAIN(61), 0x00000006 },
00281         { AR5K_RF_GAIN(62), 0x00000006 },
00282         { AR5K_RF_GAIN(63), 0x00000006 },
00283         /* PHY activation */
00284         { AR5K_PHY(53), 0x00000020 },
00285         { AR5K_PHY(51), 0x00000004 },
00286         { AR5K_PHY(50), 0x00060106 },
00287         { AR5K_PHY(39), 0x0000006d },
00288         { AR5K_PHY(48), 0x00000000 },
00289         { AR5K_PHY(52), 0x00000014 },
00290         { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE },
00291 };
00292 
00293 /* Initial register settings for AR5211 */
00294 static const struct ath5k_ini ar5211_ini[] = {
00295         { AR5K_RXDP,            0x00000000 },
00296         { AR5K_RTSD0,           0x84849c9c },
00297         { AR5K_RTSD1,           0x7c7c7c7c },
00298         { AR5K_RXCFG,           0x00000005 },
00299         { AR5K_MIBC,            0x00000000 },
00300         { AR5K_TOPS,            0x00000008 },
00301         { AR5K_RXNOFRM,         0x00000008 },
00302         { AR5K_TXNOFRM,         0x00000010 },
00303         { AR5K_RPGTO,           0x00000000 },
00304         { AR5K_RFCNT,           0x0000001f },
00305         { AR5K_QUEUE_TXDP(0),   0x00000000 },
00306         { AR5K_QUEUE_TXDP(1),   0x00000000 },
00307         { AR5K_QUEUE_TXDP(2),   0x00000000 },
00308         { AR5K_QUEUE_TXDP(3),   0x00000000 },
00309         { AR5K_QUEUE_TXDP(4),   0x00000000 },
00310         { AR5K_QUEUE_TXDP(5),   0x00000000 },
00311         { AR5K_QUEUE_TXDP(6),   0x00000000 },
00312         { AR5K_QUEUE_TXDP(7),   0x00000000 },
00313         { AR5K_QUEUE_TXDP(8),   0x00000000 },
00314         { AR5K_QUEUE_TXDP(9),   0x00000000 },
00315         { AR5K_DCU_FP,          0x00000000 },
00316         { AR5K_STA_ID1,         0x00000000 },
00317         { AR5K_BSS_ID0,         0x00000000 },
00318         { AR5K_BSS_ID1,         0x00000000 },
00319         { AR5K_RSSI_THR,        0x00000000 },
00320         { AR5K_CFP_PERIOD_5211, 0x00000000 },
00321         { AR5K_TIMER0_5211,     0x00000030 },
00322         { AR5K_TIMER1_5211,     0x0007ffff },
00323         { AR5K_TIMER2_5211,     0x01ffffff },
00324         { AR5K_TIMER3_5211,     0x00000031 },
00325         { AR5K_CFP_DUR_5211,    0x00000000 },
00326         { AR5K_RX_FILTER_5211,  0x00000000 },
00327         { AR5K_MCAST_FILTER0_5211, 0x00000000 },
00328         { AR5K_MCAST_FILTER1_5211, 0x00000002 },
00329         { AR5K_DIAG_SW_5211,    0x00000000 },
00330         { AR5K_ADDAC_TEST,      0x00000000 },
00331         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
00332         /* PHY registers */
00333         { AR5K_PHY_AGC, 0x00000000 },
00334         { AR5K_PHY(3),  0x2d849093 },
00335         { AR5K_PHY(4),  0x7d32e000 },
00336         { AR5K_PHY(5),  0x00000f6b },
00337         { AR5K_PHY_ACT, 0x00000000 },
00338         { AR5K_PHY(11), 0x00026ffe },
00339         { AR5K_PHY(12), 0x00000000 },
00340         { AR5K_PHY(15), 0x00020100 },
00341         { AR5K_PHY(16), 0x206a017a },
00342         { AR5K_PHY(19), 0x1284613c },
00343         { AR5K_PHY(21), 0x00000859 },
00344         { AR5K_PHY(26), 0x409a4190 },   /* 0x9868 */
00345         { AR5K_PHY(27), 0x050cb081 },
00346         { AR5K_PHY(28), 0x0000000f },
00347         { AR5K_PHY(29), 0x00000080 },
00348         { AR5K_PHY(30), 0x0000000c },
00349         { AR5K_PHY(64), 0x00000000 },
00350         { AR5K_PHY(65), 0x00000000 },
00351         { AR5K_PHY(66), 0x00000000 },
00352         { AR5K_PHY(67), 0x00800000 },
00353         { AR5K_PHY(68), 0x00000001 },
00354         { AR5K_PHY(71), 0x0000092a },
00355         { AR5K_PHY_IQ,  0x00000000 },
00356         { AR5K_PHY(73), 0x00058a05 },
00357         { AR5K_PHY(74), 0x00000001 },
00358         { AR5K_PHY(75), 0x00000000 },
00359         { AR5K_PHY_PAPD_PROBE, 0x00000000 },
00360         { AR5K_PHY(77), 0x00000000 },   /* 0x9934 */
00361         { AR5K_PHY(78), 0x00000000 },   /* 0x9938 */
00362         { AR5K_PHY(79), 0x0000003f },   /* 0x993c */
00363         { AR5K_PHY(80), 0x00000004 },
00364         { AR5K_PHY(82), 0x00000000 },
00365         { AR5K_PHY(83), 0x00000000 },
00366         { AR5K_PHY(84), 0x00000000 },
00367         { AR5K_PHY_RADAR, 0x5d50f14c },
00368         { AR5K_PHY(86), 0x00000018 },
00369         { AR5K_PHY(87), 0x004b6a8e },
00370         /* Initial Power table (32bytes)
00371          * common on all cards/modes.
00372          * Note: Table is rewritten during
00373          * txpower setup later using calibration
00374          * data etc. so next write is non-common */
00375         { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },
00376         { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },
00377         { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },
00378         { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff },
00379         { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff },
00380         { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff },
00381         { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff },
00382         { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff },
00383         { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff },
00384         { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff },
00385         { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff },
00386         { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff },
00387         { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff },
00388         { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff },
00389         { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff },
00390         { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff },
00391         { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff },
00392         { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff },
00393         { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff },
00394         { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff },
00395         { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff },
00396         { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff },
00397         { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff },
00398         { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff },
00399         { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff },
00400         { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff },
00401         { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff },
00402         { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },
00403         { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },
00404         { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },
00405         { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },
00406         { AR5K_PHY_CCKTXCTL, 0x00000000 },
00407         { AR5K_PHY(642), 0x503e4646 },
00408         { AR5K_PHY_GAIN_2GHZ, 0x6480416c },
00409         { AR5K_PHY(644), 0x0199a003 },
00410         { AR5K_PHY(645), 0x044cd610 },
00411         { AR5K_PHY(646), 0x13800040 },
00412         { AR5K_PHY(647), 0x1be00060 },
00413         { AR5K_PHY(648), 0x0c53800a },
00414         { AR5K_PHY(649), 0x0014df3b },
00415         { AR5K_PHY(650), 0x000001b5 },
00416         { AR5K_PHY(651), 0x00000020 },
00417 };
00418 
00419 /* Initial mode-specific settings for AR5211
00420  * 5211 supports OFDM-only g (draft g) but we
00421  * need to test it !
00422  */
00423 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
00424         { AR5K_TXCFG,
00425         /*        a         aTurbo        b       g (OFDM)    */
00426            { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
00427         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
00428            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00429         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
00430            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00431         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
00432            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00433         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
00434            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00435         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
00436            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00437         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
00438            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00439         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
00440            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00441         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
00442            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00443         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
00444            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00445         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
00446            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00447         { AR5K_DCU_GBL_IFS_SLOT,
00448            { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
00449         { AR5K_DCU_GBL_IFS_SIFS,
00450            { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
00451         { AR5K_DCU_GBL_IFS_EIFS,
00452            { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
00453         { AR5K_DCU_GBL_IFS_MISC,
00454            { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
00455         { AR5K_TIME_OUT,
00456            { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
00457         { AR5K_USEC_5211,
00458            { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
00459         { AR5K_PHY_TURBO,
00460            { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
00461         { AR5K_PHY(8),
00462            { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
00463         { AR5K_PHY(9),
00464            { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
00465         { AR5K_PHY(10),
00466            { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
00467         { AR5K_PHY(13),
00468            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00469         { AR5K_PHY(14),
00470            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
00471         { AR5K_PHY(17),
00472            { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
00473         { AR5K_PHY(18),
00474            { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
00475         { AR5K_PHY(20),
00476            { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
00477         { AR5K_PHY_SIG,
00478            { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
00479         { AR5K_PHY_AGCCOARSE,
00480            { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
00481         { AR5K_PHY_AGCCTL,
00482            { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
00483         { AR5K_PHY_NF,
00484            { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
00485         { AR5K_PHY_RX_DELAY,
00486            { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
00487         { AR5K_PHY(70),
00488            { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
00489         { AR5K_PHY_FRAME_CTL_5211,
00490            { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
00491         { AR5K_PHY_PCDAC_TXPOWER_BASE,
00492            { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
00493         { AR5K_RF_BUFFER_CONTROL_4,
00494            { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
00495 };
00496 
00497 /* Initial register settings for AR5212 */
00498 static const struct ath5k_ini ar5212_ini_common_start[] = {
00499         { AR5K_RXDP,            0x00000000 },
00500         { AR5K_RXCFG,           0x00000005 },
00501         { AR5K_MIBC,            0x00000000 },
00502         { AR5K_TOPS,            0x00000008 },
00503         { AR5K_RXNOFRM,         0x00000008 },
00504         { AR5K_TXNOFRM,         0x00000010 },
00505         { AR5K_RPGTO,           0x00000000 },
00506         { AR5K_RFCNT,           0x0000001f },
00507         { AR5K_QUEUE_TXDP(0),   0x00000000 },
00508         { AR5K_QUEUE_TXDP(1),   0x00000000 },
00509         { AR5K_QUEUE_TXDP(2),   0x00000000 },
00510         { AR5K_QUEUE_TXDP(3),   0x00000000 },
00511         { AR5K_QUEUE_TXDP(4),   0x00000000 },
00512         { AR5K_QUEUE_TXDP(5),   0x00000000 },
00513         { AR5K_QUEUE_TXDP(6),   0x00000000 },
00514         { AR5K_QUEUE_TXDP(7),   0x00000000 },
00515         { AR5K_QUEUE_TXDP(8),   0x00000000 },
00516         { AR5K_QUEUE_TXDP(9),   0x00000000 },
00517         { AR5K_DCU_FP,          0x00000000 },
00518         { AR5K_DCU_TXP,         0x00000000 },
00519         /* Tx filter table 0 (32 entries) */
00520         { AR5K_DCU_TX_FILTER_0(0),  0x00000000 }, /* DCU 0 */
00521         { AR5K_DCU_TX_FILTER_0(1),  0x00000000 },
00522         { AR5K_DCU_TX_FILTER_0(2),  0x00000000 },
00523         { AR5K_DCU_TX_FILTER_0(3),  0x00000000 },
00524         { AR5K_DCU_TX_FILTER_0(4),  0x00000000 }, /* DCU 1 */
00525         { AR5K_DCU_TX_FILTER_0(5),  0x00000000 },
00526         { AR5K_DCU_TX_FILTER_0(6),  0x00000000 },
00527         { AR5K_DCU_TX_FILTER_0(7),  0x00000000 },
00528         { AR5K_DCU_TX_FILTER_0(8),  0x00000000 }, /* DCU 2 */
00529         { AR5K_DCU_TX_FILTER_0(9),  0x00000000 },
00530         { AR5K_DCU_TX_FILTER_0(10), 0x00000000 },
00531         { AR5K_DCU_TX_FILTER_0(11), 0x00000000 },
00532         { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */
00533         { AR5K_DCU_TX_FILTER_0(13), 0x00000000 },
00534         { AR5K_DCU_TX_FILTER_0(14), 0x00000000 },
00535         { AR5K_DCU_TX_FILTER_0(15), 0x00000000 },
00536         { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */
00537         { AR5K_DCU_TX_FILTER_0(17), 0x00000000 },
00538         { AR5K_DCU_TX_FILTER_0(18), 0x00000000 },
00539         { AR5K_DCU_TX_FILTER_0(19), 0x00000000 },
00540         { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */
00541         { AR5K_DCU_TX_FILTER_0(21), 0x00000000 },
00542         { AR5K_DCU_TX_FILTER_0(22), 0x00000000 },
00543         { AR5K_DCU_TX_FILTER_0(23), 0x00000000 },
00544         { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */
00545         { AR5K_DCU_TX_FILTER_0(25), 0x00000000 },
00546         { AR5K_DCU_TX_FILTER_0(26), 0x00000000 },
00547         { AR5K_DCU_TX_FILTER_0(27), 0x00000000 },
00548         { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */
00549         { AR5K_DCU_TX_FILTER_0(29), 0x00000000 },
00550         { AR5K_DCU_TX_FILTER_0(30), 0x00000000 },
00551         { AR5K_DCU_TX_FILTER_0(31), 0x00000000 },
00552         /* Tx filter table 1 (16 entries) */
00553         { AR5K_DCU_TX_FILTER_1(0),  0x00000000 },
00554         { AR5K_DCU_TX_FILTER_1(1),  0x00000000 },
00555         { AR5K_DCU_TX_FILTER_1(2),  0x00000000 },
00556         { AR5K_DCU_TX_FILTER_1(3),  0x00000000 },
00557         { AR5K_DCU_TX_FILTER_1(4),  0x00000000 },
00558         { AR5K_DCU_TX_FILTER_1(5),  0x00000000 },
00559         { AR5K_DCU_TX_FILTER_1(6),  0x00000000 },
00560         { AR5K_DCU_TX_FILTER_1(7),  0x00000000 },
00561         { AR5K_DCU_TX_FILTER_1(8),  0x00000000 },
00562         { AR5K_DCU_TX_FILTER_1(9),  0x00000000 },
00563         { AR5K_DCU_TX_FILTER_1(10), 0x00000000 },
00564         { AR5K_DCU_TX_FILTER_1(11), 0x00000000 },
00565         { AR5K_DCU_TX_FILTER_1(12), 0x00000000 },
00566         { AR5K_DCU_TX_FILTER_1(13), 0x00000000 },
00567         { AR5K_DCU_TX_FILTER_1(14), 0x00000000 },
00568         { AR5K_DCU_TX_FILTER_1(15), 0x00000000 },
00569         { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
00570         { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
00571         { AR5K_STA_ID1,         0x00000000 },
00572         { AR5K_BSS_ID0,         0x00000000 },
00573         { AR5K_BSS_ID1,         0x00000000 },
00574         { AR5K_BEACON_5211,     0x00000000 },
00575         { AR5K_CFP_PERIOD_5211, 0x00000000 },
00576         { AR5K_TIMER0_5211,     0x00000030 },
00577         { AR5K_TIMER1_5211,     0x0007ffff },
00578         { AR5K_TIMER2_5211,     0x01ffffff },
00579         { AR5K_TIMER3_5211,     0x00000031 },
00580         { AR5K_CFP_DUR_5211,    0x00000000 },
00581         { AR5K_RX_FILTER_5211,  0x00000000 },
00582         { AR5K_DIAG_SW_5211,    0x00000000 },
00583         { AR5K_ADDAC_TEST,      0x00000000 },
00584         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
00585         { AR5K_FRAME_CTL_QOSM,  0x000fc78f },
00586         { AR5K_XRMODE,          0x2a82301a },
00587         { AR5K_XRDELAY,         0x05dc01e0 },
00588         { AR5K_XRTIMEOUT,       0x1f402710 },
00589         { AR5K_XRCHIRP,         0x01f40000 },
00590         { AR5K_XRSTOMP,         0x00001e1c },
00591         { AR5K_SLEEP0,          0x0002aaaa },
00592         { AR5K_SLEEP1,          0x02005555 },
00593         { AR5K_SLEEP2,          0x00000000 },
00594         { AR5K_BSS_IDM0,        0xffffffff },
00595         { AR5K_BSS_IDM1,        0x0000ffff },
00596         { AR5K_TXPC,            0x00000000 },
00597         { AR5K_PROFCNT_TX,      0x00000000 },
00598         { AR5K_PROFCNT_RX,      0x00000000 },
00599         { AR5K_PROFCNT_RXCLR,   0x00000000 },
00600         { AR5K_PROFCNT_CYCLE,   0x00000000 },
00601         { AR5K_QUIET_CTL1,      0x00000088 },
00602         /* Initial rate duration table (32 entries )*/
00603         { AR5K_RATE_DUR(0),     0x00000000 },
00604         { AR5K_RATE_DUR(1),     0x0000008c },
00605         { AR5K_RATE_DUR(2),     0x000000e4 },
00606         { AR5K_RATE_DUR(3),     0x000002d5 },
00607         { AR5K_RATE_DUR(4),     0x00000000 },
00608         { AR5K_RATE_DUR(5),     0x00000000 },
00609         { AR5K_RATE_DUR(6),     0x000000a0 },
00610         { AR5K_RATE_DUR(7),     0x000001c9 },
00611         { AR5K_RATE_DUR(8),     0x0000002c },
00612         { AR5K_RATE_DUR(9),     0x0000002c },
00613         { AR5K_RATE_DUR(10),    0x00000030 },
00614         { AR5K_RATE_DUR(11),    0x0000003c },
00615         { AR5K_RATE_DUR(12),    0x0000002c },
00616         { AR5K_RATE_DUR(13),    0x0000002c },
00617         { AR5K_RATE_DUR(14),    0x00000030 },
00618         { AR5K_RATE_DUR(15),    0x0000003c },
00619         { AR5K_RATE_DUR(16),    0x00000000 },
00620         { AR5K_RATE_DUR(17),    0x00000000 },
00621         { AR5K_RATE_DUR(18),    0x00000000 },
00622         { AR5K_RATE_DUR(19),    0x00000000 },
00623         { AR5K_RATE_DUR(20),    0x00000000 },
00624         { AR5K_RATE_DUR(21),    0x00000000 },
00625         { AR5K_RATE_DUR(22),    0x00000000 },
00626         { AR5K_RATE_DUR(23),    0x00000000 },
00627         { AR5K_RATE_DUR(24),    0x000000d5 },
00628         { AR5K_RATE_DUR(25),    0x000000df },
00629         { AR5K_RATE_DUR(26),    0x00000102 },
00630         { AR5K_RATE_DUR(27),    0x0000013a },
00631         { AR5K_RATE_DUR(28),    0x00000075 },
00632         { AR5K_RATE_DUR(29),    0x0000007f },
00633         { AR5K_RATE_DUR(30),    0x000000a2 },
00634         { AR5K_RATE_DUR(31),    0x00000000 },
00635         { AR5K_QUIET_CTL2,      0x00010002 },
00636         { AR5K_TSF_PARM,        0x00000001 },
00637         { AR5K_QOS_NOACK,       0x000000c0 },
00638         { AR5K_PHY_ERR_FIL,     0x00000000 },
00639         { AR5K_XRLAT_TX,        0x00000168 },
00640         { AR5K_ACKSIFS,         0x00000000 },
00641         /* Rate -> db table
00642          * notice ...03<-02<-01<-00 ! */
00643         { AR5K_RATE2DB(0),      0x03020100 },
00644         { AR5K_RATE2DB(1),      0x07060504 },
00645         { AR5K_RATE2DB(2),      0x0b0a0908 },
00646         { AR5K_RATE2DB(3),      0x0f0e0d0c },
00647         { AR5K_RATE2DB(4),      0x13121110 },
00648         { AR5K_RATE2DB(5),      0x17161514 },
00649         { AR5K_RATE2DB(6),      0x1b1a1918 },
00650         { AR5K_RATE2DB(7),      0x1f1e1d1c },
00651         /* Db -> Rate table */
00652         { AR5K_DB2RATE(0),      0x03020100 },
00653         { AR5K_DB2RATE(1),      0x07060504 },
00654         { AR5K_DB2RATE(2),      0x0b0a0908 },
00655         { AR5K_DB2RATE(3),      0x0f0e0d0c },
00656         { AR5K_DB2RATE(4),      0x13121110 },
00657         { AR5K_DB2RATE(5),      0x17161514 },
00658         { AR5K_DB2RATE(6),      0x1b1a1918 },
00659         { AR5K_DB2RATE(7),      0x1f1e1d1c },
00660         /* PHY registers (Common settings
00661          * for all chips/modes) */
00662         { AR5K_PHY(3),          0xad848e19 },
00663         { AR5K_PHY(4),          0x7d28e000 },
00664         { AR5K_PHY_TIMING_3,    0x9c0a9f6b },
00665         { AR5K_PHY_ACT,         0x00000000 },
00666         { AR5K_PHY(16),         0x206a017a },
00667         { AR5K_PHY(21),         0x00000859 },
00668         { AR5K_PHY_BIN_MASK_1,  0x00000000 },
00669         { AR5K_PHY_BIN_MASK_2,  0x00000000 },
00670         { AR5K_PHY_BIN_MASK_3,  0x00000000 },
00671         { AR5K_PHY_BIN_MASK_CTL, 0x00800000 },
00672         { AR5K_PHY_ANT_CTL,     0x00000001 },
00673         /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */
00674         { AR5K_PHY_MAX_RX_LEN,  0x00000c80 },
00675         { AR5K_PHY_IQ,          0x05100000 },
00676         { AR5K_PHY_WARM_RESET,  0x00000001 },
00677         { AR5K_PHY_CTL,         0x00000004 },
00678         { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },
00679         { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },
00680         { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },
00681         { AR5K_PHY(82),         0x9280b212 },
00682         { AR5K_PHY_RADAR,       0x5d50e188 },
00683         /*{ AR5K_PHY(86), 0x000000ff },*/
00684         { AR5K_PHY(87),         0x004b6a8e },
00685         { AR5K_PHY_NFTHRES,     0x000003ce },
00686         { AR5K_PHY_RESTART,     0x192fb515 },
00687         { AR5K_PHY(94),         0x00000001 },
00688         { AR5K_PHY_RFBUS_REQ,   0x00000000 },
00689         /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */
00690         /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */
00691         { AR5K_PHY(644),        0x00806333 },
00692         { AR5K_PHY(645),        0x00106c10 },
00693         { AR5K_PHY(646),        0x009c4060 },
00694         /* { AR5K_PHY(647), 0x1483800a }, */
00695         /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */
00696         { AR5K_PHY(648),        0x018830c6 },
00697         { AR5K_PHY(649),        0x00000400 },
00698         /*{ AR5K_PHY(650), 0x000001b5 },*/
00699         { AR5K_PHY(651),        0x00000000 },
00700         { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
00701         { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
00702         /*{ AR5K_PHY(655), 0x13c889af },*/
00703         { AR5K_PHY(656),        0x38490a20 },
00704         { AR5K_PHY(657),        0x00007bb6 },
00705         { AR5K_PHY(658),        0x0fff3ffc },
00706 };
00707 
00708 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
00709 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
00710         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
00711         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00712            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00713         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
00714            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00715         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
00716            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00717         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
00718            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00719         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
00720            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00721         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
00722            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00723         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
00724            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00725         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
00726            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00727         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
00728            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00729         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
00730            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00731         { AR5K_DCU_GBL_IFS_SIFS,
00732            { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
00733         { AR5K_DCU_GBL_IFS_SLOT,
00734            { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
00735         { AR5K_DCU_GBL_IFS_EIFS,
00736            { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
00737         { AR5K_DCU_GBL_IFS_MISC,
00738            { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
00739         { AR5K_TIME_OUT,
00740            { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
00741         { AR5K_PHY_TURBO,
00742            { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
00743         { AR5K_PHY(8),
00744            { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
00745         { AR5K_PHY_RF_CTL2,
00746            { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
00747         { AR5K_PHY_SETTLING,
00748            { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
00749         { AR5K_PHY_AGCCTL,
00750            { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
00751         { AR5K_PHY_NF,
00752            { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
00753         { AR5K_PHY_WEAK_OFDM_HIGH_THR,
00754            { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
00755         { AR5K_PHY(70),
00756            { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
00757         { AR5K_PHY_OFDM_SELFCORR,
00758            { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
00759         { 0xa230,
00760            { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
00761 };
00762 
00763 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
00764 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
00765         { AR5K_TXCFG,
00766         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00767            { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
00768         { AR5K_USEC_5211,
00769            { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
00770         { AR5K_PHY_RF_CTL3,
00771            { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
00772         { AR5K_PHY_RF_CTL4,
00773            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00774         { AR5K_PHY_PA_CTL,
00775            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00776         { AR5K_PHY_GAIN,
00777            { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
00778         { AR5K_PHY_DESIRED_SIZE,
00779            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
00780         { AR5K_PHY_SIG,
00781            { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
00782         { AR5K_PHY_AGCCOARSE,
00783            { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
00784         { AR5K_PHY_WEAK_OFDM_LOW_THR,
00785            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
00786         { AR5K_PHY_RX_DELAY,
00787            { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
00788         { AR5K_PHY_FRAME_CTL_5211,
00789            { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
00790         { AR5K_PHY_GAIN_2GHZ,
00791            { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
00792         { AR5K_PHY_CCK_RX_CTL_4,
00793            { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
00794 };
00795 
00796 static const struct ath5k_ini rf5111_ini_common_end[] = {
00797         { AR5K_DCU_FP,          0x00000000 },
00798         { AR5K_PHY_AGC,         0x00000000 },
00799         { AR5K_PHY_ADC_CTL,     0x00022ffe },
00800         { 0x983c,               0x00020100 },
00801         { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
00802         { AR5K_PHY_PAPD_PROBE,  0x00004883 },
00803         { 0x9940,               0x00000004 },
00804         { 0x9958,               0x000000ff },
00805         { 0x9974,               0x00000000 },
00806         { AR5K_PHY_SPENDING,    0x00000018 },
00807         { AR5K_PHY_CCKTXCTL,    0x00000000 },
00808         { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
00809         { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
00810         { 0xa23c,               0x13c889af },
00811 };
00812 
00813 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
00814 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
00815         { AR5K_TXCFG,
00816         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00817            { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
00818         { AR5K_USEC_5211,
00819            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00820         { AR5K_PHY_RF_CTL3,
00821            { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
00822         { AR5K_PHY_RF_CTL4,
00823            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00824         { AR5K_PHY_PA_CTL,
00825            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00826         { AR5K_PHY_GAIN,
00827            { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
00828         { AR5K_PHY_DESIRED_SIZE,
00829            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
00830         { AR5K_PHY_SIG,
00831            { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
00832         { AR5K_PHY_AGCCOARSE,
00833            { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
00834         { AR5K_PHY_WEAK_OFDM_LOW_THR,
00835            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
00836         { AR5K_PHY_RX_DELAY,
00837            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
00838         { AR5K_PHY_FRAME_CTL_5211,
00839            { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
00840         { AR5K_PHY_CCKTXCTL,
00841            { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
00842         { AR5K_PHY_CCK_CROSSCORR,
00843            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
00844         { AR5K_PHY_GAIN_2GHZ,
00845            { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
00846         { AR5K_PHY_CCK_RX_CTL_4,
00847            { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
00848 };
00849 
00850 static const struct ath5k_ini rf5112_ini_common_end[] = {
00851         { AR5K_DCU_FP,          0x00000000 },
00852         { AR5K_PHY_AGC,         0x00000000 },
00853         { AR5K_PHY_ADC_CTL,     0x00022ffe },
00854         { 0x983c,               0x00020100 },
00855         { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
00856         { AR5K_PHY_PAPD_PROBE,  0x00004882 },
00857         { 0x9940,               0x00000004 },
00858         { 0x9958,               0x000000ff },
00859         { 0x9974,               0x00000000 },
00860         { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
00861         { 0xa23c,               0x13c889af },
00862 };
00863 
00864 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
00865 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
00866         { AR5K_TXCFG,
00867         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00868            { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
00869         { AR5K_USEC_5211,
00870            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00871         { AR5K_PHY_RF_CTL3,
00872            { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
00873         { AR5K_PHY_RF_CTL4,
00874            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00875         { AR5K_PHY_PA_CTL,
00876            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00877         { AR5K_PHY_GAIN,
00878            { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
00879         { AR5K_PHY_DESIRED_SIZE,
00880            { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
00881         { AR5K_PHY_SIG,
00882            { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
00883         { AR5K_PHY_AGCCOARSE,
00884            { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
00885         { AR5K_PHY_WEAK_OFDM_LOW_THR,
00886            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
00887         { AR5K_PHY_RX_DELAY,
00888            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
00889         { AR5K_PHY_FRAME_CTL_5211,
00890            { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
00891         { AR5K_PHY_CCKTXCTL,
00892            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
00893         { AR5K_PHY_CCK_CROSSCORR,
00894            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
00895         { AR5K_PHY_GAIN_2GHZ,
00896            { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
00897         { AR5K_PHY_CCK_RX_CTL_4,
00898            { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
00899         { 0xa300,
00900            { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
00901         { 0xa304,
00902            { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
00903         { 0xa308,
00904            { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
00905         { 0xa30c,
00906            { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
00907         { 0xa310,
00908            { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
00909         { 0xa314,
00910            { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
00911         { 0xa318,
00912            { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
00913         { 0xa31c,
00914            { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
00915         { 0xa320,
00916            { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
00917         { 0xa324,
00918            { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
00919         { 0xa328,
00920            { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
00921         { 0xa32c,
00922            { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
00923         { 0xa330,
00924            { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
00925         { 0xa334,
00926            { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
00927 };
00928 
00929 static const struct ath5k_ini rf5413_ini_common_end[] = {
00930         { AR5K_DCU_FP,          0x000003e0 },
00931         { AR5K_5414_CBCFG,      0x00000010 },
00932         { AR5K_SEQ_MASK,        0x0000000f },
00933         { 0x809c,               0x00000000 },
00934         { 0x80a0,               0x00000000 },
00935         { AR5K_MIC_QOS_CTL,     0x00000000 },
00936         { AR5K_MIC_QOS_SEL,     0x00000000 },
00937         { AR5K_MISC_MODE,       0x00000000 },
00938         { AR5K_OFDM_FIL_CNT,    0x00000000 },
00939         { AR5K_CCK_FIL_CNT,     0x00000000 },
00940         { AR5K_PHYERR_CNT1,     0x00000000 },
00941         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
00942         { AR5K_PHYERR_CNT2,     0x00000000 },
00943         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
00944         { AR5K_TSF_THRES,       0x00000000 },
00945         { 0x8140,               0x800003f9 },
00946         { 0x8144,               0x00000000 },
00947         { AR5K_PHY_AGC,         0x00000000 },
00948         { AR5K_PHY_ADC_CTL,     0x0000a000 },
00949         { 0x983c,               0x00200400 },
00950         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
00951         { AR5K_PHY_SCR,         0x0000001f },
00952         { AR5K_PHY_SLMT,        0x00000080 },
00953         { AR5K_PHY_SCAL,        0x0000000e },
00954         { 0x9958,               0x00081fff },
00955         { AR5K_PHY_TIMING_7,    0x00000000 },
00956         { AR5K_PHY_TIMING_8,    0x02800000 },
00957         { AR5K_PHY_TIMING_11,   0x00000000 },
00958         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
00959         { 0x99e4,               0xaaaaaaaa },
00960         { 0x99e8,               0x3c466478 },
00961         { 0x99ec,               0x000000aa },
00962         { AR5K_PHY_SCLOCK,      0x0000000c },
00963         { AR5K_PHY_SDELAY,      0x000000ff },
00964         { AR5K_PHY_SPENDING,    0x00000014 },
00965         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
00966         { 0xa23c,               0x93c889af },
00967         { AR5K_PHY_FAST_ADC,    0x00000001 },
00968         { 0xa250,               0x0000a000 },
00969         { AR5K_PHY_BLUETOOTH,   0x00000000 },
00970         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
00971         { 0xa25c,               0x0f0f0f01 },
00972         { 0xa260,               0x5f690f01 },
00973         { 0xa264,               0x00418a11 },
00974         { 0xa268,               0x00000000 },
00975         { AR5K_PHY_TPC_RG5,     0x0c30c16a },
00976         { 0xa270, 0x00820820 },
00977         { 0xa274, 0x081b7caa },
00978         { 0xa278, 0x1ce739ce },
00979         { 0xa27c, 0x051701ce },
00980         { 0xa338, 0x00000000 },
00981         { 0xa33c, 0x00000000 },
00982         { 0xa340, 0x00000000 },
00983         { 0xa344, 0x00000000 },
00984         { 0xa348, 0x3fffffff },
00985         { 0xa34c, 0x3fffffff },
00986         { 0xa350, 0x3fffffff },
00987         { 0xa354, 0x0003ffff },
00988         { 0xa358, 0x79a8aa1f },
00989         { 0xa35c, 0x066c420f },
00990         { 0xa360, 0x0f282207 },
00991         { 0xa364, 0x17601685 },
00992         { 0xa368, 0x1f801104 },
00993         { 0xa36c, 0x37a00c03 },
00994         { 0xa370, 0x3fc40883 },
00995         { 0xa374, 0x57c00803 },
00996         { 0xa378, 0x5fd80682 },
00997         { 0xa37c, 0x7fe00482 },
00998         { 0xa380, 0x7f3c7bba },
00999         { 0xa384, 0xf3307ff0 },
01000 };
01001 
01002 /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
01003 /* XXX: a mode ? */
01004 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
01005         { AR5K_TXCFG,
01006         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
01007            { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
01008         { AR5K_USEC_5211,
01009            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
01010         { AR5K_PHY_RF_CTL3,
01011            { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
01012         { AR5K_PHY_RF_CTL4,
01013            { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
01014         { AR5K_PHY_PA_CTL,
01015            { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
01016         { AR5K_PHY_GAIN,
01017            { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
01018         { AR5K_PHY_DESIRED_SIZE,
01019            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
01020         { AR5K_PHY_SIG,
01021            { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
01022         { AR5K_PHY_AGCCOARSE,
01023            { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
01024         { AR5K_PHY_WEAK_OFDM_LOW_THR,
01025            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
01026         { AR5K_PHY_RX_DELAY,
01027            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
01028         { AR5K_PHY_FRAME_CTL_5211,
01029            { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
01030         { AR5K_PHY_CCKTXCTL,
01031            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
01032         { AR5K_PHY_CCK_CROSSCORR,
01033            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
01034         { AR5K_PHY_GAIN_2GHZ,
01035            { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
01036         { AR5K_PHY_CCK_RX_CTL_4,
01037            { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
01038 };
01039 
01040 static const struct ath5k_ini rf2413_ini_common_end[] = {
01041         { AR5K_DCU_FP,          0x000003e0 },
01042         { AR5K_SEQ_MASK,        0x0000000f },
01043         { AR5K_MIC_QOS_CTL,     0x00000000 },
01044         { AR5K_MIC_QOS_SEL,     0x00000000 },
01045         { AR5K_MISC_MODE,       0x00000000 },
01046         { AR5K_OFDM_FIL_CNT,    0x00000000 },
01047         { AR5K_CCK_FIL_CNT,     0x00000000 },
01048         { AR5K_PHYERR_CNT1,     0x00000000 },
01049         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
01050         { AR5K_PHYERR_CNT2,     0x00000000 },
01051         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
01052         { AR5K_TSF_THRES,       0x00000000 },
01053         { 0x8140,               0x800000a8 },
01054         { 0x8144,               0x00000000 },
01055         { AR5K_PHY_AGC,         0x00000000 },
01056         { AR5K_PHY_ADC_CTL,     0x0000a000 },
01057         { 0x983c,               0x00200400 },
01058         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
01059         { AR5K_PHY_SCR,         0x0000001f },
01060         { AR5K_PHY_SLMT,        0x00000080 },
01061         { AR5K_PHY_SCAL,        0x0000000e },
01062         { 0x9958,               0x000000ff },
01063         { AR5K_PHY_TIMING_7,    0x00000000 },
01064         { AR5K_PHY_TIMING_8,    0x02800000 },
01065         { AR5K_PHY_TIMING_11,   0x00000000 },
01066         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
01067         { 0x99e4,               0xaaaaaaaa },
01068         { 0x99e8,               0x3c466478 },
01069         { 0x99ec,               0x000000aa },
01070         { AR5K_PHY_SCLOCK,      0x0000000c },
01071         { AR5K_PHY_SDELAY,      0x000000ff },
01072         { AR5K_PHY_SPENDING,    0x00000014 },
01073         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
01074         { 0xa23c,               0x93c889af },
01075         { AR5K_PHY_FAST_ADC,    0x00000001 },
01076         { 0xa250,               0x0000a000 },
01077         { AR5K_PHY_BLUETOOTH,   0x00000000 },
01078         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
01079         { 0xa25c,               0x0f0f0f01 },
01080         { 0xa260,               0x5f690f01 },
01081         { 0xa264,               0x00418a11 },
01082         { 0xa268,               0x00000000 },
01083         { AR5K_PHY_TPC_RG5,     0x0c30c16a },
01084         { 0xa270, 0x00820820 },
01085         { 0xa274, 0x001b7caa },
01086         { 0xa278, 0x1ce739ce },
01087         { 0xa27c, 0x051701ce },
01088         { 0xa300, 0x18010000 },
01089         { 0xa304, 0x30032602 },
01090         { 0xa308, 0x48073e06 },
01091         { 0xa30c, 0x560b4c0a },
01092         { 0xa310, 0x641a600f },
01093         { 0xa314, 0x784f6e1b },
01094         { 0xa318, 0x868f7c5a },
01095         { 0xa31c, 0x8ecf865b },
01096         { 0xa320, 0x9d4f970f },
01097         { 0xa324, 0xa5cfa18f },
01098         { 0xa328, 0xb55faf1f },
01099         { 0xa32c, 0xbddfb99f },
01100         { 0xa330, 0xcd7fc73f },
01101         { 0xa334, 0xd5ffd1bf },
01102         { 0xa338, 0x00000000 },
01103         { 0xa33c, 0x00000000 },
01104         { 0xa340, 0x00000000 },
01105         { 0xa344, 0x00000000 },
01106         { 0xa348, 0x3fffffff },
01107         { 0xa34c, 0x3fffffff },
01108         { 0xa350, 0x3fffffff },
01109         { 0xa354, 0x0003ffff },
01110         { 0xa358, 0x79a8aa1f },
01111         { 0xa35c, 0x066c420f },
01112         { 0xa360, 0x0f282207 },
01113         { 0xa364, 0x17601685 },
01114         { 0xa368, 0x1f801104 },
01115         { 0xa36c, 0x37a00c03 },
01116         { 0xa370, 0x3fc40883 },
01117         { 0xa374, 0x57c00803 },
01118         { 0xa378, 0x5fd80682 },
01119         { 0xa37c, 0x7fe00482 },
01120         { 0xa380, 0x7f3c7bba },
01121         { 0xa384, 0xf3307ff0 },
01122 };
01123 
01124 /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
01125 /* XXX: a mode ? */
01126 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
01127         { AR5K_TXCFG,
01128         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
01129            { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
01130         { AR5K_USEC_5211,
01131            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
01132         { AR5K_PHY_TURBO,
01133            { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
01134         { AR5K_PHY_RF_CTL3,
01135            { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
01136         { AR5K_PHY_RF_CTL4,
01137            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
01138         { AR5K_PHY_PA_CTL,
01139            { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
01140         { AR5K_PHY_SETTLING,
01141            { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
01142         { AR5K_PHY_GAIN,
01143            { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
01144         { AR5K_PHY_DESIRED_SIZE,
01145            { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
01146         { AR5K_PHY_SIG,
01147            { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
01148         { AR5K_PHY_AGCCOARSE,
01149            { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
01150         { AR5K_PHY_WEAK_OFDM_LOW_THR,
01151            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
01152         { AR5K_PHY_RX_DELAY,
01153            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
01154         { AR5K_PHY_FRAME_CTL_5211,
01155            { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
01156         { AR5K_PHY_CCKTXCTL,
01157            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
01158         { AR5K_PHY_CCK_CROSSCORR,
01159            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
01160         { AR5K_PHY_GAIN_2GHZ,
01161            { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
01162         { AR5K_PHY_CCK_RX_CTL_4,
01163            { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
01164         { 0xa324,
01165            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01166         { 0xa328,
01167            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01168         { 0xa32c,
01169            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01170         { 0xa330,
01171            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01172         { 0xa334,
01173            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01174 };
01175 
01176 static const struct ath5k_ini rf2425_ini_common_end[] = {
01177         { AR5K_DCU_FP,          0x000003e0 },
01178         { AR5K_SEQ_MASK,        0x0000000f },
01179         { 0x809c,               0x00000000 },
01180         { 0x80a0,               0x00000000 },
01181         { AR5K_MIC_QOS_CTL,     0x00000000 },
01182         { AR5K_MIC_QOS_SEL,     0x00000000 },
01183         { AR5K_MISC_MODE,       0x00000000 },
01184         { AR5K_OFDM_FIL_CNT,    0x00000000 },
01185         { AR5K_CCK_FIL_CNT,     0x00000000 },
01186         { AR5K_PHYERR_CNT1,     0x00000000 },
01187         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
01188         { AR5K_PHYERR_CNT2,     0x00000000 },
01189         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
01190         { AR5K_TSF_THRES,       0x00000000 },
01191         { 0x8140,               0x800003f9 },
01192         { 0x8144,               0x00000000 },
01193         { AR5K_PHY_AGC,         0x00000000 },
01194         { AR5K_PHY_ADC_CTL,     0x0000a000 },
01195         { 0x983c,               0x00200400 },
01196         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
01197         { AR5K_PHY_SCR,         0x0000001f },
01198         { AR5K_PHY_SLMT,        0x00000080 },
01199         { AR5K_PHY_SCAL,        0x0000000e },
01200         { 0x9958,               0x00081fff },
01201         { AR5K_PHY_TIMING_7,    0x00000000 },
01202         { AR5K_PHY_TIMING_8,    0x02800000 },
01203         { AR5K_PHY_TIMING_11,   0x00000000 },
01204         { 0x99dc,               0xfebadbe8 },
01205         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
01206         { 0x99e4,               0xaaaaaaaa },
01207         { 0x99e8,               0x3c466478 },
01208         { 0x99ec,               0x000000aa },
01209         { AR5K_PHY_SCLOCK,      0x0000000c },
01210         { AR5K_PHY_SDELAY,      0x000000ff },
01211         { AR5K_PHY_SPENDING,    0x00000014 },
01212         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
01213         { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
01214         { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
01215         { 0xa23c,               0x93c889af },
01216         { AR5K_PHY_FAST_ADC,    0x00000001 },
01217         { 0xa250,               0x0000a000 },
01218         { AR5K_PHY_BLUETOOTH,   0x00000000 },
01219         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
01220         { 0xa25c,               0x0f0f0f01 },
01221         { 0xa260,               0x5f690f01 },
01222         { 0xa264,               0x00418a11 },
01223         { 0xa268,               0x00000000 },
01224         { AR5K_PHY_TPC_RG5,     0x0c30c166 },
01225         { 0xa270, 0x00820820 },
01226         { 0xa274, 0x081a3caa },
01227         { 0xa278, 0x1ce739ce },
01228         { 0xa27c, 0x051701ce },
01229         { 0xa300, 0x16010000 },
01230         { 0xa304, 0x2c032402 },
01231         { 0xa308, 0x48433e42 },
01232         { 0xa30c, 0x5a0f500b },
01233         { 0xa310, 0x6c4b624a },
01234         { 0xa314, 0x7e8b748a },
01235         { 0xa318, 0x96cf8ccb },
01236         { 0xa31c, 0xa34f9d0f },
01237         { 0xa320, 0xa7cfa58f },
01238         { 0xa348, 0x3fffffff },
01239         { 0xa34c, 0x3fffffff },
01240         { 0xa350, 0x3fffffff },
01241         { 0xa354, 0x0003ffff },
01242         { 0xa358, 0x79a8aa1f },
01243         { 0xa35c, 0x066c420f },
01244         { 0xa360, 0x0f282207 },
01245         { 0xa364, 0x17601685 },
01246         { 0xa368, 0x1f801104 },
01247         { 0xa36c, 0x37a00c03 },
01248         { 0xa370, 0x3fc40883 },
01249         { 0xa374, 0x57c00803 },
01250         { 0xa378, 0x5fd80682 },
01251         { 0xa37c, 0x7fe00482 },
01252         { 0xa380, 0x7f3c7bba },
01253         { 0xa384, 0xf3307ff0 },
01254 };
01255 
01256 /*
01257  * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
01258  * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
01259  */
01260 
01261 /* RF5111 Initial BaseBand Gain settings */
01262 static const struct ath5k_ini rf5111_ini_bbgain[] = {
01263         { AR5K_BB_GAIN(0), 0x00000000 },
01264         { AR5K_BB_GAIN(1), 0x00000020 },
01265         { AR5K_BB_GAIN(2), 0x00000010 },
01266         { AR5K_BB_GAIN(3), 0x00000030 },
01267         { AR5K_BB_GAIN(4), 0x00000008 },
01268         { AR5K_BB_GAIN(5), 0x00000028 },
01269         { AR5K_BB_GAIN(6), 0x00000004 },
01270         { AR5K_BB_GAIN(7), 0x00000024 },
01271         { AR5K_BB_GAIN(8), 0x00000014 },
01272         { AR5K_BB_GAIN(9), 0x00000034 },
01273         { AR5K_BB_GAIN(10), 0x0000000c },
01274         { AR5K_BB_GAIN(11), 0x0000002c },
01275         { AR5K_BB_GAIN(12), 0x00000002 },
01276         { AR5K_BB_GAIN(13), 0x00000022 },
01277         { AR5K_BB_GAIN(14), 0x00000012 },
01278         { AR5K_BB_GAIN(15), 0x00000032 },
01279         { AR5K_BB_GAIN(16), 0x0000000a },
01280         { AR5K_BB_GAIN(17), 0x0000002a },
01281         { AR5K_BB_GAIN(18), 0x00000006 },
01282         { AR5K_BB_GAIN(19), 0x00000026 },
01283         { AR5K_BB_GAIN(20), 0x00000016 },
01284         { AR5K_BB_GAIN(21), 0x00000036 },
01285         { AR5K_BB_GAIN(22), 0x0000000e },
01286         { AR5K_BB_GAIN(23), 0x0000002e },
01287         { AR5K_BB_GAIN(24), 0x00000001 },
01288         { AR5K_BB_GAIN(25), 0x00000021 },
01289         { AR5K_BB_GAIN(26), 0x00000011 },
01290         { AR5K_BB_GAIN(27), 0x00000031 },
01291         { AR5K_BB_GAIN(28), 0x00000009 },
01292         { AR5K_BB_GAIN(29), 0x00000029 },
01293         { AR5K_BB_GAIN(30), 0x00000005 },
01294         { AR5K_BB_GAIN(31), 0x00000025 },
01295         { AR5K_BB_GAIN(32), 0x00000015 },
01296         { AR5K_BB_GAIN(33), 0x00000035 },
01297         { AR5K_BB_GAIN(34), 0x0000000d },
01298         { AR5K_BB_GAIN(35), 0x0000002d },
01299         { AR5K_BB_GAIN(36), 0x00000003 },
01300         { AR5K_BB_GAIN(37), 0x00000023 },
01301         { AR5K_BB_GAIN(38), 0x00000013 },
01302         { AR5K_BB_GAIN(39), 0x00000033 },
01303         { AR5K_BB_GAIN(40), 0x0000000b },
01304         { AR5K_BB_GAIN(41), 0x0000002b },
01305         { AR5K_BB_GAIN(42), 0x0000002b },
01306         { AR5K_BB_GAIN(43), 0x0000002b },
01307         { AR5K_BB_GAIN(44), 0x0000002b },
01308         { AR5K_BB_GAIN(45), 0x0000002b },
01309         { AR5K_BB_GAIN(46), 0x0000002b },
01310         { AR5K_BB_GAIN(47), 0x0000002b },
01311         { AR5K_BB_GAIN(48), 0x0000002b },
01312         { AR5K_BB_GAIN(49), 0x0000002b },
01313         { AR5K_BB_GAIN(50), 0x0000002b },
01314         { AR5K_BB_GAIN(51), 0x0000002b },
01315         { AR5K_BB_GAIN(52), 0x0000002b },
01316         { AR5K_BB_GAIN(53), 0x0000002b },
01317         { AR5K_BB_GAIN(54), 0x0000002b },
01318         { AR5K_BB_GAIN(55), 0x0000002b },
01319         { AR5K_BB_GAIN(56), 0x0000002b },
01320         { AR5K_BB_GAIN(57), 0x0000002b },
01321         { AR5K_BB_GAIN(58), 0x0000002b },
01322         { AR5K_BB_GAIN(59), 0x0000002b },
01323         { AR5K_BB_GAIN(60), 0x0000002b },
01324         { AR5K_BB_GAIN(61), 0x0000002b },
01325         { AR5K_BB_GAIN(62), 0x00000002 },
01326         { AR5K_BB_GAIN(63), 0x00000016 },
01327 };
01328 
01329 /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
01330 static const struct ath5k_ini rf5112_ini_bbgain[] = {
01331         { AR5K_BB_GAIN(0), 0x00000000 },
01332         { AR5K_BB_GAIN(1), 0x00000001 },
01333         { AR5K_BB_GAIN(2), 0x00000002 },
01334         { AR5K_BB_GAIN(3), 0x00000003 },
01335         { AR5K_BB_GAIN(4), 0x00000004 },
01336         { AR5K_BB_GAIN(5), 0x00000005 },
01337         { AR5K_BB_GAIN(6), 0x00000008 },
01338         { AR5K_BB_GAIN(7), 0x00000009 },
01339         { AR5K_BB_GAIN(8), 0x0000000a },
01340         { AR5K_BB_GAIN(9), 0x0000000b },
01341         { AR5K_BB_GAIN(10), 0x0000000c },
01342         { AR5K_BB_GAIN(11), 0x0000000d },
01343         { AR5K_BB_GAIN(12), 0x00000010 },
01344         { AR5K_BB_GAIN(13), 0x00000011 },
01345         { AR5K_BB_GAIN(14), 0x00000012 },
01346         { AR5K_BB_GAIN(15), 0x00000013 },
01347         { AR5K_BB_GAIN(16), 0x00000014 },
01348         { AR5K_BB_GAIN(17), 0x00000015 },
01349         { AR5K_BB_GAIN(18), 0x00000018 },
01350         { AR5K_BB_GAIN(19), 0x00000019 },
01351         { AR5K_BB_GAIN(20), 0x0000001a },
01352         { AR5K_BB_GAIN(21), 0x0000001b },
01353         { AR5K_BB_GAIN(22), 0x0000001c },
01354         { AR5K_BB_GAIN(23), 0x0000001d },
01355         { AR5K_BB_GAIN(24), 0x00000020 },
01356         { AR5K_BB_GAIN(25), 0x00000021 },
01357         { AR5K_BB_GAIN(26), 0x00000022 },
01358         { AR5K_BB_GAIN(27), 0x00000023 },
01359         { AR5K_BB_GAIN(28), 0x00000024 },
01360         { AR5K_BB_GAIN(29), 0x00000025 },
01361         { AR5K_BB_GAIN(30), 0x00000028 },
01362         { AR5K_BB_GAIN(31), 0x00000029 },
01363         { AR5K_BB_GAIN(32), 0x0000002a },
01364         { AR5K_BB_GAIN(33), 0x0000002b },
01365         { AR5K_BB_GAIN(34), 0x0000002c },
01366         { AR5K_BB_GAIN(35), 0x0000002d },
01367         { AR5K_BB_GAIN(36), 0x00000030 },
01368         { AR5K_BB_GAIN(37), 0x00000031 },
01369         { AR5K_BB_GAIN(38), 0x00000032 },
01370         { AR5K_BB_GAIN(39), 0x00000033 },
01371         { AR5K_BB_GAIN(40), 0x00000034 },
01372         { AR5K_BB_GAIN(41), 0x00000035 },
01373         { AR5K_BB_GAIN(42), 0x00000035 },
01374         { AR5K_BB_GAIN(43), 0x00000035 },
01375         { AR5K_BB_GAIN(44), 0x00000035 },
01376         { AR5K_BB_GAIN(45), 0x00000035 },
01377         { AR5K_BB_GAIN(46), 0x00000035 },
01378         { AR5K_BB_GAIN(47), 0x00000035 },
01379         { AR5K_BB_GAIN(48), 0x00000035 },
01380         { AR5K_BB_GAIN(49), 0x00000035 },
01381         { AR5K_BB_GAIN(50), 0x00000035 },
01382         { AR5K_BB_GAIN(51), 0x00000035 },
01383         { AR5K_BB_GAIN(52), 0x00000035 },
01384         { AR5K_BB_GAIN(53), 0x00000035 },
01385         { AR5K_BB_GAIN(54), 0x00000035 },
01386         { AR5K_BB_GAIN(55), 0x00000035 },
01387         { AR5K_BB_GAIN(56), 0x00000035 },
01388         { AR5K_BB_GAIN(57), 0x00000035 },
01389         { AR5K_BB_GAIN(58), 0x00000035 },
01390         { AR5K_BB_GAIN(59), 0x00000035 },
01391         { AR5K_BB_GAIN(60), 0x00000035 },
01392         { AR5K_BB_GAIN(61), 0x00000035 },
01393         { AR5K_BB_GAIN(62), 0x00000010 },
01394         { AR5K_BB_GAIN(63), 0x0000001a },
01395 };
01396 
01397 
01398 /*
01399  * Write initial register dump
01400  */
01401 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
01402                 const struct ath5k_ini *ini_regs, bool change_channel)
01403 {
01404         unsigned int i;
01405 
01406         /* Write initial registers */
01407         for (i = 0; i < size; i++) {
01408                 /* On channel change there is
01409                  * no need to mess with PCU */
01410                 if (change_channel &&
01411                                 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
01412                                 ini_regs[i].ini_register <= AR5K_PCU_MAX)
01413                         continue;
01414 
01415                 switch (ini_regs[i].ini_mode) {
01416                 case AR5K_INI_READ:
01417                         /* Cleared on read */
01418                         ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
01419                         break;
01420                 case AR5K_INI_WRITE:
01421                 default:
01422                         AR5K_REG_WAIT(i);
01423                         ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
01424                                         ini_regs[i].ini_register);
01425                 }
01426         }
01427 }
01428 
01429 static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
01430                 unsigned int size, const struct ath5k_ini_mode *ini_mode,
01431                 u8 mode)
01432 {
01433         unsigned int i;
01434 
01435         for (i = 0; i < size; i++) {
01436                 AR5K_REG_WAIT(i);
01437                 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
01438                         (u32)ini_mode[i].mode_register);
01439         }
01440 
01441 }
01442 
01443 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
01444 {
01445         /*
01446          * Write initial register settings
01447          */
01448 
01449         /* For AR5212 and combatible */
01450         if (ah->ah_version == AR5K_AR5212) {
01451 
01452                 /* First set of mode-specific settings */
01453                 ath5k_hw_ini_mode_registers(ah,
01454                         ARRAY_SIZE(ar5212_ini_mode_start),
01455                         ar5212_ini_mode_start, mode);
01456 
01457                 /*
01458                  * Write initial settings common for all modes
01459                  */
01460                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
01461                                 ar5212_ini_common_start, change_channel);
01462 
01463                 /* Second set of mode-specific settings */
01464                 switch (ah->ah_radio) {
01465                 case AR5K_RF5111:
01466 
01467                         ath5k_hw_ini_mode_registers(ah,
01468                                         ARRAY_SIZE(rf5111_ini_mode_end),
01469                                         rf5111_ini_mode_end, mode);
01470 
01471                         ath5k_hw_ini_registers(ah,
01472                                         ARRAY_SIZE(rf5111_ini_common_end),
01473                                         rf5111_ini_common_end, change_channel);
01474 
01475                         /* Baseband gain table */
01476                         ath5k_hw_ini_registers(ah,
01477                                         ARRAY_SIZE(rf5111_ini_bbgain),
01478                                         rf5111_ini_bbgain, change_channel);
01479 
01480                         break;
01481                 case AR5K_RF5112:
01482 
01483                         ath5k_hw_ini_mode_registers(ah,
01484                                         ARRAY_SIZE(rf5112_ini_mode_end),
01485                                         rf5112_ini_mode_end, mode);
01486 
01487                         ath5k_hw_ini_registers(ah,
01488                                         ARRAY_SIZE(rf5112_ini_common_end),
01489                                         rf5112_ini_common_end, change_channel);
01490 
01491                         ath5k_hw_ini_registers(ah,
01492                                         ARRAY_SIZE(rf5112_ini_bbgain),
01493                                         rf5112_ini_bbgain, change_channel);
01494 
01495                         break;
01496                 case AR5K_RF5413:
01497 
01498                         ath5k_hw_ini_mode_registers(ah,
01499                                         ARRAY_SIZE(rf5413_ini_mode_end),
01500                                         rf5413_ini_mode_end, mode);
01501 
01502                         ath5k_hw_ini_registers(ah,
01503                                         ARRAY_SIZE(rf5413_ini_common_end),
01504                                         rf5413_ini_common_end, change_channel);
01505 
01506                         ath5k_hw_ini_registers(ah,
01507                                         ARRAY_SIZE(rf5112_ini_bbgain),
01508                                         rf5112_ini_bbgain, change_channel);
01509 
01510                         break;
01511                 case AR5K_RF2316:
01512                 case AR5K_RF2413:
01513 
01514                         ath5k_hw_ini_mode_registers(ah,
01515                                         ARRAY_SIZE(rf2413_ini_mode_end),
01516                                         rf2413_ini_mode_end, mode);
01517 
01518                         ath5k_hw_ini_registers(ah,
01519                                         ARRAY_SIZE(rf2413_ini_common_end),
01520                                         rf2413_ini_common_end, change_channel);
01521 
01522                         /* Override settings from rf2413_ini_common_end */
01523                         if (ah->ah_radio == AR5K_RF2316) {
01524                                 ath5k_hw_reg_write(ah, 0x00004000,
01525                                                         AR5K_PHY_AGC);
01526                                 ath5k_hw_reg_write(ah, 0x081b7caa,
01527                                                         0xa274);
01528                         }
01529 
01530                         ath5k_hw_ini_registers(ah,
01531                                         ARRAY_SIZE(rf5112_ini_bbgain),
01532                                         rf5112_ini_bbgain, change_channel);
01533                         break;
01534                 case AR5K_RF2317:
01535                 case AR5K_RF2425:
01536 
01537                         ath5k_hw_ini_mode_registers(ah,
01538                                         ARRAY_SIZE(rf2425_ini_mode_end),
01539                                         rf2425_ini_mode_end, mode);
01540 
01541                         ath5k_hw_ini_registers(ah,
01542                                         ARRAY_SIZE(rf2425_ini_common_end),
01543                                         rf2425_ini_common_end, change_channel);
01544 
01545                         ath5k_hw_ini_registers(ah,
01546                                         ARRAY_SIZE(rf5112_ini_bbgain),
01547                                         rf5112_ini_bbgain, change_channel);
01548                         break;
01549                 default:
01550                         return -EINVAL;
01551 
01552                 }
01553 
01554         /* For AR5211 */
01555         } else if (ah->ah_version == AR5K_AR5211) {
01556 
01557                 /* AR5K_MODE_11B */
01558                 if (mode > 2) {
01559                         ATH5K_ERR(ah->ah_sc,
01560                                 "unsupported channel mode: %d\n", mode);
01561                         return -EINVAL;
01562                 }
01563 
01564                 /* Mode-specific settings */
01565                 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
01566                                 ar5211_ini_mode, mode);
01567 
01568                 /*
01569                  * Write initial settings common for all modes
01570                  */
01571                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
01572                                 ar5211_ini, change_channel);
01573 
01574                 /* AR5211 only comes with 5111 */
01575 
01576                 /* Baseband gain table */
01577                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
01578                                 rf5111_ini_bbgain, change_channel);
01579         /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
01580         } else if (ah->ah_version == AR5K_AR5210) {
01581                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
01582                                 ar5210_ini, change_channel);
01583         }
01584 
01585         return 0;
01586 }

ros_rt_wmp
Author(s): Danilo Tardioli, dantard@unizar.es
autogenerated on Mon Oct 6 2014 08:27:10