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Defines | |
| #define | UFCR_FIFO_ENABLE (1 << 0) |
| #define | UFCR_FIFO_TRIG1 (0 << 6) |
| #define | UFCR_FIFO_TRIG14 (3 << 6) |
| #define | UFCR_FIFO_TRIG4 (1 << 6) |
| #define | UFCR_FIFO_TRIG8 (2 << 6) |
| #define | UFCR_RX_FIFO_RESET (1 << 1) |
| #define | UFCR_TX_FIFO_RESET (1 << 2) |
| #define | UIER_EDSSI (1 << 3) |
| #define | UIER_ELSI (1 << 2) |
| #define | UIER_ERBFI (1 << 0) |
| #define | UIER_ETBEI (1 << 1) |
| #define | UIIR_CTI_INT (6 << 1) |
| #define | UIIR_ID_MASK 0x0E |
| #define | UIIR_MS_INT (0 << 1) |
| #define | UIIR_NO_INT (1 << 0) |
| #define | UIIR_RDA_INT (2 << 1) |
| #define | UIIR_RLS_INT (3 << 1) |
| #define | UIIR_THRE_INT (1 << 1) |
| #define | ULCR_BREAK_ENABLE (1 << 6) |
| #define | ULCR_CHAR_5 (0 << 0) |
| #define | ULCR_CHAR_6 (1 << 0) |
| #define | ULCR_CHAR_7 (2 << 0) |
| #define | ULCR_CHAR_8 (3 << 0) |
| #define | ULCR_DLAB_ENABLE (1 << 7) |
| #define | ULCR_PAR_EVEN (3 << 3) |
| #define | ULCR_PAR_MARK (5 << 3) |
| #define | ULCR_PAR_NO (0 << 3) |
| #define | ULCR_PAR_ODD (1 << 3) |
| #define | ULCR_PAR_SPACE (7 << 3) |
| #define | ULCR_STOP_1 (0 << 2) |
| #define | ULCR_STOP_2 (1 << 2) |
| #define | ULSR_BI (1 << 4) |
| #define | ULSR_ERR_MASK 0x1E |
| #define | ULSR_FE (1 << 3) |
| #define | ULSR_OE (1 << 1) |
| #define | ULSR_PE (1 << 2) |
| #define | ULSR_RDR (1 << 0) |
| #define | ULSR_RXFE (1 << 7) |
| #define | ULSR_TEMT (1 << 6) |
| #define | ULSR_THRE (1 << 5) |
| #define | UMCR_DTR (1 << 0) |
| #define | UMCR_LB (1 << 4) |
| #define | UMCR_RTS (1 << 1) |
| #define | UMSR_CTS (1 << 4) |
| #define | UMSR_DCD (1 << 7) |
| #define | UMSR_DCTS (1 << 0) |
| #define | UMSR_DDCD (1 << 3) |
| #define | UMSR_DDSR (1 << 1) |
| #define | UMSR_DSR (1 << 5) |
| #define | UMSR_RI (1 << 6) |
| #define | UMSR_TERI (1 << 2) |
Define Documentation
| #define UFCR_FIFO_ENABLE (1 << 0) |
| #define UFCR_FIFO_TRIG1 (0 << 6) |
| #define UFCR_FIFO_TRIG14 (3 << 6) |
| #define UFCR_FIFO_TRIG4 (1 << 6) |
| #define UFCR_FIFO_TRIG8 (2 << 6) |
| #define UFCR_RX_FIFO_RESET (1 << 1) |
| #define UFCR_TX_FIFO_RESET (1 << 2) |
| #define UIER_EDSSI (1 << 3) |
| #define UIER_ERBFI (1 << 0) |
| #define UIER_ETBEI (1 << 1) |
| #define UIIR_CTI_INT (6 << 1) |
| #define UIIR_ID_MASK 0x0E |
| #define UIIR_MS_INT (0 << 1) |
| #define UIIR_NO_INT (1 << 0) |
| #define UIIR_RDA_INT (2 << 1) |
| #define UIIR_RLS_INT (3 << 1) |
| #define UIIR_THRE_INT (1 << 1) |
| #define ULCR_BREAK_ENABLE (1 << 6) |
| #define ULCR_CHAR_5 (0 << 0) |
| #define ULCR_CHAR_6 (1 << 0) |
| #define ULCR_CHAR_7 (2 << 0) |
| #define ULCR_CHAR_8 (3 << 0) |
| #define ULCR_DLAB_ENABLE (1 << 7) |
| #define ULCR_PAR_EVEN (3 << 3) |
| #define ULCR_PAR_MARK (5 << 3) |
| #define ULCR_PAR_NO (0 << 3) |
| #define ULCR_PAR_ODD (1 << 3) |
| #define ULCR_PAR_SPACE (7 << 3) |
| #define ULCR_STOP_1 (0 << 2) |
| #define ULCR_STOP_2 (1 << 2) |
| #define ULSR_ERR_MASK 0x1E |