vl53l1_register_settings.h
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1 /*
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4 * This file is part of VL53L1 Core and is dual licensed,
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62 
69 #ifndef _VL53L1_REGISTER_SETTINGS_H_
70 #define _VL53L1_REGISTER_SETTINGS_H_
71 
72 
85 #define VL53L1_DEVICESCHEDULERMODE_PSEUDO_SOLO 0x00
86 #define VL53L1_DEVICESCHEDULERMODE_STREAMING 0x01
87 #define VL53L1_DEVICESCHEDULERMODE_HISTOGRAM 0x02
88 
97 #define VL53L1_DEVICEREADOUTMODE_SINGLE_SD (0x00 << 2)
98 #define VL53L1_DEVICEREADOUTMODE_DUAL_SD (0x01 << 2)
99 #define VL53L1_DEVICEREADOUTMODE_SPLIT_READOUT (0x02 << 2)
100 #define VL53L1_DEVICEREADOUTMODE_SPLIT_MANUAL (0x03 << 2)
101 
110 /*
111 #define VL53L1_DEVICEMEASUREMENTMODE_STOP 0x00
112 #define VL53L1_DEVICEMEASUREMENTMODE_SINGLESHOT 0x10
113 #define VL53L1_DEVICEMEASUREMENTMODE_BACKTOBACK 0x20
114 #define VL53L1_DEVICEMEASUREMENTMODE_TIMED 0x40
115 #define VL53L1_DEVICEMEASUREMENTMODE_ABORT 0x80
116 */
117 #define VL53L1_DEVICEMEASUREMENTMODE_MODE_MASK 0xF0
118 #define VL53L1_DEVICEMEASUREMENTMODE_STOP_MASK 0x0F
119 
120 #define VL53L1_GROUPEDPARAMETERHOLD_ID_MASK 0x02
121 
124 #define VL53L1_EWOK_I2C_DEV_ADDR_DEFAULT 0x29
125 
126 #define VL53L1_OSC_FREQUENCY 0x00
127 #define VL53L1_OSC_TRIM_DEFAULT 0x00
128 #define VL53L1_OSC_FREQ_SET_DEFAULT 0x00
129 
130 #define VL53L1_RANGE_HISTOGRAM_REF 0x08
131 #define VL53L1_RANGE_HISTOGRAM_RET 0x10
132 #define VL53L1_RANGE_HISTOGRAM_BOTH 0x18
133 #define VL53L1_RANGE_HISTOGRAM_INIT 0x20
134 #define VL53L1_RANGE_VHV_INIT 0x40
135 
136 /* Result Status */
137 #define VL53L1_RESULT_RANGE_STATUS 0x1F
138 
139 /* */
140 #define VL53L1_SYSTEM__SEED_CONFIG__MANUAL 0x00
141 #define VL53L1_SYSTEM__SEED_CONFIG__STANDARD 0x01
142 #define VL53L1_SYSTEM__SEED_CONFIG__EVEN_UPDATE_ONLY 0x02
143 
144 /* Interrupt Config */
145 #define VL53L1_INTERRUPT_CONFIG_LEVEL_LOW 0x00
146 #define VL53L1_INTERRUPT_CONFIG_LEVEL_HIGH 0x01
147 #define VL53L1_INTERRUPT_CONFIG_OUT_OF_WINDOW 0x02
148 #define VL53L1_INTERRUPT_CONFIG_IN_WINDOW 0x03
149 #define VL53L1_INTERRUPT_CONFIG_NEW_SAMPLE_READY 0x20
150 
151 /* Interrupt Clear */
152 #define VL53L1_CLEAR_RANGE_INT 0x01
153 #define VL53L1_CLEAR_ERROR_INT 0x02
154 
155 /* Sequence Config */
156 #define VL53L1_SEQUENCE_VHV_EN 0x01
157 #define VL53L1_SEQUENCE_PHASECAL_EN 0x02
158 #define VL53L1_SEQUENCE_REFERENCE_PHASE_EN 0x04
159 #define VL53L1_SEQUENCE_DSS1_EN 0x08
160 #define VL53L1_SEQUENCE_DSS2_EN 0x10
161 #define VL53L1_SEQUENCE_MM1_EN 0x20
162 #define VL53L1_SEQUENCE_MM2_EN 0x40
163 #define VL53L1_SEQUENCE_RANGE_EN 0x80
164 
165 /* defines for DSS__ROI_CONTROL */
166 #define VL53L1_DSS_CONTROL__ROI_SUBTRACT 0x20
167 #define VL53L1_DSS_CONTROL__ROI_INTERSECT 0x10
168 
169 #define VL53L1_DSS_CONTROL__MODE_DISABLED 0x00
170 #define VL53L1_DSS_CONTROL__MODE_TARGET_RATE 0x01
171 #define VL53L1_DSS_CONTROL__MODE_EFFSPADS 0x02
172 #define VL53L1_DSS_CONTROL__MODE_BLOCKSELECT 0x03
173 
174 /* SPAD Readout defines
175  *
176  * 7:6 - SPAD_IN_SEL_REF
177  * 5:4 - SPAD_IN_SEL_RTN
178  * 2 - SPAD_PS_BYPASS
179  * 0 - SPAD_EN_PULSE_EXTENDER
180  */
181 
182 #define VL53L1_RANGING_CORE__SPAD_READOUT__STANDARD 0x45
183 #define VL53L1_RANGING_CORE__SPAD_READOUT__RETURN_ARRAY_ONLY 0x05
184 #define VL53L1_RANGING_CORE__SPAD_READOUT__REFERENCE_ARRAY_ONLY 0x55
185 #define VL53L1_RANGING_CORE__SPAD_READOUT__RETURN_SPLIT_ARRAY 0x25
186 #define VL53L1_RANGING_CORE__SPAD_READOUT__CALIB_PULSES 0xF5
187 
188 
189 #define VL53L1_LASER_SAFETY__KEY_VALUE 0x6C
190 
191 /* Range Status defines
192  *
193  * 7 - GPH ID
194  * 6 - Min threshold hit
195  * 5 - Max threshold hit
196  * 4:0 - Range Status
197  */
198 
199 #define VL53L1_RANGE_STATUS__RANGE_STATUS_MASK 0x1F
200 #define VL53L1_RANGE_STATUS__MAX_THRESHOLD_HIT_MASK 0x20
201 #define VL53L1_RANGE_STATUS__MIN_THRESHOLD_HIT_MASK 0x40
202 #define VL53L1_RANGE_STATUS__GPH_ID_RANGE_STATUS_MASK 0x80
203 
204 /* Interrupt Status defines
205  *
206  * 5 - GPH ID
207  * 4:3 - Interrupt Error Status
208  * 2:0 - Interrupt Status
209  */
210 
211 #define VL53L1_INTERRUPT_STATUS__INT_STATUS_MASK 0x07
212 #define VL53L1_INTERRUPT_STATUS__INT_ERROR_STATUS_MASK 0x18
213 #define VL53L1_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK 0x20
214 
218 #endif
219 
220 /* _VL53L1_REGISTER_SETTINGS_H_ */
221 
222 

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autogenerated on Fri Aug 2 2024 08:35:54